82571EB [INTEL]
Gigabit Ethernet Controller; 千兆位以太网控制器
| 型号： | 82571EB |
| 厂家： | 
INTEL |
| 描述： | Gigabit Ethernet Controller |
| 文件： | 总58页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82571EB/82572EI Gigabit Ethernet
Controller
Networking Silicon
Product Datasheet
Revision 1.2
August 2006
ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF
SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY,
RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel product(s) referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may
require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by
visiting Intel's website at http://www.intel.com.
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © Intel Corporation, 2003 - 2006
*Other names and brands may be claimed as the property of others.
ii
Product Datasheet
82571EB/82572 Gigabit Ethernet Controller
Revision History
Date
Revision
Notes
Oct 2002
0.15
Initial Release
Revised ballout, added package drawing, added visual pin descriptions, changed some
ball names to “EXP” ball naming convention.
Feb 2003
Aug 2003
0.5
0.6
•
•
•
•
Updated power specifications.
Changed names to “PE” naming convention
Revised signal descriptions, pinout information tables, and ballout grid.
Modified LAN disable ballout to cover A-0 (DEV_DIS_N) and B-0
(DEV_OFF_N).
•
Removed integrated Baseboard Management Controller.
•
•
•
•
•
•
•
•
•
•
Updated operating temperature
Changed DEV_DIS_N pin (A Stepping) to RSVD_NC
Corrected LED descriptions in signal descriptions in signal descriptions
Added Absolute Maximum Ratings
Added General Operating Conditions
Added Power Specifications
Oct 2003
0.75
Added voltage Ramp and Sequencing Recommendations
Added DC I/O Specifications
Added Timing Specifications
Edited Thermal Characteristics
•
Section 4.4, Figure 2; Section 4.5.1.1;Section 4.5.1.2, Figure 5; Section 4.5.2,
Figure 6; Section 5.1, Figure 7; Section 5.1, Figure 8; Section 5.4, Figure 9, ball T6
changed to PERST_N.
May 2004
0.85
0.90
•
•
•
Included 82572EI information
Updated signal names
January
2005
Updated power numbers
May 2005
Nov 2005
0.92
1.0
•
•
Corrected 1.1V Operating Range in Table 2
Changed document status to “Intel Confidential,” updated power values, made
minor corrections to text
•
•
Corrected pinlists
Pin A7 DEVICE_DIS_N has been moved to Reserved and No Connect Signals;
this pin is now Reserved. Refer to 82571EB/82571EI Design Guide for guidance
on proper connection.
March 2006
1.1
1.2
•
•
Pin R4 LAN_PWR_GOOD has been moved to Reserved and No Connect Signals;
this pin is now Reserved. Refer to 82571EB/82571EI Design Guide for guidance
on proper connection.
August
2006
Corrected signal mames, minor text corrections
Product Datasheet
iii
82571EB/82572 Gigabit Ethernet Controller
Contents
1.0
Introduction..................................................................................................................................... 1
1.1
1.2
1.3
Document Scope................................................................................................................. 1
Reference Documents......................................................................................................... 2
Block Diagram.................................................................................................................... 3
2.0
Features of the 82571EB/82572EI Gigabit Ethernet Controller ................................................ 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
PCI Express Features.......................................................................................................... 5
MAC-Specific Features ...................................................................................................... 5
PHY Specific Features........................................................................................................ 6
Host Offloading Features.................................................................................................... 6
Manageability Features....................................................................................................... 7
Additional Device Features ................................................................................................ 7
Technology Features........................................................................................................... 8
3.0
Signal Descriptions.......................................................................................................................... 9
3.1
3.2
3.3
3.4
Signal Type Definitions...................................................................................................... 9
PCI Express Interface ......................................................................................................... 9
Power Management Signals ............................................................................................. 10
SMB and Fast Management Link Bus Signals................................................................. 10
EEPROM and Serial FLASH Interface Signals ............................................................... 11
LED Signals...................................................................................................................... 11
Other Signals .................................................................................................................... 12
Crystal Signals.................................................................................................................. 12
PHY Analog Signals......................................................................................................... 12
Serializer / Deserializer Signals........................................................................................ 14
Test Interface Signals ....................................................................................................... 14
Power Supply Connections............................................................................................... 15
3.12.1 Digital and Analog Supplies .............................................................................. 15
3.12.2 Grounds, Reserved Pins and No Connects......................................................... 15
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
4.0
Voltage, Temperature, and Timing Specifications .................................................................... 17
4.1
4.2
Targeted Absolute Maximum Ratings.............................................................................. 17
Targeted Recommended Operating Conditions ............................................................... 18
4.2.1
4.2.2
4.2.3
General Operating Conditions............................................................................ 18
Voltage Ramps................................................................................................... 19
Voltage Power Sequencing Options................................................................... 20
4.3
DC Specifications............................................................................................................. 20
4.3.4
4.3.5
4.3.6
Power Specifications--82571EB ........................................................................ 21
Power Specifications--82572EI.......................................................................... 23
I/O Characteristics.............................................................................................. 25
4.4
4.5
Targeted AC Characteristics............................................................................................. 26
Targeted Timing Specifications........................................................................................ 28
4.5.1
4.5.2
4.5.3
PCI Express Interface......................................................................................... 28
EEPROM Interface ............................................................................................ 31
FLASH Interface................................................................................................ 33
iv
Product Datasheet
82571EB/82572 Gigabit Ethernet Controller
5.0
Package and Pinout Information..................................................................................................35
5.1
5.2
5.3
5.4
Package Information..........................................................................................................35
Thermal Specification .......................................................................................................37
Pinout Information.............................................................................................................37
Visual Pin Assignments.....................................................................................................50
Product Datasheet
v
82571EB/82572 Gigabit Ethernet Controller
Note: This page is intentionally left blank
vi
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
1.0
Introduction
The Intel 82571EB Gigabit Ethernet Controller is a single, compact component with two fully
integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. The
Intel 82572EI Gigabit Ethernet Controller is a single-port version of the controller in the same
package. These devices use the PCI Express* architecture (Rev. 1.0a). The Intel 82571EB/82572EI
enables dual- or single-port Gigabit Ethernet implementation in a very small area and can be used
for server and workstation network designs with critical space constraints.
The Intel 82571EB/82572EI provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Ports also contain a
Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit
backplane applications. In addition to managing MAC and PHY Ethernet layer functions, the
controller manages PCI Express packet traffic across its transaction, link, and physical/logical
layers.
The Intel 82571EB/82572EI’s on-board System Management Bus (SMB) ports enable network
manageability implementations required by information technology personnel for remote control
and alerting via the LAN. With SMB, management packets can be routed to or from a management
processor. The SMB ports enable industry standards, such as Alert Standard Format (ASF) 2.0, to
be implemented using the 82571EB/82572EI controller. In addition, on-chip ASF 2.0 circuitry
provides alerting and remote control capabilities with standardized interfaces. Enhanced pass-
through capabilities also allow system remote control over standardized interfaces.
The 82571EB/82572EI Gigabit Ethernet Controller with PCI Express architecture is designed for
high performance and low memory latency. The device is optimized to connect to a system
Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the 82571EB/82572EI
controller can connect to an I/O Control Hub (ICH6 & 7) that has a PCI Express interface.
Wide internal data paths eliminate performance bottlenecks by efficiently handling large address
and data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit
Ethernet and independent transmit and receive queues, the 82571EB/82572EI controller efficiently
handles packets with minimum latency. The 82571EB/82572EI controller includes advanced
interrupt handling features. The 82571EB/82572EI uses efficient ring buffer descriptor data
structures, with up to 64 packet descriptors cached on chip. A large 48 KByte per port on-chip
packet buffer maintains superior performance. In addition, using hardware acceleration, the
controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP
segmentation.
The 82571EB/82572EI is packaged in a 17 mm X 17 mm, 256-ball grid array.
1.1
Document Scope
This document contains targeted datasheet specifications for the 82571EB/82572EI Gigabit
Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and
pinout information.
Product Datasheet
1
82571EB/82572 Gigabit Ethernet Controller
1.2
Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout
techniques. The following documents provide additional information:
• 82571EB/82572EI Gigabit Ethernet Controller Design Guide, AP-447. Intel Corporation.
• Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation.
• PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group.
• PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group.
• PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest
Group.
• IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers (IEEE).
This version incorporates various IEEE standards previously published separately.
2
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
1.3
Block Diagram
Figure 1. 82571EB/82572EI Gigabit Ethernet Controller Block Diagram (Single Port Shown)
Product Datasheet
3
82571EB/82572 Gigabit Ethernet Controller
Note: This page is intentionally left blank.
4
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
2.0
Features of the 82571EB/82572EI Gigabit Ethernet
Controller
2.1
PCI Express Features
Features
Benefits
Bus sharing not required
•
•
•
Uses x4 PCI Express interface on MCH device
Low latency path to memory
Relieves congestion for IO devices
Peak bandwidth 2 GB/s in each direction per PCI Express
lane
•
•
Supports Gigabit Ethernet at full wire speed
Compatible extensions to PCI power management and
ACPI
PCI Express Power Management
High bandwidth density per pin
•
•
PE_WAKE_n available for wakeup event
Less congested board routing
2.2
MAC-Specific Features
Features
Benefits
•
•
Network packets handled without waiting or buffer
overflow.
Optimized transmit and receive queues
Control over the transmissions of pause frames through
software or hardware triggering
IEEE 802.3x compliant flow control support with software
controllable pause times and threshold values
•
•
•
Frame loss reduced from receive overruns
Efficient use of PCI Express bandwidth
Efficient packet prioritization
Caches up to 64 packet descriptors (per queue)
Separate transmit queue per port
Programmable host memory receive buffers (256 Bytes to
16 KBytes) and cache line size (64 Bytes to 128 Bytes)
•
Efficient use of PCI Express bandwidth
•
•
Low latency data handling
Wide, pipelined internal data path architecture
Superior DMA transfer rate performance
•
•
No external FIFO memory requirements
FIFO size adjustable to application
Dual 48 KByte configurable Transmit and Receive FIFO
buffers
Descriptor ring management hardware for transmit and
receive
•
•
Simple software programming model
Efficient system memory and use of PCI Express
bandwidth
Optimized descriptor fetching and write-back mechanisms
Mechanism available for reducing interrupts generated by
transmit and receive operations
•
•
Maximizes system performance and throughput
Enables jumbo frames
Supports transmission and reception of packets up to 9 kB
Product Datasheet
5
82571EB/82572 Gigabit Ethernet Controller
2.3
PHY Specific Features
Features
Benefits
•
•
•
Smaller footprint and lower power dissipation
compared to multi-chip MAC and PHY solutions
Integrated PHY for 10/100/1000 Mbps operation
Automatic link configuration including speed, duplex,
and flow control
IEEE 802.3ab Auto-Negotiation support
Robust operation over the installed base of Category-5
(CAT-5) twisted pair cabling
IEEE 802.3ab PHY compliance and compatibility
State-of-the-art DSP architecture implements digital
adaptive equalization, echo cancellation, and cross-talk
cancellation
•
•
Robust performance in noisy environments
Tolerance of common electrical signal impairments
•
•
Improved end-user troubleshooting
Tolerance of common wiring faults
PHY cable correction and diagnostics
•
•
•
Low-Power Link-Up (LPLU)
Smart Speed
•
•
Enables link in low-power mode
Reacts to various link speeds
Smart Power-Down
2.4
Host Offloading Features
Features
Benefits
Transmit and receive IP, TCP and UDP checksum off-
loading capabilities
•
Lower CPU utilization
•
•
Increased throughput and lower CPU utilization
Transmit TCP segmentation
IPv6 Offloading
Large send offload feature (in Microsoft* Windows*
XP) compatible
•
Checksum and segmentation capability extended to
new standard packet type
•
•
•
16 exact matched packets (unicast or multicast)
4096-bit hash filter for multicast frames
Advanced packet filtering
Promiscuous (unicast and multicast) transfer mode
support
•
•
•
Optional filtering of invalid frames
IEEE 802.1q VLAN support with VLAN tag insertion,
stripping and packet filtering for up to 4096 VLAN tags
Ability to create multiple virtual LAN segments
Descriptor ring management hardware for transmit and
receive
Optimized fetching and write-back mechanisms for
efficient system memory and PCI bandwidth usage
•
High throughput for large data transfers on networks
supporting jumbo frames
9 kB jumbo frame support
6
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
2.5
Manageability Features
Features
Benefits
Manageability features:
•
•
•
Alerting and control via standardized interfaces
Network management flexibility
•
Two SMBus ports one with Fast Management Link
Capability
•
•
Alerting Standards Format 1.0 and 2.0
Manageability data transfers up to 8 Mb/s peak rate
Advanced Power Management (Wake on LAN)
•
•
•
Enables effective ASF 2.0 implementations
Promotes customized designs
Allows packets routing to and from either LAN port
and a server management processor
On-board microcontroller
•
•
Supports serial text and keyboard redirection
Supports remote floppy/CD
Preboot eXecution Environment (PXE) Flash interface
support (32-bit nd 64-bit)
•
Local Flash interface for PXE image
Compliance with PCI Power Management 1.1 and ACPI
2.0 register set compliant including:
•
PCI power management capability requirements for PC
and embedded applications
•
•
D0 and D3 power states
Network Device Class Power Management
Specification 1.1
•
•
•
Easy system monitoring with industry standard
consoles
SNMP and RMON statistic counters
SDG 3.0, WfM 3.0, and PC2001 compliance
Wake on LAN support
Remote network management capabilities through
DMI 2.0 and SNMP software
Packet recognition and wake-up for NIC and LOM
applications without software configuration
2.6
Additional Device Features
Features
Benefits
•
•
•
•
•
•
Inherent dual port teaming ability
High availability using one port for failover
Higher throughput than single Gigabit Ethernet port
Lower latency due to one electrical load on the bus
Saves critical board space
82571EB: Two complete Gigabit Ethernet connections in a
single device
Reduced multi-port Gigabit Ethernet costs
•
•
•
•
Supports backplane and fiber applications as well as
copper-based Gigabit
Integrated SERDES
Four activity and link indication outputs (per port) that
directly drive LEDs
Link and activity indications (10, 100, and 1000 Mbps)
on each port
Software definable function (speed, link, and activity)
and blinking allowing flexible LED implementations
Programmable LED functionality
Internal PLL for clock generation can use a 25 MHz crystal
Lower component count and system cost
Product Datasheet
7
82571EB/82572 Gigabit Ethernet Controller
Features
Benefits
JTAG (IEEE 1149.1) Test Access Port built in silicon
•
•
Simplified testing using boundary scan
Additional flexibility for LEDs or other low speed
I/O devices
Four software definable pins per port
Provides loopback capabilities
•
Validates silicon integrity
2.7
Technology Features
Features
Benefits
•
•
17 mm X 17 mm component occupies
only 28% more board space than a single
port device
256-pin Flip-Chip Ball Grid Array (FC-BGA) package
Implemented in 90 nm CMOS process
Offers lowest geometry to minimize
power and size while maintaining Intel
quality and reliability standards
Operating temperature:
1000BASE-T, 0° C to 55° C (with thermal management)
1000BASE-T, 0° C to 70° C (with increased thermal management)
1000BASE-SX/LX (or SERDES backplane), 0°C to 70° C
Storage temperature 65° C to 140° C
•
•
Simple thermal design
Typical targeted power dissipation:
~3.50 W @ D0 1000 Mbps
Minimizes impact of incorporating
Gigabit instead of Fast Ethernet.
~0.78mW @ D3 100 Mbps (wakeup enabled)
~0.36mW @ D3 wakeup disabled
8
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
3.0
Signal Descriptions
Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82571EB/82572EI controller are electrically defined as follows:
Name
Definition
I
Input. Standard input only digital signal.
Output. Standard output only digital signal.
O
TS
Tri-state. Bi-directional three-state digital input/output signal.
Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-
up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the
de-asserted state.
OD
A
A(I)
A(O)
P
Analog. PCI Express*, SERDES, or, PHY analog signal.
Analog-Input. Standard input only analog signal.
Analog-Output. Standard output only analog signal.
Power. Power connection, voltage reference, or other reference connection.
3.2
PCI Express Interface
Symbol
Type
Name and Function
High Speed Serial Receive Data. These signals connect to corresponding PETn and
PETp signals on a system motherboard or a PCI Express connector. Series AC coupling
capacitors are required at the transmitter end. The PCI Express differential inputs are
clocked at 2.5 Gb/s.
PERn[3:0]
PERp[3:0]
A(I)
High Speed Serial Transmit Data. These signals connect to corresponding PERn and
PERp signals on a system motherboard or a PCI Express connector. Series AC coupling
capacitors are required at the 82571EB/82572EI controller end. The PCI Express
differential outputs are clocked at 2.5 Gb/s.
PETn[3:0]
PETp[3:0]
A(O)
High Speed Serial Impedance Compensation. Connect the recommended resistor value
across these balls. Refer to the 82571EB/82572EI Design Guide for the recommended
value.
PE_RCOMPp
PE_RCOMPn
P
I
PE_CLKp
PE_CLKn
100 MHz Differential Clock for the PCI Express Interface. The reference clock is
furnished by the system and has a 300 ppm frequency tolerance.
PCI Express Reset. When the signal is low, all PCI Express functions are held in reset.
When the signal is high, it denotes that main power is available to the 82571EB/82572EI
controller and the reference clock is running.
PE_RSTn
I
In systems with a PCI Express add-in card, this signal routes to the connector.
Product Datasheet
9
82571EB/82572EI Gigabit Ethernet Controller
3.3
Power Management Signals
Symbol
Type
Name and Function
Auxiliary Power Present. If the Auxiliary Power signal is high, then auxiliary power
is present and the 82571EB/82572EI device should support the D3cold power state.
AUX_PWR
I
LAN0_DIS_N
LAN1_DIS_N/
RSVD_B8
LAN Disables 0 and 1. Disables individual Ethernet ports. State is latched upon a
rising edge of PERST_N or a PCI Express reset event. This pin has an internal pull-up
resistor.
I
I
Device Off. Asynchronously disables Ethernet controller, including voltage regulator
control outputs if selected in CTRL_EXT. This pin has an internal pull-up resistor.
DEV_OFF_N
Wake. The 82571EB/82572EI device drives this signal low when it receives a wake-up
event and either the PME Enable bit in the Power Management Control/Status Register
or the Advanced Power Management Enable (APME) bit of the Wake-up Control
Register (WUC) is 1b.
PE_WAKEn
OD
3.4
SMB and Fast Management Link Bus Signals
Symbol
Type
Name and Function
SMB Clock. The SMB Clock signals are open drain signals for the serial SMB
interface (Ports A and B). Alternatively, when SMB Port A is configured for a Fast
Management Link Bus, SMB Clock A becomes the Fast Management Link Bus
Master Clock. The Fast Management Link Bus can be clocked up to 6.5 MHz.
SMBCLK0/FLBMCK
SMBCLK1
I/O
SMB Data. The SMB Data signals are open drain signals for the serial SMB interface
(Ports A and B). Alternatively, when SMB Port A is configured for a Fast
Management Link Bus, SMB Data A becomes Fast Management Link Bus Master
Data.
SMBD0/FLBMD
SMBD1
I/O
SMB Alert. The SMB Alert signal is an open drain signal for serial SMB Port A. In
ASF mode, this signal acts as a power good input. It acts as an alert input in 82559
compatible mode.
SMBALRT_N/
PCI_PWR_GOOD
I/O
O
Fast Management Link Bus Slave Data. When SMB Port A is configured for a Fast
Management Link Bus, this signal becomes the serial data path for slave data from
the 82571EB/82572EI controller.
FLBSD
Fast Management Link Bus Interrupt Extension. Driven by the 82571EB/
82572EI controller as a slave to alert the master to read data. Alternatively, it signals
the master to extend the low phase of the clock.
FLBINTEX
O
10
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
3.5
EEPROM and Serial FLASH Interface Signals
Symbol
Type
Name and Function
EEPROM Data Input. The EEPROM Data Input pin is used for output to the SPI EEPROM
memory device.
EE_DI
O
EEPROM Data Output. The EEPROM Data Output pin is used for input from the SPI
EEPROM memory device. The EE_DO includes an internal pull-up resistor.
EE_DO
EE_CS_N
EE_SK
I
O
O
EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device.
EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the SPI
EEPROM interface, which is approximately 2 MHz.
FLSH_CE_N
FLSH_SCK
FLSH_SI
O
O
O
I
FLASH Chip Enable Output. Used to enable FLASH device.
FLASH Serial Clock Output.
FLASH Serial Data Input. This pin is an output to the memory device.
FLASH Serial Data Output. This pin is an input from the memory device.
FLSH_SO
3.6
LED Signals
Symbol
Type
Name and Function
LED0_0. Programmable LED output for Port A. As the Link LED, it indicates link
connectivity on Port A.
LED0_0
O
O
O
O
O
O
O
O
LED0_1. Programmable LED output for Port A. As the Activity LED, it flashes to indicate
receive activity on Port A for packets destined for this node.
LED0_1
LED0_2
LED0_3
LED0_2. Programmable LED output for Port A. As the Link 100 LED, it indicates link at
100 Mbps for Port A.
LED0_3. Programmable LED output for Port A. As the Link 1000 LED, it indicates link at
1000 Mbps for Port A.
LED1_0/
RSVD_P8
LEDB0_N. Programmable LED output for Port B. As the Link LED, it indicates link
connectivity on Port B. (82571 EB only.)
LED1_1/
RSVD_R8
LED1_1. Programmable LED output for Port B. As the Activity LED, it flashes to indicate
receive activity on Port B for packets destined for this node. (82571 EB only.)
LED1_2/
RSVD_T8
LED1_2. Programmable LED output for Port B. As the Link 100 LED, it indicates link at
100 Mbps for Port B. (82571 EB only.)
LED1_3/
RSVD_P9
LED1_3. Programmable LED output for Port B. As the Link 1000 LED, it indicates link at
1000 Mbps for Port B. (82571 EB only.)
Product Datasheet
11
82571EB/82572EI Gigabit Ethernet Controller
3.7
Other Signals
Symbol
Type
Name and Function
SDP0_1
SDP0_2
SDP0_3
SDP0_4
SDP1_1/RSVD_P6
SDP1_2/RSVD_B6
SDP1_3/RSVD_C6
SDP1_4/RSVD_R6
Software Defined Pin. The Software Defined Pins are programmable with respect to
input and output capability. SDP0_3 and SDP1_3 may optionally be configured as
interrupt inputs. SDP signals default to inputs upon power-up, but may be configured
differently by the EEPROM.
TS
3.8
Crystal Signals
Symbol
Type
Name and Function
Crystal One. The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel
resonant crystal with a frequency tolerance of 30 ppm or better. The other end of the crystal
should be connected to XTAL2. Optionally, an oscillator can be connected to XTAL 1. See the
design guide for more information..
XTAL1
I
Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal
into oscillation.
XTAL2
O
3.9
PHY Analog Signals
Port 0
Symbol
Type
Name and Function
Bias Resistors. These are the reference connections for the Media Dependent Interface.
The recommended resistor value should be connected across the positive/negative pair,
even if the MDI interface is not used. Refer to the 82571EB/82572EI Design Guide for
the recommended value.
RBIAS0p
RBIAS0n
P
Media Dependent Interface [0].
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X
configuration, they correspond to BI_DB+/-.
MDI_PLUS0_0
A
100BASE-TX: In MDI configuration, these are used for the transmit pair, and in MDI-X
configuration, they are used for the receive pair.
MDI_MINUS0_0
10BASE-T: In MDI configuration, they are used for the transmit pair, and in MDI-X
configuration, used for the receive pair.
12
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Symbol
Type
Name and Function
Media Dependent Interface [1].
1000BASE-T: In MDI configuration, these correspond to BI_DB+/-, and in MDI-X
configuration, they correspond to BI_DA+/-.
MDI_PLUS0_1
A
100BASE-TX: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
MDI_MINUS0_1
10BASE-T: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
Media Dependent Interface [2].
1000BASE-T: In MDI configuration, these correspond to BI_DC+/-, and in MDI-X
configuration, they correspond to BI_DD+/-.
MDI_PLUS0_2
A
A
MDI_MINUS0_2
100BASE-TX: Unused.
10BASE-T: Unused.
Media Dependent Interface [3].
1000BASE-T: In MDI configuration, these correspond to BI_DD+/-, and in MDI-X
configuration, they correspond to BI_DC+/-.
MDI_PLUS0_3
MDI_MINUS0_3
100BASE-TX: Unused.
10BASE-T: Unused.
Port 1 (82571EB Only)
Symbol
Type
Name and Function
RBIAS1p/
RSVD_M14
Bias Resistors. These are the reference connections for the Media Dependent Interface.
The recommended resistor value should be connected across the positive/negative pair,
even if the MDI interface is not used. Refer to the 82571EB/82572EI Design Guide for
the recommended value.
P
RBIAS1n/
RSVD_N14
Media Dependent Interface [0].
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X
configuration, they correspond to BI_DB+/-.
MDI_PLUS1_0/
RSVD_T14
A
A
100BASE-TX: In MDI configuration, they are used for the transmit pair, and in MDI-X
configuration, they are used for the receive pair.
MDI_MINUS1_0/
RSVD_R14
10BASE-T: In MDI configuration, they are used for the transmit pair, and in MDI-X
configuration, they are used for the receive pair.
Media Dependent Interface [1].
1000BASE-T: In MDI configuration, these correspond to BI_DB+/-, and in MDI-X
configuration, they correspond to BI_DA+/-.
MDI_PLUS1_1/
RSVD_T15
100BASE-TX: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
MDI_MINUS1_1/
RSVD_R15
10BASE-T: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
Media Dependent Interface [2].
MDI_PLUS1_2/
RSVD_P16
1000BASE-T: In MDI configuration, these correspond to BI_DC+/-, and in MDI-X
configuration, they correspond to BI_DD+/-.
A
A
MDI_MINUS1_2/
RSVD_P15
100BASE-TX: Unused.
10BASE-T: Unused.
Media Dependent Interface [3].
MDI_PLUS1_3/
RSVD_N16
1000BASE-T: In MDI configuration, these correspond to BI_DD+/-, and in MDI-X
configuration, they correspond to BI_DC+/-.
MDI_MINUS1_3/
RSVD_N15
100BASE-TX: Unused.
10BASE-T: Unused.
Product Datasheet
13
82571EB/82572EI Gigabit Ethernet Controller
3.10
Serializer / Deserializer Signals
Symbol
Type
Name and Function
SERDES Receive Pairs. Signals SRDSI_0_PLUS and SRDSI_0_MINUS make the
differential receive pair for the 1.25 GHz serial interface for Port 0. For serializer/
deserializer operation, the inputs should be coupled to ECL voltage levels.
SRDSI_0_PLUS
SRDSI_0_MINUS
SRDSI_1_PLUS/
RSVD_M16
A(I)
Signals SRDSI_1_PLUS and SRDSI_1_MINUS make the differential receive pair for
the 1.25 GHz serial interface for Port 1. For serializer/deserializer operation, the inputs
should be coupled to ECL voltage levels.
SRDSI_1_MINUS/
RSVD_L16
If the SERDES interface is not used, these pins should not be connected.
SERDES Transmit Pairs. Signals SRDSO_0_PLUS and SRDSO_0_MINUS make the
differential transmit pair for the 1.25 GHz serial interface for Port 0. For serializer/
deserializer operation, the outputs drive the LVPECL voltage levels.
SRDSO_0_PLUS
SRDSO_0_MINUS
SRDSO_1_PLUS/
RSVD_K15
A(O) Signals SRDSO_1_PLUS and SRDSO_1_MINUS make the differential transmit pair for
the 1.25 GHz serial interface for Port 1. For serializer/deserializer operation, the outputs
drive the LVPECL voltage levels.
SRDSO_1_MINUS
/RSVD_L15
If the SERDES interface is not used, these pins should not be connected.
Signal Detects. These pins (SRDSA_SIG_DET for Port 0; SRDSB_SIG_DET for Port
1) indicate whether the SERDES signals (connected to the 1.25 GHz serial interface)
have been detected by the optical transceivers. If the SERDES interface is not used, the
SIG_DET inputs can be left unconnected.
SRDSA_SIG_DET
I
SRDSB_SIG_DET/
RSVD_C4
SERDES Impedance Compensation. Connect the recommended resistor value across
these balls, even if not using the SERDES interface. Refer to the 82571EB/82572EI
Design Guide for the recommended value.
SRDS_RCOMPp
SRDS_RCOMPn
A
3.11
Test Interface Signals
Symbol
Type
Name and Function
JTAG Test Access Port Clock.
JTCK
JTDI
I
I
JTAG Test Access Port Test Data In.
JTAG Test Access Port Test Data Out.
JTAG Test Access Port Mode Select.
JTDO
JTMS
O
I
14
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Symbol
Type
Name and Function
IEEE_TEST0p
IEEE_TEST0n
IEEE Analog Test Pins. Differential outputs providing reference clocks for IEEE
PHY conformance verification. For prototype testing, connect each pair to two-pin
headers. For production systems, leave pins unconnected.
IEEE_TEST1p/
RSVD_R13
O
IEEE_TEST1n/
RSVD_T13
THERM_Dp
THERM_Dn
O
I
Thermal Diode Reference. Can be used to measure the Si temperature.
Factory Test Pin. Attach a 1 KΩ pull-down resistor to ground for normal
operation.
TEST_EN
3.12
Power Supply Connections
3.12.1
Digital and Analog Supplies
Symbol
Type
Name and Function
3.3V Digital Power Supply. For I/O circuits.
VCC33
P
1.8V Analog Power Supply. For PHY analog, PHY I/O, PCI Express analog, and Phase Lock
Loop circuits, Connect all 1.8V pins to a single power supply.
VCC18
VCC11
P
P
1.1V Digital Power Supply. For core digital, PHY digital, PCI Express digital and clock
circuits, connect all 1.1V pins to a single power supply.
3.12.2
Grounds, Reserved Pins and No Connects
Symbol
Type
Name and Function
VSSA
VSS
P
P
Analog Ground. Connects to PHY analog circuits. Connect directly to analog ground.
Digital Ground. Connects to core and digital I/O. Connect to GND.
Reserved Pin. These pins are reserved by Intel and may have factory test functions. For normal
operation, do not connect any circuitry to these pins (allow them to “float”). Some special
configurations may require pull-up or pull-down resistors on these pins. Please refer to the
82571EB/82572EI design guide for more information.
RSVD_ pin#
NC_pin#
P
P
No Connect. This pin is not connected internally.
Product Datasheet
15
82571EB/82572EI Gigabit Ethernet Controller
16
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.0
Voltage, Temperature, and Timing Specifications
4.1
Targeted Absolute Maximum Ratings
Table 1. Absolute Maximum Ratingsa
Symbol
VCC(3.3)
Parameter
Min
Max
Unit
DC supply voltage on 3.3V pins with
respect to VSS
VSS - 0.5
4.6
V
DC supply voltage on 1.8V pins with
respect to VSSb
VCC(1.8)
VCC(1.1)
VSS - 0.3
VSS - 0.2
2.5
1.7
V
V
DC supply voltage on 1.1V pins with
respect to VSSb
3.3V I/O Voltage
1.8V I/O Voltage
1.1V I/O Voltage
VSS - 0.5
VSS - 0.3
VSS - 0.2
4.6
2.5
1.7
VI / VO
V
IO
DC output current
N/A
-65
30
mA
°C
Tstorage
Storage temperature range
140
ESD per MIL_STD-883 Test Method
3015, Specification 2001V Latchup
Over/Undershoot: 150 mA, 125° C
VDD overstress:
VDD(3.3) * (7.2 V)
N/A
V
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded for
an indefinite duration. These values should not be used as the limits for normal device operations.
b. During normal device power up and power down, the 1.8V and 1.1V supplies must not ramp before the 3.3V supply.
Product Datasheet
17
82571EB/82572EI Gigabit Ethernet Controller
4.2
Targeted Recommended Operating Conditions
4.2.1
General Operating Conditions
Table 2. Recommended Operating Conditions a
Symbol
VCC(3.3)
Parameter
Min
Max
Unit
DC supply voltage on 3.3V pins
DC supply voltage on 1.8V pinsb, c
DC supply voltage on 1.1V pins
Input rise/fall time (normal input)
Operating temperature range (ambient)
Junction temperature
3.0
1.71
1.045
0
3.6
1.89
1.155
200
V
V
VCC(1.8)
VCC(1.1)
tR / tF
Ta
V
ns
°C
°C
0
55d
TJ
N/A
≤110
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might
result in permanent damage. Device functionality to stated DC and AC limits is not guaranteed, if conditions exceed recommended oper-
ating conditions.
b. See Section 4.2.2 for voltage ramp and sequencing recommendations.
c. Operation with internal voltage regulator control of PNP pass transistor may exceed this range due to 82571EB process skew tracking.
d. 1000BASE-T designs require thermal management (heatsink and/or forced air flow) to achieve 0° to 55° C operation. Increased thermal
management can increase this temperature range to 0° to 70° C. Applications using the SERDES interface are rated for 0° to 70° C without
thermal management.
18
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.2.2
Voltage Ramps
Table 3. 3.3V Supply Voltage Ramp
Parameter
Description
Min
Max
Unit
Rise Time
Time from 10% to 90% mark
Voltage dip allowed in ramp
0.1
100a
0
ms
Monotonicity
N/A
mV
Ramp rate at any time between 10% to
90%
Slope
24
3
28000
3.6
mV/ms
V
Operational
Range
Voltage range for normal operating
conditions
Maximum voltage ripple at a bandwidth
equal to 50 MHz
Ripple
N/A
70
mVpeak-peak
Overshoot
Settling Time
Overshoot time upon rampb
Maximum voltage allowedb
N/A
N/A
0.05
100
ms
Overshoot
mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
b. Excessive overshoot can affect long term reliability.
Table 4. 1.8V Supply Voltage Ramp
Parameter
Description
Min
Max
Unit
Rise Time
Time from 10% to 90% mark
Voltage dip allowed in ramp
0.1
100a
0
ms
Monotonicity
N/A
mV
Ramp rate at any time between 10% to
90%
Slope
14
60000
1.89
40
mV/ms
V
Operational
Range
Voltage range for normal operating
conditions
1.71
N/A
Maximum voltage ripple at a bandwidth
equal to 1 MHz
Ripple
mVpeak-peak
Overshoot
SettlingTime
Overshoot time upon rampb
Maximum voltage allowedb
N/A
N/A
0.1
ms
Overshoot
100
mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
b. Excessive overshoot can affect long term reliability.
Table 5. 1.1V Supply Voltage Ramp
Parameter
Description
Min
Max
Unit
Rise Time
Time from 10% to 90% mark
Voltage dip allowed in ramp
0.1
100a
0
ms
Monotonicity
N/A
mV
Ramp rate at any time between 10% to
90%
Slope
7.6
33600
1.155
mV/ms
V
Operational
Range
Voltage range for normal operating
conditions
1.045
Product Datasheet
19
82571EB/82572EI Gigabit Ethernet Controller
Table 5. 1.1V Supply Voltage Ramp
Maximum voltage ripple at a bandwidth
equal to 1 MHz
Ripple
N/A
40
mVpeak-peak
Overshoot
SettlingTime
Overshoot time upon rampb
Maximum voltage allowedb
N/A
N/A
0.05
100
ms
Overshoot
mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
b. Excessive overshoot can affect long term reliability.
4.2.3
Voltage Power Sequencing Options
To meet 375 mA inrush current requirements (not including external capacitors) the ramp time
should be 5 ms -100 ms on all power rails. For faster ramps (100 us - 5 ms), expect higher inrush
current due to the high charging current of the decoupling capacitors of 3.3V, 1.8V and 1.1V rails.
4.3
DC Specifications
Table 6. DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
DC supply voltage on 3.3V
pins
VCC(3.3)
3.00
3.30
3.60
V
DC supply voltage on 1.8V
pins
VCC(1.8)
VCC(1.1)
1.71
1.80
1.89
V
V
DC supply voltage on 1.1V
pins
1.045
1.100
1.155
20
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.3.4
Power Specifications--82571EB
Table 7. D0a--Active Link
D0a--Active Link
@10
Mbps
@100
Mbps
@ 1000 Mbps
(copper)
@ 1000 Mbps
(SERDES)
Typ Icc Typ Icc Typ Icc MaxIcc Typ Icc MaxIcc
(mA)a
(mA)a
(mA)a
(mA)a
(mA)a
(mA)b
3.3V
1.8V
1.1V
26
26
26
34
42
46
350
399
893
913
254
282
370
456
1022
1520
529
1002
Total
Device
Power
1.12W
1.31W
2.82W
3.43W
1.18W
1.76W
a. Typical conditions: operating temperature (T ) = 25 C, nominal voltages and contin-
A
uous network traffic at link speed at full duplex.
b. Maximum conditions: maximum operating temperature (T ) values, typical voltage
J
values and continuous network traffic at link speed at full duplex.
Product Datasheet
21
82571EB/82572EI Gigabit Ethernet Controller
Table 8. D0a--Idle Link L0s Only
D0a--Idle Link
L0s Only
Unplugged--no
@1000Mbps
(copper)
@10Mbps
@100Mbps
link
Typ Icc (mA)a
3.3V
1.8V
1.1V
26
26
26
26
130
332
123
334
306
414
837
839
Total
Device
Power
0.69W
0.67W
1.10W
2.52W
a. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full du-
plex
Table 9. D3cold
D3cold - wake-up
enabled
D3cold-
wake
disabled
(no link)
@100
Mbps
@10 Mbps
Typ Icc
Typ Icc
(mA)a, b
Typ Icc
(mA)a b
(mA)a, b
3.3V
1.8V
1.1V
26
74
26
26
76
243
236
133
123
Total
Device
Power
0.37W
0.78W
0.36W
a. D3 Cold activated on a Windows Server 2003 OS--using
Hbernate mode
b. L0s enable, L1 disabled
22
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 10. D(r) Unintialized
D(r) Uninitialized
Disabled through LAN_DIS_N Disabled through DEV_OFF_N
Typ Icc (mA)
Typ Icc (mA)
3.3V
1.8V
1.1V
26
63
26
68
83
130
Total Device
Power
0.34W
0.30W
4.3.5
Power Specifications--82572EI
Table 11. D0a--Active Link
D0a--Active Link
@10
Mbps
@100
Mbps
@ 1000 Mbps
(copper)
Typ Icc Typ Icc Typ Icc MaxIcc
(mA)a
(mA)a
(mA)a
(mA)a
3.3V
1.8V
1.1V
26
26
26
34
210
211
484
502
291
232
494
1023
Total
Device
Power
0.78W
0.72W
1.50W
2.14W
a. Typical conditions: operating temperature (T ) = 25 C,
A
nominal voltages and continuous network traffic at link
speed at full duplex.
Product Datasheet
23
82571EB/82572EI Gigabit Ethernet Controller
Table 12. D0a--Idle Link
D0a--Idle Link
L0s Only
Unplugged--no
link
@1000Mbps
(copper)
@10Mbps
@100Mbps
Typ Icc (mA)a
3.3V
1.8V
1.1V
26
26
26
26
111
176
102
179
199
218
425
839
Total
Device
Powerb
0.48W
0.47W
0.68W
1.77W
a. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full du-
plex
b. LOs enabled; L1 disabled
Table 13. D3cold
D3cold - wake-up
enabled
D3cold-wake disabled;
unplugged, no link
@100
@10 Mbps
Mbps
Typ Icc
Typ Icc
(mA)a, b
Typ Icc (mA)a b
(mA)a, b
3.3V
1.8V
1.1V
26
77
26
26
84
173
163
120
110
Total
Device
Power
0.36W
0.58W
0.36W
a. D3 Cold activated on a Windows Server 2003 OS--using Hbernate mode
b. LOs enabled, L1 disabled
Table 14. D(r) Unintialized
D(r) Uninitialized
Disabled through LAN_DIS_N Disabled through DEV_OFF_N
Typ Icc (mA)
Typ Icc (mA)
3.3V
26
26
24
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 14. D(r) Unintialized
D(r) Uninitialized
Disabled through LAN_DIS_N Disabled through DEV_OFF_N
Typ Icc (mA)
Typ Icc (mA)
1.8V
1.1V
60
68
83
114
Total Device
Power
0.32W
0.30W
4.3.6
I/O Characteristics
Table 15. I/O Characteristicsa
Symbol
VIH
Parameter
Input high voltage
Condition
Min
Typ
Max
Units
VCC(3.3)
+ 0.5
2.0
-0.5
-15
N/A
N/A
N/A
V
V
VIL
IIN
Input low voltage
Input current
0.8
15
VIN = VDD(3.3) or
VSS
µA
IOH = -16 mA
VCC = Min
2.4
N/A
N/A
N/A
N/A
N/A
0.4
VOH
Output high voltage
Output low voltage
V
I
OH = -100 µA
V
CC - 0.02
VCC = Min
IOL = 16 mA
VCC = Min
N/A
VOL
V
I
OL = 100 µA
N/A
-10
N/A
N/A
0.2
10
VCC = Min
Off-state output leakage
current
IOZ
V
O = VCC or VSS
µA
b
CIN
Input capacitance
Internal pull-up
N/A
2.6
2.5
N/A
5.5
pF
PU
N/A
kΩ
a. The input buffer also has hysteresis > 160 mV.
b. = 2.5 pF(maximum input capacitance), C = 16 pF (characterized max output load capacitance per 160 MHz).
C
in
out
Product Datasheet
25
82571EB/82572EI Gigabit Ethernet Controller
4.4
Targeted AC Characteristics
Table 16. 25 MHz Clock Input Requirements
Symbol
Parameter
Min
Typ
Max
Unit
f0
Frequency
N/A
-50
25.000
N/A
N/A
N/A
N/A
N/A
20
N/A
+50
60
MHz
ppm
%
df0
Dc
tr
Frequency Variation
Duty Cycle
40
Rise Time
N/A
N/A
N/A
N/A
N/A
1.0
5
ns
tf
Fall Time
5
ns
Jptp
Cin
T
Clock Jitter (peak-to-peak)a
Input Capacitance
Operating Temperature
Input clock amplitude (peak-to-peak)
Clock common mode
250
N/A
70
ps
pF
°C
V
N/A
1.2
Aptp
Vcm
1.3
N/A
N/A
0.6
V
a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000Base-T Standard (at least 105 clock edges, filtered
by HPF with cut off frequency of 5000 Hz).
26
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 17. Reference Crystal Specification Requirements
Specification
Value
Vibrational Mode
Fundamental
25.000 MHz at 25 °C
±30 ppm recommended
Nominal Frequency
•
•
±50 ppm across the entire
operating temperature range
(required by IEEE specifications)
Frequency Tolerance
Temperature Stability
Calibration Mode
Load Capacitance
Shunt Capacitance
Series Resistance, Rs
Drive Level
+/- 30 ppm at 0 °C to 70 °C
Parallel
20 pF to 24 pF
6 pF maximum
50 Ω maximum
0.5 mW maximum
+/- 5.0 ppm per year maximum
500 ΜΩ minimum at DC 100 V
4 pF
Aging
Insulation Resistance
Board Capacitance
External Capacitors
Board Resistance
27 pF
0.1 Ω
Table 18. Link Interface Clock Requirements
Symbol
fGTXa
Parameter
GTX_CLK frequency
Min
Typ
Max
Unit
N/A
125
N/A
MHz
a. GTX_CLK is used externally for test purposes only.
Table 19. EEPROM Interface Clock Requirements
Symbol
Parameter
SPI EEPROM Clock
Min
Typ
Max
Unit
fSK
N/A
2
2.1
MHz
Table 20. AC Test Loads for General Output Pins
Symbol
Parameter
Min
Typ
Max
Unit
CL
Capacitance of test load
N/A
16
N/A
pF
Product Datasheet
27
82571EB/82572EI Gigabit Ethernet Controller
CL
Figure 2. AC Test Loads for General Output Pins
4.5
Targeted Timing Specifications
Note: Timing specifications are preliminary and subject to change. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
4.5.1
PCI Express Interface
4.5.1.1
Differential Transmitter (TX) Output Specifications
Table 21. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Typ
Max
Units
UI
Unit Interval
399.88
400
400.12
ps
Differential Peak
to Peak Output
Voltage
VTX-DIFFp-p
0.800
-3.0
N/A
-3.5
1.2
V
De-Emphasized
Differential
Output Voltage
(Ratio)
VTX-DE-RATIO
-4.0
dB
Minimum TX
Eye Width
TTX-EYE
0.70
N/A
N/A
N/A
N/A
UI
UI
TTX-RISE,
TTX-FALL
D+/D- TX Output
Rise/Fall Time
0.125
RMS AC Peak
Common Mode
Output Voltage
VTX-CM-ACp
N/A
0
N/A
N/A
N/A
20
25
20
mV
mV
mV
Absolute Delta of
DC Common
Mode Voltage
between D+ and
D-
VTX-CM-DC-LINE-
DELTA
Electrical Idle
Differential Peak
Output Voltage
VTX-IDLE-DIFFp
0
28
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 21. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Typ
Max
Units
The amount of
voltage change
VTX-RCV-DETECT allowed during
N/A
N/A
600
mV
Receiver
Detectoin
Differential
RLTX-DIFF
12
6
N/A
N/A
N/A
N/A
dB
dB
Return Loss
Common Mode
RLTX-CM
Return Loss
DC Differential
ZTX-DIFF-DC
80
100
120
TX Impedance
Ω
Lane-toLane
LTX-SKEW
N/A
N/A
500 + 2 UI
ps
Output Skew
V
TX-DIFF = 0 mV
VTX-DIFF = 0 mV
(D+ D- Crossing Point)
[Transition Bit]
TX-DIFFp-p-MIN = 800 mV
(D+ D- Crossing Point)
V
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
0.7 UI = UI - 0.3 UI(JTX-TOTAL-MAX
)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
Figure 3. PCI Express Transmitter Eye Diagram
Product Datasheet
29
82571EB/82572EI Gigabit Ethernet Controller
D+ Package Pin
C = CTX
TX
Silicon + Package
C = CTX
D- Package Pin
R = 50 Ω
R = 50 Ω
Figure 4. PCI Express Transmitter Test Load
4.5.1.2
Differential Receiver (RX) Input Specifications
Table 22. Differential Receiver (RX) Output Specifications
Symbol
Parameter
Min
Typ
Max
Units
UI
VRX-DIFFp-p
Unit Interval
399.88
400
400.12
ps
V
Differential Peak
to Peak Output
Voltage
0.175
0.4
N/A
N/A
N/A
1.2
N/A
150
Minimum RX
Eye Width
RTX-EYE
UI
AC Peak
Common Mode
Input Voltage
VRX-CM-ACp
N/A
mV
Differential
Return Loss
RLRX-DIFF
RLRX-CM
15
6
N/A
N/A
N/A
N/A
dB
dB
Common Mode
Return Loss
DC Differential
Input Impedance
ZRX-DIFF-DC
LRX-SKEW
80
100
120
20
Ω
Total Skew
N/A
N/A
ns
30
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
VRX-DIFF = 0 mV
VRX-DIFF = 0 mV
(D+ D- Crossing Point)
(D+ D- Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 5. PCI Express Receiver Eye Diagram
4.5.2
EEPROM Interface
Table 23. EEPROM Interface Time Specifications
Symbol
Parameter
Min
Typ
Max
Units
SCK clock
frequency
tSCK
0
2
2.1
MHz
tRI
Input rise time
Input fall time
SCK high timea
SCK low timea
CS high time
CS setup time
CS hold time
N/A
N/A
200
200
250
250
250
2.5 ns
2.5 ns
250
2
µs
µs
ns
ns
ns
ns
ns
tFI
2
tWH
tWH
tCS
N/A
N/A
N/A
N/A
N/A
250
N/A
N/A
N/A
tCSS
tCSH
Data-in setup
time
tSU
50
N/A
N/A
ns
tH
Data-in hold time
Output Valid
50
0
N/A
N/A
N/A
N/A
200
N/A
ns
ns
ns
tV
tHO
Output hold time
0
Output disable
time
tDIS
tWC
N/A
N/A
N/A
N/A
250
10
ns
Write cycle time
ms
a. 50% duty cycle.
Product Datasheet
31
82571EB/82572EI Gigabit Ethernet Controller
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
SCK
VIL
tWL
tWH
tSU
tH
VIH
SI
VALID IN
VIL
tV
tHO
tDIO
VIH
VIL
Hi-Z
Hi-Z
SO
Figure 6. EEPROM Interface Time Diagram
32
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.5.3
FLASH Interface
Table 24. FLASH Interface Time Specifications
Symbol
Parameter
Min
Typ
Max
Units
SCK clock
frequency
tSCK
0
15.625
20
MHz
tRI
Input rise time
Input fall time
SCK high timea
SCK low timea
CS high time
CS setup time
CS hold time
N/A
N/A
20
2.5 ns
2.5 ns
32
20
ns
ns
ns
ns
ns
ns
ns
tFI
20
tWH
tWH
tCS
N/A
N/A
N/A
N/A
N/A
20
32
25
N/A
N/A
N/A
tCSS
tCSH
25
250
Data-in setup
time
tSU
5
N/A
N/A
ns
tH
Data-in hold time
Output Valid
5
0
0
N/A
N/A
N/A
N/A
20
ns
ns
ns
tV
tHO
Output hold time
N/A
Output disable
time
tDIS
tEC
N/A
N/A
N/A
60
100
100
ns
Erase cycle time
per sector
µs
a. 50% duty cycle.
tCS
VIH
CS
VIL
tCSH
tcss
VIH
tWH
tWL
Sck
VIL
tSU
tH
VIH
SI
VALID IN
VIL
tHO
tDIS
tv
VOH
SO
HI-Z
HI-Z
VOL
Figure 7. FLASH Interface Time Diagram
Product Datasheet
33
82571EB/82572EI Gigabit Ethernet Controller
34
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
5.0
Package and Pinout Information
This section describes the 82571EB/82572EI device physical characteristics. The pin number-to-
signal mapping is indicated beginning with Table 25.
Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest information before finalizing a design.
5.1
Package Information
The 82571EB/82572EI device is a 256-lead flip-chip ball grid array (FC-BGA) measuring 17 mm
by 17 mm. The nominal ball pitch is 1 mm. See Figure 9.
Detail Area
0.43 mm
Solder Resist Opening
0.62 mm
Metal Diameter
Figure 8. 82571EB/82572EI Controller FC-BGA Package Ball Pad Dimensions
Product Datasheet
33
82571EB/82572EI Gigabit Ethernet Controller
Figure 9. 82571EB/82572EI Mechanical Specifications
34
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
5.2
5.3
Thermal Specification
The 82571EB/82572EI device is specified for operation when the ambient temperature (T ) is
A
within the range of 0° C to 55° C. For more information about the thermal characteristics of the
device, including operation outside of this range, please refer to the 82571EB/82572EB Thermal
Application Note, AP-490
Pinout Information
Signal names apply to both the 82571EB and the 82572EI unless there is a “/”, which indicates that
the the first name is for the 82571EB and the second name is for the 82572EI.
Table 25. PCI Express Signals
Signal
Pin
Signal
Pin
Signal
Pin
PERn0
PERp0
R2
T2
M2
N2
E1
F1
J2
PERn3
PERp3
PETn0
B1
C1
P1
PETn2
PETp2
D2
E2
A2
B2
G2
H2
T6
PERn1
PETn3
PERp1
PETp0
R1
L1
M1
K2
PETp3
PERn2
PETn1
PE_RCOMPn
PE_RCOMPp
PE_RSTn
PERp2
PETp1
PE_CLKn
PE_CLKp
Table 26. Power Management Signals
Signal
Pin
Signal
Pin
LAN0_DIS_N
B7
PE_WAKEn
P11
LAN1_DIS_N/
RSVD_B8
B8
T3
AUX_PWR
C8
DEV_OFF_N
Table 27. SMB/Fast Management Link Bus Signals
Signal
Pin
Signal
Pin
Signal
Pin
SMBCLK0/
FLBMCK
SMBALRT_N/
PCI_PWR_GOOD
T12
R12
SMBCLK1
SMBD1
P13
P12
R11
SMBD0/FLBMD
FLBSD
P7
FLBINTEX
R7
Product Datasheet
35
82571EB/82572EI Gigabit Ethernet Controller
Table 28. EEPROM and Serial FLASH Interface Signals
Signal
Pin
Signal
Pin
Signal
Pin
EE_SK
EE_DO
EE_DI
B12
A12
C12
EE_CS_N
FLSH_SCK
FLSH_CE_N
C13
R10
P10
FLSH_SI
T9
R9
FLSH_SO
Table 29. LED Signals
Signal
Pin
Signal
Pin
Signal
Pin
LED0_0
LED0_2
LED0_3
B11
B10
C10
LED0_1
C11
P8
LED1_3/RSVD_P9
LED1_1/RSVD_R8
P9
LED1_0/RSVD_P8
LED1_2/RSVD_T8
R8
T8
Table 30. Other Signals
Signal
Pin
Signal
Pin
SDP0_0
SDP0_1
SDP0_2
SDP0_3
B9
A9
C9
A8
SDP1_0/RSVD_P6
SDP1_1/RSVD_B6
SDP1_2/RSVD_C6
SDP1_3/RSVD_R6
P6
B6
C6
R6
Table 31. PHY and SERDES Signals
Signal
Pin
Signal
Pin
Signal
Pin
MDI_MINUS1_3/
RSVD_N15
MDI_MINUS0_0
B14
N15
SRDSI_0_MINUS
F16
MDI_PLUS1_3/
RSVD_N16
MDI_PLUS0_0
MDI_MINUS0_1
MDI_PLUS0_1
MDI_MINUS0_2
MDI_PLUS0_2
MDI_MINUS0_3
A14
B15
A15
C15
C16
D15
P16
N16
D14
E14
N14
M14
F15
SRDSI_0_PLUS
E16
L15
K15
C4
SRDSO_1_MINUS/
RSVD_L15
RBIAS0n
RBIAS0p
SRDSO_1_PLUS/
RSVD_K15
RBIAS1n/
RSVD_N14
SRDSB_SIG_DET/
RSVD_C4
RBIAS1p/
RSVD_M14
SRDSI_1_MINUS/
RSVD_L16
L16
M16
B4
SRDSI_1_PLUS/
RSVD_M16
SRDSO_0_MINUS
SRDSO_0_PLUS
MDI_PLUS1_2/
RSVD_P16
G15
SRDSA_SIG_DET
36
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Signal
Pin
Signal
Pin
Signal
Pin
MDI_MINUS1_0/
RSVD_R14
MDI_PLUS0_3
D16
R14
SRDS_RCOMPn
H14
MDI_PLUS1_1/
RSVD_T15
MDI_PLUS1_0/
RSVD_T14
T15
P15
T14
R15
SRDS_RCOMPp
H15
MDI_MINUS1_2/
RSVD_P15
MDI_MINUS1_1/
RSVD_R15
Table 32. Test Interface Signals
Signal
Pin
Signal
Pin
Signal
Pin
JTCK
JTDI
P4
IEEE_TEST0n
IEEE_TEST0p
A13
B13
THERM_Dp
THERM_Dn
D4
D5
R3
IEEE_TEST1n/
RSVD_T13
JTDO
P5
T13
R13
IEEE_TEST1p/
RSVD_R13
JTMS
P3
TEST_EN
R5
Table 33. Crystal Signals
Signal
Pin
XTAL1
XTAL2
J16
H16
Product Datasheet
37
82571EB/82572EI Gigabit Ethernet Controller
Table 34. Power Signals
Signal
Pin
Signal
Pin
Signal
Pin
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
A4
A10
D7
VCC18
VCC18
VCC18
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
M4
M5
K4
E7
E9
E13
F7
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
M9
M13
E12
F13
G12
K12
L13
M12
F12
L12
J4
D9
N7
N9
T5
T11
E10
F10
G10
H10
J10
K10
L10
M10
H4
F9
G7
G9
H7
H9
J7
J5
N4
J9
N5
K7
K9
L7
L9
M7
H5
K5
38
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 35. Ground Signals
Signal
Pin
Signal
Pin
Signal
Pin
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
A1
A16
B16
C2
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
H13
J3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A5
A11
D6
D8
D10
E5
J11
J12
J13
K1
C14
D1
D3
K3
E6
D11
D12
D13
E3
K11
K13
K14
K16
L2
E8
F5
F6
F8
E4
G6
G8
H6
H8
J6
E11
E15
F2
L3
L4
L5
F3
L11
L14
M3
M11
M15
N1
F4
J8
F11
F14
G1
K6
K8
L6
G3
L8
G4
N3
M6
M8
N6
N8
N10
T4
G5
N11
N12
N13
P2
G11
G13
G14
G16
H3
P14
R16
T1
T10
H11
H12
T16
Product Datasheet
39
82571EB/82572EI Gigabit Ethernet Controller
Table 36. Reserved and No Connect Signals
Note:
These pins are reserved by Intel and may have factory test functions. For normal operation, do not connect any circuitry to
these pins (allow them to “float”). Some configurations may require pull-up or pull-down resistors on these pins. Please
refer to the 82571EB/82572EI design guide for more information.
Signal
Pin
RSVD_A3
RSVD_ A6
DEVICE_DIS_N
RSVD_B3
A3
A6
A7
B3
B5
C3
C5
C7
H1
J1
RSVD_ B5
RSVD_ C3
RSVD_ C5
RSVD_ C7
RSVD_H1
RSVD_J1
RSVD_J14
RSVD_J15
LAN_PWR_GOOD
NC_T7
J14
J15
R4
T7
Table 37. Signal Names in Pin Order (Sheet 1 of 8)
Signal Name
Pin
VSSA
PETn3
A1
A2
RSVD_A3
VCC33
A3
A4
VSS
A5
RSVD_A6
DEVICE_DIS_N
SDP0_3
A6
A7
A8
SDP0_1
A9
VCC33
A10
A11
A12
A13
A14
A15
A16
VSS
EE_DO
IEEE_TEST0n
MDI_PLUS0_0
MDI_PLUS0_1
VSSA
40
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 2 of 8)
Signal Name
Pin
PERn3
PETp3
B1
B2
RSVD_B3
B3
SRDSA_SIG_DET
RSVD_B5
B4
B5
SDP1_1/RSVD_B6
LAN0_DIS_N
LAN1_DIS_N/RSVD_B8
SDP0_0
B6
B7
B8
B9
LED0_2
B10
B11
B12
B13
B14
B15
B16
C1
LED0_0
EE_SK
IEEE_TEST0p
MDI_MINUS0_0
MDI_MINUS0_1
VSSA
PERp3
VSSA
C2
RSVD_C3
C3
SRDSB_SIG_DET/RSVD_C4
RSVD_C5
C4
C5
SDP1_2/RSVD_C6
RSVD_C7
C6
C7
AUX_PWR
SDP0_2
C8
C9
LED0_3
C10
C11
C12
C13
C14
C15
C16
D1
LED0_1
EE_DI
EE_CS_N
VSSA
MDI_MINUS0_2
MDI_PLUS0_2
VSSA
PETn2
D2
VSSA
D3
THERM_Dp
THERM_Dn
VSS
D4
D5
D6
Product Datasheet
41
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 3 of 8)
Signal Name
Pin
VCC33
VSS
D7
D8
VCC33
VSS
D9
D10
D11
D12
D13
D14
D15
D16
E1
VSSA
VSSA
VSSA
RBIAS0n
MDI_MINUS0_3
MDI_PLUS0_3
PERn2
PETp2
VSSA
E2
E3
VSSA
E4
VSS
E5
VSS
E6
VCC11
VSS
E7
E8
VCC11
VCC18
VSSA
E9
E10
E11
E12
E13
E14
E15
E16
F1
VCC11
VCC11
RBIAS0p
VSSA
SRDSI_0_PLUS
PERp2
VSSA
F2
VSSA
F3
VSSA
F4
VSS
F5
VSS
F6
VCC11
VSS
F7
F8
VCC11
VCC18
VSSA
F9
F10
F11
F12
VCC11
42
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 4 of 8)
Signal Name
Pin
VCC11
VSSA
F13
F14
F15
F16
G1
SRDSO_0_MINUS
SRDSI_0_MINUS
VSSA
PE_RCOMPn
VSSA
G2
G3
VSSA
G4
VSSA
G5
VSS
G6
VCC11
G7
VSS
G8
VCC11
G9
VCC18
G10
G11
G12
G13
G14
G15
G16
H1
VSSA
VCC11
VSSA
VSSA
SRDSO_0_PLUS
VSSA
RSVD_H1
PE_RCOMPp
VSSA
H2
H3
VCC18
H4
VCC18
H5
VSS
H6
VCC11
H7
VSS
H8
VCC11
H9
VCC18
H10
H11
H12
H13
H14
H15
H16
J1
VSSA
VSSA
VSSA
SRDS_RCOMPn
SRDS_RCOMPp
XTAL2
RSVD_J1
PE_CLKn
J2
Product Datasheet
43
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 5 of 8)
Signal Name
Pin
VSSA
VCC11
VCC11
VSS
J3
J4
J5
J6
VCC11
VSS
J7
J8
VCC11
VCC18
VSSA
J9
J10
J11
J12
J13
J14
J15
J16
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
L1
VSSA
VSSA
RSVD_J14
RSVD_J15
XTAL1
VSSA
PE_CLKp
VSSA
VCC18
VCC18
VSS
VCC11
VSS
VCC11
VCC18
VSSA
VCC11
VSSA
VSSA
SRDSO_1_PLUS/RSVD_K15
VSSA
PETn1
VSSA
L2
VSSA
L3
VSSA
L4
VSSA
L5
VSS
L6
VCC11
VSS
L7
L8
44
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 6 of 8)
Signal Name
Pin
VCC11
L9
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VCC18
VSSA
VCC11
VCC11
VSSA
SRDSO_1_MINUS/RSVD_L15
SRDSI_1_MINUS/RSVD_L16
PETp1
PERn1
VSSA
VCC18
VCC18
VSS
VCC11
VSS
VCC11
VCC18
VSSA
VCC11
VCC11
RBIAS1p/RSVD_M14
VSSA
SRDSI_1_PLUS/RSVD_M16
VSSA
PERp1
N2
VSSA
N3
VCC11
VCC11
VSS
N4
N5
N6
VCC33
VSS
N7
N8
VCC33
VSS
N9
N10
N11
N12
N13
N14
VSSA
VSSA
VSSA
RBIAS1n/RSVD_N14
Product Datasheet
45
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 7 of 8)
Signal Name
Pin
MDI_MINUS1_3/RSVD_N15
MDI_PLUS1_3/RSVD_N16
PETn0
N15
N16
P1
VSSA
P2
JTMS
P3
JTCK
P4
JTDO
P5
SDP1_0/RSVD_P6
FLBSD
P6
P7
LED1_0/RSVD_P8
LED1_3/RSVD_P9
FLSH_CE_N
PE_WAKEn
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
R2
R3
SMBD1
SMBCLK1
VSSA
MDI_MINUS1_2/RSVD_P15
MDI_PLUS1_2/RSVD_P16
PETp0
PERn0
JTDI
LAN_PWR_GOOD
TEST_EN
R4
R5
SDP1_3/RSVD_R6
FLBINTEX
R6
R7
LED1_1/RSVD_R8
FLSH_SO
R8
R9
R10
FLSH_SCK
SMBALRT_N/PCI_PWR_GOOD R11
SMBD0/FLBMD
IEEE_TEST1p/RSVD_R13
MDI_MINUS1_0/RSVD_R14
MDI_MINUS1_1/RSVD_R15
VSSA
R12
R13
R14
R15
R16
T1
VSSA
PERp0
T2
DEV_OFF_N
T3
VSS
T4
46
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 8 of 8)
Signal Name
Pin
VCC33
PE_RSTn
T5
T6
NC_T7
T7
LED1_2/RSVD_T8
FLSH_SI
T8
T9
VSS
T10
T11
T12
T13
T14
T15
T16
VCC33
SMBCLK0/FLBMCK
IEEE_TEST1n/RSVD_T13
MDI_PLUS1_0/RSVD_T14
MDI_PLUS1_1/RSVD_T15
VSSA
Product Datasheet
47
82571EB/82572EI Gigabit Ethernet Controller
5.4
Visual Pin Assignments
A
B
C
D
E
F
G
H
MDI_
MDI_
SRDSI_0
_PLUS
SRDSI_0
_MINUS
VSSA
VSSA
VSSA
XTAL2
16
15
PLUS0_2
PLUS0_3
MDI_
MINUS0_1
MDI_
MINUS0_2
MDI_
MINUS0_3
SRDSO_0
_MINUS
SRDSO_0
_PLUS
MDI_PLUS0_1
VSSA
SRDS_RCOMPp
MDI_PLUS0_0
IEEE_TEST0n
EE_DO
MDI_MINUS0_0
IEEE_TEST0p
EE_SK
VSSA
EE_CS_N
EE_DI
RBIAS0n
VSSA
VSSA
VSSA
VSS
RBIAS0p
VCC11
VCC11
VSSA
VSSA
VCC11
VCC11
VSSA
VSSA
VSSA
SRDS_RCOMPn
VSSA
14
13
12
11
10
9
VCC11
VSSA
VSSA
VSS
LED0_0
LED0_1
LED0_3
SDP0_2
VSSA
VCC33
LED0_2
VCC18
VCC11
VCC18
VCC11
VCC18
VCC11
VCC18
SDP0_1
SDP0_0
VCC33
VCC11
LAN1_DIS_N/
RSVD_B8
SDP0_3
DEVICE_DIS_N
RSVD_A6
AUX_PWR
RSVD_C7
VSS
VCC33
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
8
LAN0_DIS_N
7
6
SDP1_1/
RSVD_B6
SDP1_2/
RSVD_C6
THERM_
Dn
VSS
RSVD_B5
RSVD_C5
VSS
VSS
VSSA
VSSA
VCC18
VCC18
5
4
SRDSB_SIG_DET/
RSVD_C4
THERM_
Dp
VCC33
SRDSA_SIG_DET
VSSA
VSSA
RSVD_A3
PETn3
RSVD_B3
PETp3
RSVD_C3
VSSA
VSSA
PETn2
VSSA
VSSA
PETp2
PERn2
VSSA
VSSA
PERp2
VSSA
PE_RCOMPn
VSSA
VSSA
3
2
1
PE_RCOMPp
RSVD_H1
VSSA
PERn3
PERp3
Figure 10. 82571EB/82572EI Visual Pin Assignment pt.1 (Top View)
48
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
J
K
L
M
N
P
R
T
SRDSI_1_MINUS/
RSVD_L16
SRDSI_1_PLUS/
RSVD_M16
MDI_PLUS1_3/
RSVD_N16
MDI_PLUS1_2/
RSVD_P16
XTAL1
RSVD_J15
RSVD_J14
VSSA
VSSA
VSSA
VSSA
16
15
14
13
12
11
SRDSO_1_
PLUS/RSVD_K15
SRDSO_1_
MINUS/RSVD_L15
MDI_MINUS1_3/
RSVD_N15
MDI_MINUS1_2
/RSVD_P15
MDI_MINUS1_1/
RSVD_15
MDI_PLUS1_1
/RSVD_T15
VSSA
RBIAS1p/
RSVD_M14
RBIAS1n/
RSVD_N14
MDI_MINUS1_0/
RSVD_R14
MDI_PLUS1_0
/RSVD_T14
VSSA
VSSA
VCC11
VSSA
VCC11
VCC11
VSSA
SMBCLK1
SMBD1
IEEE_TEST1p/
RSVD_R13
IEEE_TEST1n/
RSVD_T13
VCC11
VCC11
VSSA
VSSA
SMBCLK0/
FLBMCK
VSSA
SMBD0/FLBMD
SMBALRT_N/
PCI_PWR_GOOD
VSSA
VCC18
VCC11
VSSA
VCC18
VCC11
VSSA
VCC18
VCC11
VSSA
VCC18
VCC11
VSSA
VSS
PE_WAKEn
FLSH_CE_N
VCC33
VSS
FLSH_SCK
FLSH_SO
10
9
LED1_3/
RSVD_P9
VCC33
FLSH_SI
LED1_0/
LED1_1/
LED1_2/
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC33
VSS
8
RSVD_P8
RSVD_R8
RSVD_T8
FLBSD
FLBINTEX
NC_T7
7
6
SDP1_0/
RSVD_P6
SDP1_3/
RSVD_R6
PE_RSTn
VCC11
VCC11
VCC18
VCC18
VSSA
VSSA
VSSA
VSSA
VSSA
PETn1
VCC18
VCC18
VSSA
VCC11
VCC11
VSSA
PERp1
VSSA
JTDO
JTCK
JTMS
VSSA
PETn0
TEST_EN
RSVD
JTDI
VCC33
VSS
5
4
3
2
1
VSSA
DEV_OFF_N
PERp0
PE_CLKn
RSVD_J1
PE_CLKp
VSSA
PERn1
PETp1
PERn0
PETp0
VSSA
Figure 11. 82571EB/82572EI Visual Pin Assignment pt.2 (Top View)
Product Datasheet
49
82571EB/82572EI Gigabit Ethernet Controller
This page left blank intentionally.
50
Product Datasheet
©2020 ICPDF网 联系我们和版权申明