82577GBE [INTEL]
Intel® 82577 GbE PHY Specification Update; 英特尔® 82577千兆以太网PHY规范更新
| 型号： | 82577GBE |
| 厂家： | 
INTEL |
| 描述： | Intel® 82577 GbE PHY Specification Update |
| 文件： | 总8页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® 82577 GbE PHY Specification
Update
January 2012
Revision 1.7
82577 Specification Update
Revision History
Date
Revision
Description
Added Specification Change #1.
Added Sofware Clarification #1.
Added Specification Clarification 2.
January 2012
1.7
February 2010
January 2010
1.6
1.5
Added Thailand as a Country Of Origin (COO) to Figure 1.
Added Specification Clarification #1.
Removed Erratum #2.
Removed Specification Change #1.
Added Erratum #2.
November 2009
September 2009
1.4
1.3
Initial Public Release.
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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics
of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with
this information.
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specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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*Other names and brands may be claimed as the property of others.
Copyright © 2012, Intel Corporation. All Rights Reserved.
2
82577 Specification Update
1.1
Introduction and Scope
This document applies to the 82577 GbE PHY.
This document is an update to a published specification, the Intel® 82577 GbE PHY Datasheet. It is
intended for use by system manufacturers and software developers. All product documents are subject
to frequent revision, and new order numbers will apply. New documents may be added. Be sure you
have the latest information before finalizing your design.
1.2
Product Code and Device Identification
Table 1 and Figure 1 describe the various identifying markings on each lead-free device package:
Table 1. Markings
Tray/Tape and Reel
Device
Stepping
Top Marking
MM #
Description
903235
903236
903237
903238
Tape and Reel
Tray
82577LM
82577LM
82577LC
82577LC
A3
A3
A3
A3
WG82577LM
WG82577LM
WG82577LC
WG82577LC
Corporate Mobile and Workstation
Corporate Mobile and Workstation
Consumer Mobile
Tape and Reel
Tray
Consumer Mobile
Text "intel" (no caps) in Neo
Sans Intel medium font; no ®
Pin 1 identifier
Intel product name
Wafer lot no. concatenated
with assembler vendor code
©'09 then "e3" RoHS mark
Country of Origin (COO)
China or Thailand
Figure 1. Typical Top Marking Example With Identifying Marks (82577LC Shown)
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82577 Specification Update
Table 2. Device IDs
Device ID Code
Vendor ID
Device ID
Revision ID
0x8086
0x8086
0x10EA
0x10EB
N/A
N/A
82577LM
82577LC
1.3
Nomenclature Used In This Document
This document uses specific terms, codes, and abbreviations to describe changes, errata, sightings
and/or clarifications that apply to silicon/steppings. See Table 3 for a description.
Table 3. Terms, Codes, Abbreviations
Name
Description
Specification
Changes
Modifications to the current published specifications. These changes will be incorporated in the next release
of the specifications.
Design defects or errors. Errata may cause device behavior to deviate from published specifications.
Hardware and software designed to be used with any given stepping must assume that all errata documented
for that stepping are present on all devices.
Errata
Specification
Clarifications
Greater detail or further highlights concerning a specification’s impact to a complex design situation. These
clarifications will be incorporated in the next release of the specifications.
Documentation
Changes
Typos, errors, or omissions from the current published specifications. These changes will be incorporated in
the next release of the specifications.
If the errata applies to a stepping, “Yes” is indicated for the stepping (for example: “A0=Yes” indicates errata
applies to stepping A0). If the errata does not apply to stepping, “No” is indicated (for example: “A0=No”
indicates the errata does not apply to stepping A0).
Yes or No
Doc
Document change or update that will be implemented.
This erratum is intended to be fixed in a future stepping of the component.
This erratum has been previously fixed.
Fix
Fixed
NoFix
Eval
There are no plans to fix this erratum.
Plans to fix this erratum are under evaluation.
(No mark) or
(Blank box)
This erratum is fixed in listed stepping or specification change does not apply to listed stepping.
This Item is either new or modified from the previous version of the document.
Red Change
Bar/or Bold
DS
Datasheet
PDG
EDS
Platform Design Guide
External Data Specification
4
82577 Specification Update
1.4
Changes, Errata, Clarifications
See Section 1.3 for an explanation of terms, codes, and abbreviations used in the following tables and
discussions.
Table 4.
Summary of Changes
1.4.1 Specification Changes............................................................................ 5
1. Updates to PXE/iSCSI EEPROM Words ........................................... 5
Specification Clarifications ...................................................................... 6
1.4.2
1.4.3
1.
2.
PHY Does Not Maintain Gigabit Link in Low Power States ................. 6
Activity LED Functionality ............................................................ 6
Software Clarifications ........................................................................... 6
1.
While in TCP Segmentation Offload, Each Buffer is Limited to 64 KB.. 6
Documentation Changes......................................................................... 6
External Errata ..................................................................................... 7
1.4.4
1.4.5
1.
9 KB Jumbo Frames Not Supported With PCI Express* (PCIe*) Spread
Spectrum Clocking (SSC) ............................................................ 7
1.4.1
Specification Changes
1. Updates to PXE/iSCSI EEPROM Words
Word 0x30 (bits 2:0) is now defined as follows:
CLP (Combo)
Executes
iSCSI Boot Option ROM
CTRL-D Menu
FCoE Boot Option ROM
CTRL-D Menu
Bit(s)
Value
Port Status
Displays port as PXE. Allows
changing to Boot Disabled,
iSCSI Primary or Secondary.
Displays port as PXE.
Allows changing to Boot
Disabled, FCoE enabled.
0
PXE
PXE
Displays port as Disabled.
Allows changing to iSCSI
Primary/Secondary.
Displays port as Disabled.
Allows changing to FCoE
enabled.
1
2
Boot Disabled
iSCSI Primary
NONE
iSCSI
Displays port as iSCSI
Primary. Allows changing to
Boot Disabled, iSCSI
Secondary.
Displays port as iSCSI.
Allows changing to Boot
Disabled, FCoE enabled.
2:0
Displays port as iSCSI
Secondary. Allows changing
to Boot Disabled,
Displays port as iSCSI
Allows changing to Boot
Disabled, FCoE enabled.
3
iSCSI Secondary
iSCSI
iSCSI Primary.
Displays port as FCoE. Allows
changing port to Boot
Disabled, iSCSI Primary or
Secondary.
Displays port as FCoE
Allows changing to Boot
Disabled.
4
FCoE
FCOE
7:5
Reserved
Same as disabled.
Same as disabled.
Same as disabled.
4:3
5
Same a before.
Bit 5: formerly used to indicate iSCSI enable / disable, is no longer valid and is not checked by software.
Same a before.
15:7
5
82577 Specification Update
1.4.2
Specification Clarifications
1. PHY Does Not Maintain Gigabit Link in Low Power States
Clarification: While operating in power states less than D0 or operating system states other than S0,
the PHY is designed to negotiate to the lowest speed possible, and maintains a link in
those states only at 10 Mb/s or 100 Mb/s. If the PHY is connected to a link partner that is
only capable of gigabit connections, the link is lost in these lower power states. This
limitation is due to power requirements imposed by energy saving initiatives (such as
Energy Star), as the additional power required to maintain gigabit connections might
cause the system to exceed the level needed to meet the specifications.
Impact:
When attached to a port that is limited to gigabit speed connections, the PHY loses link in
low power states, and therefore network functions normally available in those states,
such as Wake on LAN (WoL) or remote management, is not possible in that environment.
2. Activity LED Functionality
Clarification: If a system based on the 82577 is connected to a hub, the Activity LED blinks for all
network traffic present on the hub, not just traffic destined to the local port. Connecting
the system to a switch or router filters out most traffic not addressed to the local port.
1.4.3
Software Clarifications
1. While in TCP Segmentation Offload, Each Buffer is Limited to 64 KB
Problem Description:
Clarification: The 82577 supports 256 KB TCP packets; however, each buffer is limited to 64 KB since
the data length field in the transmit descriptor is only 16 bits. This restriction increases
driver implementation complexity if the operating system passes down a scatter/gather
element greater than 64 KB in length. This can be avoided by limiting the offload size to
64 KB.
Investigation has concluded that the increase in data transfer size does not provide any
noticeable improvements in LAN performance. As a result, Intel network software drivers
limit the data transfer size in all drivers to 64 KB.
Please note that Linux operating systems only support 64 KB data transfers.
For further details about how Intel network software drivers address this issue, refer to
Technical Advisory TA-191.
1.4.4
Documentation Changes
None active.
6
82577 Specification Update
1.4.5
Errata
1. 9 KB Jumbo Frames Not Supported With PCI Express* (PCIe*) Spread Spectrum Clocking (SSC)
Problem:
82577LM is unable to support 9 KB jumbo frames when PCIe SSC is enabled in Intel®
Series Express Chipset.
5
Implication: Enabling 9 KB jumbo frames with PCIe SSC enabled might result in data overflow/
underflow errors resulting in packets transmitted/received with CRC errors.
Workaround: For 9 KB jumbo frames support, PCIe SSC must be disabled.
Status:
No fix for 9 KB jumbo frames.
7
82577 Specification Update
Note:
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