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Intel® 82575EB Gigabit Ethernet Controller Datasheet; 英特尔82575EB千兆以太网控制器数据表
82575EB
型号： 82575EB
厂家： INTEL    INTEL
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Intel® 82575EB Gigabit Ethernet Controller Datasheet
英特尔82575EB千兆以太网控制器数据表

控制器 以太网
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Intel® 82575EB Gigabit Ethernet  
Controller Datasheet  
LAN Access Division  
317679-004  
Revision: 2.11  
January 2011  
®
Intel 82575EB Gigabit Ethernet Controller — Legal  
Legal  
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SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked  
"reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility  
whatsoever for conflicts or incompatibilities arising from future changes to them. The information here  
is subject to change without notice. Do not finalize a design with this information.  
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before  
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Copyright © 2006,2007,2010,2011; Intel Corporation. All Rights Reserved.  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
2
®
Revisions — Intel 82575EB Gigabit Ethernet Controller  
Revisions  
Date  
Revision  
Description  
8/2005  
1/2006  
7/2006  
2/2007  
0.10  
0.25  
0.50  
0.75  
Initial Release  
Added general information, updated pins list  
Removed information regarding Fast Management Link; added general information  
Added measured power values; corrected Visual Pin Assignment Diagrams (RBIAS0_N and  
RBIAS1_N corrected to VSS).  
6/2007  
1.0  
2.0  
Updated classification, changed RMII to NC-SI, updated pin list, updated NC-SI timing specs.  
changed LAN_PWR_GOOD to Internal_Power_On_Reset.  
12/13/2010  
Section 2.1, PCI Express Features - Support for x4, x2, and x1 modes now indicated.  
Section 3.5, MDIO Signals - MDC pin now listed as type 0.  
Section 3.7, LED Signals - Introductory note updated.  
Section 9.2, Pin Map - Corrected information applicable to pins AC5, AC16, AC17, AD16,  
AD17, B12, K14.  
1/28/2011  
1/28/2011  
2.1  
Update Doc title to match brand string.  
Table 7, DC Characteristics - VCC(1.0) row updated. See bold.  
Build issue corrected.  
2.11  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
3
®
Intel 82575EB Gigabit Ethernet Controller — Contents  
Contents  
1.0  
1.1  
1.2  
1.3  
Introduction .............................................................................................................................5  
Document Scope .........................................................................................................................5  
References .................................................................................................................................6  
Block Diagram.............................................................................................................................6  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
Features of the 82575EB Gigabit Ethernet Controller................................................................7  
PCI Express Features ...................................................................................................................7  
MAC-Specific Features..................................................................................................................7  
PHY-Specific Features ..................................................................................................................8  
Host Offloading Features ..............................................................................................................8  
Manageability Features.................................................................................................................9  
Additional Device Features.......................................................................................................... 10  
Technology Features.................................................................................................................. 10  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
Signal Descriptions and Pinout List.........................................................................................11  
Signal Type Definitions............................................................................................................... 11  
PCI Express Interface................................................................................................................. 12  
Power Management Signals ........................................................................................................ 12  
System Management Interface Signals ......................................................................................... 13  
MDIO Signals............................................................................................................................ 13  
SPI EEPROM and FLASH Signals................................................................................................... 13  
LED Signals .............................................................................................................................. 14  
Other Signals............................................................................................................................ 15  
Crystal Signals.......................................................................................................................... 15  
PHY Analog Signals.................................................................................................................... 15  
Serializer/Deserializer Signals ..................................................................................................... 16  
Test Interface Signals ................................................................................................................ 16  
Power Supply Connections.......................................................................................................... 17  
Digital and Analog Supplies .................................................................................................. 17  
Grounds, Reserved Pins and No Connects ............................................................................... 17  
3.9  
3.10  
3.11  
3.12  
3.13  
3.13.1  
3.13.2  
4.0  
Pinout/Signal Name ...............................................................................................................18  
5.0  
5.1  
5.2  
5.2.1  
5.2.2  
5.3  
Power Requirements ..............................................................................................................37  
Targeted Absolute Maximum Ratings............................................................................................ 37  
Targeted Recommended Operating Conditions............................................................................... 38  
General Operating Conditions................................................................................................ 38  
Voltage Ramp and Sequencing Recommendations.................................................................... 38  
Thermal Information.................................................................................................................. 40  
6.0  
6.1  
6.2  
6.3  
6.4  
Electrical Specification............................................................................................................41  
DC Specifications....................................................................................................................... 41  
Resets ..................................................................................................................................... 45  
Pull-up and Pull-down Specifications and Signals............................................................................46  
Targeted AC Characteristics ........................................................................................................ 49  
EEPROM Interface ............................................................................................................... 50  
FLASH Interface.................................................................................................................. 51  
NC-SI Interface................................................................................................................... 52  
SMBus Interface.................................................................................................................. 53  
6.4.1  
6.4.2  
6.4.3  
6.4.4  
7.0  
Crystal Requirements .............................................................................................................55  
LED Configuration...................................................................................................................56  
8.0  
9.0  
9.1  
9.2  
Mechanical Information..........................................................................................................57  
Targeted Package Information..................................................................................................... 57  
Pin Map.................................................................................................................................... 59  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
4
®
Introduction — Intel 82575EB Gigabit Ethernet Controller  
1.0 Introduction  
®
The Intel 82575EB Gigabit Ethernet Controller is a single, compact component with two fully  
integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. The device uses  
the PCI Express Base Specification, Rev.1.1RD.  
The 82575EB provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and  
10BASE-T applications (802.3z, 802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer  
(SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to  
managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic  
across its transaction, link, and physical/logical layers. The SERDES can be used in SGMII mode to  
connect to external PHY, either on-board or via the SFP connector.  
The Intel 82575EB’s on-board System Management Bus (SMB) ports enable network manageability  
implementations required by information technology personnel for remote control and alerting via the  
LAN. With SMB, management packets can be routed to or from a management processor. Enhanced  
pass-through capabilities also allow system remote control over standardized interfaces. Also included  
is a new manageability interface, NC-SI that supports the DMTF preOS sideband protocol. An internal  
management interface called MDIO enables the MAC (and software) to monitor and control the PHY.  
Both ports support the Wake on LAN feature.  
The 82575EB with PCI Express architecture is designed for high performance and low memory latency.  
The device is optimized to connect to a system Memory Control Hub (MCH) using four PCI Express  
lanes. Alternatively, the 82575EB can connect to an I/O Control Hub that has a PCI Express interface.  
Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and  
data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit Ethernet and  
independent transmit and receive queues, the 82575EB efficiently handles packets with minimum  
latency. The 82575EB includes advanced interrupt handling features, including MSI-X support. The  
82575EB uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached  
on chip. A large 48 KByte per port on-chip packet buffer maintains superior performance. In addition,  
using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum  
calculations and TCP segmentation.  
The 82575EB operation can be configured using EEPROM and FLASH; it can be also be used in EEPROM-  
less configurations.  
The 82575EB is packaged in a 25mm X 25mm, 576-pin flip chip ball grid array (FCBGA).  
1.1  
Document Scope  
This document contains targeted datasheet specifications for the 82575EB, including signal  
descriptions, DC and AC parameters, packaging data, and pinout information.  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
5
®
Intel 82575EB Gigabit Ethernet Controller — References  
1.2  
References  
The primary references include the following manuals:  
• Intel® 82575EB Gigabit Controller Datasheet  
• Intel® 82575EB Gigabit Controller Design Guide  
• Intel® 82575EB Gigabit Controller Manageability  
• Intel® 82575EB Gigabit Controller Software Developer's Manual and EEPROM Guide  
• Intel® 82575EB Gigabit Controller Thermal Design Considerations  
• Intel® 82575EB Gigabit Controller Specification Update  
1.3  
Block Diagram  
FLASH  
EEPROM  
LAN  
PCI Express (x4)  
Host  
Port 0  
Port 1  
SerDes/SGMII/SFP  
82575  
RMII  
SMB  
SerDes/SGMII/SFP  
LAN  
Management  
LEDs  
SDP  
JTAG  
Figure 1.  
82575EB Gigabit Ethernet Controller Block Diagram  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Datasheet  
6
Revision: 2.11  
January 2011  
®
Features of the 82575EB Gigabit Ethernet Controller — Intel 82575EB Gigabit Ethernet  
Controller  
2.0 Features of the 82575EB Gigabit  
Ethernet Controller  
2.1  
PCI Express Features  
Features  
Benefits  
Bus sharing not required  
Uses x4 PCI Express interface on MCH device.  
Supports x4, x2, and x1 modes.  
•
•
•
•
•
•
•
Low latency path to memory  
Relieves congestion for IO devices connected to ICH  
Supports Gigabit Ethernet at full wire speed  
Compatible extensions to PCI power management and ACPI  
PE_WAKE available for wakeup event  
Peak bandwidth 2 GB/s in each direction per PCI Express lane  
PCI Express Power Management  
High bandwidth density per pin  
Less congested board routing  
64-bit address support for systems using more than 4 GB of  
physical memory  
2.2  
MAC-Specific Features  
Features  
Benefits  
I/O Acceleration Technology2 (IOAT2)  
•
•
Accelerated TCP I/O.  
Four optimized transmit and receive queues  
Network packets handled without waiting or buffer  
overflow.  
IEEE 802.3x compliant flow control support with software  
controllable pause times and threshold values  
•
Control over the transmissions of pause frames through  
software or hardware triggering  
•
•
•
Frame loss reduced from receive overruns  
Efficient use of PCI Express bandwidth  
Efficient packet prioritization  
Caches up to 64 packet descriptors (per queue)  
Separate transmit and receive queues per port  
Programmable host memory receive buffers (256 Bytes to 16  
KBytes) and cache line size (64 Bytes to 128 Bytes)  
•
Efficient use of PCI Express bandwidth  
Wide, pipelined internal data path architecture  
•
•
•
•
•
•
Low latency data handling  
Superior DMA transfer rate performance  
No external FIFO memory requirements  
FIFO size adjustable to application  
Dual 8 KByte configurable Transmit and Receive FIFO buffers  
Descriptor ring management hardware for transmit and receive  
Optimized descriptor fetching and write-back mechanisms  
Simple software programming model  
Efficient system memory and use of PCI Express bandwidth  
Mechanism available for reducing interrupts generated by  
transmit and receive operations  
•
Maximizes system performance and throughput  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
7
®
Intel 82575EB Gigabit Ethernet Controller — PHY-Specific Features  
Features  
Benefits  
Support for transmission and reception of packets up to 9.5 kB  
MSI-X Support  
•
•
Enables jumbo frames  
Part of the PCI standard, enables sending interrupt  
messages to specific CPUs in a multiple-cores platform  
2.3  
PHY-Specific Features  
Features  
Benefits  
IEEE 802.3x compliant flow control support with software  
controllable pause times and threshold values  
Control over the transmissions of pause frames through  
software or hardware triggering  
Frame loss reduced from receive overruns  
Reliable operation at greater distances  
Reliability  
Line Length >140m  
Operates with worst-case cable  
Supports carrier extension and packet bursting (half duplex)  
Auto-negotiation with support for Next Page  
PMA loopback capable (No echo cancel)  
Advanced Power Management -  
Improves performance  
Improves performance and reliability  
Facillitates testing/troubleshooting  
Improves power capabilities  
•
•
Low power link up  
"Smart Power Down - Link disconnect  
Support for limited auto MDIO register init - limited number of  
registers  
Improves performance  
Ease of design  
Fiber/Copper switch support  
SERDES Signal Detect and support of non-AN partner  
Smart Speed  
Auto crossover for MDI  
Smart Power Down  
Advanced Cable Diagnostics  
2.4  
Host Offloading Features  
Features  
Benefits  
Transmit and receive IP, TCP and UDP checksum off-loading  
capabilities  
•
Lower CPU utilization  
Transmit TCP segmentation  
•
•
Increased throughput and lower CPU utilization  
Large send offload feature (in Microsoft* Windows* XP)  
compatible  
IPv6 Offloading  
•
•
Checksum and segmentation capability extended to new  
standard packet type  
Header split replication in receive  
Helps the driver to focus on the relevant part of the packet  
without the need to parse it.  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
8
®
Manageability Features — Intel 82575EB Gigabit Ethernet Controller  
Features  
Benefits  
Advanced packet filtering  
•
•
•
•
16 exact matched packets (unicast or multicast)  
4096-bit hash filter for multicast frames  
Promiscuous (unicast and multicast) transfer mode support  
Optional filtering of invalid frames  
IEEE 802.1q VLAN support with VLAN tag insertion, stripping  
and packet filtering for up to 4096 VLAN tags  
•
Ability to create multiple virtual LAN segments  
Insert in Tx and extract in Rx  
Double Vlan  
•
•
Descriptor ring management hardware for transmit and receive  
Optimized fetching and write-back mechanisms for efficient  
system memory and PCI bandwidth usage  
9.5 kByte jumbo frame support  
•
High throughput for large data transfers on networks  
supporting jumbo frames  
Receive Side Scaling (RSS)  
VMDq  
•
•
Multiple Rx queues  
Virtualization environment. In this environment, packets  
dedicated to different virtual machines can be routed to  
different queues, thus easing the routing of these packets  
to the target machine.  
Direct Cache Access (DCA)  
•
•
The IO device activates a pre-fetch engine in the CPU that  
loads the data into the CPU cache ahead of time, before  
use, eliminating cache misses and reducing CPU load.  
Fragmented UDP checksum offload for packet reassembly  
2.5  
Manageability Features  
Features  
Benefits  
Advance Pass Through-compatible management packet Tx/Rx  
support  
Alert on LAN 2.0  
Both ports support Wake on LAN (WoL)  
SMBus port  
Network management flexibility  
NC-SI high-bandwidth interface  
On-board microcontroller  
Manageability DMTF preOS sideband protocol support  
Promotes customized designs  
Allows packets routing to and from either LAN port and a  
server management processor  
Preboot eXecution Environment (PXE) Flash interface support  
(32-bit and 64-bit)  
Local Flash interface for PXE image  
iSCSI Boot  
Network Management Feature  
Compliance with PCI Power Management 1.1 and ACPI 2.0  
register set compliant including:  
PCI power management capability requirements for PC and  
embedded applications  
•
•
D0 and D3 power states  
Network Device Class Power Management Specification 1.1  
SNMP and RMON statistic counters  
Easy system monitoring with industry standard consoles  
SDG 3.0, WfM 3.0, and PC2001 compliance  
Remote network management capabilities through DMI 2.0  
and SNMP software  
Watchdog Timer  
Used to give an indication to the manageability firmware or  
external devices that the 82575EB or the driver is not  
functioning.  
SGMII interface for embedded applications with an I2C or  
MDC/MDIO control interface.  
Ease of embedded designs  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
9
®
Intel 82575EB Gigabit Ethernet Controller — Additional Device Features  
2.6  
Additional Device Features  
Features  
Two complete Gigabit Ethernet connections in a single device  
Benefits  
•
•
•
•
•
•
•
Inherent dual port teaming ability  
High availability using one port for failover  
Higher throughput than single Gigabit Ethernet port  
Lower latency due to one electrical load on the bus  
Saves critical board space  
Reduced multi-port Gigabit Ethernet costs  
Integrated SERDES  
Supports backplane and fiber applications as well as  
copper-based Gigabit via the SGMII interface  
Four activity and link indication outputs (per port) that directly  
drive LEDs  
•
•
Link and activity indications (10, 100, and 1000 Mbps) on  
each port  
Programmable LED functionality  
Software definable function (speed, link, and activity) and  
blinking allowing flexible LED implementations  
Internal PLL for clock generation can use a 25 MHz crystal  
JTAG (IEEE 1149.1) Test Access Port built in silicon  
•
•
•
•
Lower component count and system cost  
Simplified testing using boundary scan  
Supports the IDCODE instruction  
Four software definable pins per port  
Additional flexibility for LEDs or other low speed  
I/O devices  
Provides loopback capabilities  
Four-wire SPI EEPROM interface  
•
•
Validates silicon integrity  
Standard  
2.7  
Technology Features  
Features  
Benefits  
576-pin Flip-Chip Ball Grid Array (FC-BGA) package  
Operating temperature:  
•
•
25 mm X 25 mm  
1000BASE-T, 0 °C to 55 °C*  
Simple thermal design  
1000BASE-SX/LX (or SERDES backplane), 0 °C to 70 °C  
Storage temperature 65 °C to 140 °C  
Typical targeted power dissipation:  
2.43 W @ D0 1000 Mbps  
•
•
Conditions: FF materials, nominal voltage,  
115 °C  
0.79 W @ D3cold 100 Mbps (wakeup enabled)  
0.29 W @ D3cold (wakeup disabled)  
Maxmum Payload Size: 128 and 256  
Minimizes impact of incorporating Gigabit  
instead of Fast Ethernet.  
Max number of transactions (TLP) supported on PCIe: Four TX DMA requests  
+ 1 TX descriptor + 1 RX descriptor.  
* For information about operating the 82575EB outside of this range, please refer to the 82575EB Thermal Management Application  
Note.  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
10  
®
Signal Descriptions and Pinout List — Intel 82575EB Gigabit Ethernet Controller  
3.0 Signal Descriptions and Pinout List  
The targeted signal names are subject to change without notice. Verify with your local Intel sales office  
that you have the latest information before finalizing a design.  
3.1  
Signal Type Definitions  
The signals of the 82575EB are electrically defined as follows:  
Name  
Definition  
DC specification  
I
Input  
See Table 9  
See Table 9  
See Table 9  
See Table 10  
Standard input only digital signal.  
Output  
O
Standard output only digital signal.  
Tri-state  
TS  
OD  
Bi-directional three-state digital input/output signal.  
Open Drain  
Wired-OR with other agents.  
The signaling agent asserts the OD signal, but the  
signal is returned to the inactive state by a weak  
pull-up resistor. The pull-up resistor may require two  
or three clock periods to fully restore the signal to  
the de-asserted state.  
A
P
Analog  
See Table 10  
See Table 10  
PCI Express*, SERDES, or PHY analog signal.  
Power  
Power connection, voltage reference, or other  
reference connection.  
®
317679-004  
Revision: 2.11  
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
11  
®
Intel 82575EB Gigabit Ethernet Controller — PCI Express Interface  
3.2  
PCI Express Interface  
Symbol  
Type  
Name and Function  
PER_0_N  
A(I)  
High Speed Serial Receive Data  
PER_0_P  
PER_1_N  
These signals connect to corresponding PETn and PETp signals on a system motherboard or a  
PCI Express connector. Series AC coupling capacitors are required at the transmitter end. The  
PCI Express differential inputs are clocked at 2.5 Gb/s.  
PER_1_P  
PER_2_N  
PER_2_P  
PER_3_N  
PER_3_P  
PET_0_N  
PET_0_P  
PET_1_N  
PET_1_P  
PET_2_N  
PET_2_P  
PET_3_N  
PET_3_P  
PE_RCOMP  
A(0)  
High Speed Serial Transmit Data  
These signals connect to corresponding PERn and PERp signals on a system motherboard or a  
PCI Express connector. Series AC coupling capacitors are required at the 82575EB end. The PCI  
Express differential outputs are clocked at 2.5 Gb/s.  
A
A
I
High Speed Serial Impedance Compensation  
Connect the recommended resistor value 1.4K from this ball to ground.  
100 MHz Differential Clock for the PCI Express Interface  
The reference clock is furnished by the system and has a 300 ppm frequency tolerance.  
PCI Express Reset  
PE_CLK_P  
PE_CLK_N  
PE_RST_N  
When the signal is low, all PCI Express functions are held in reset. When the signal is high, it  
denotes that main power is available to the 82575EB and the reference clock is running.  
In systems with a PCI Express add-in card, this signal routes to the connector.  
Wake  
PE_WAKE_N  
OD  
The device drives this signal low when it receives a wake-up event and either the PME Enable bit  
in the Power Management Control/Status Register or the Advanced Power Management Enable  
(APME) bit of the Wake-up Control Register (WUC) is 1b.  
3.3  
Power Management Signals  
Symbol  
Type  
Name and Function  
AUX_PWR  
I
Auxiliary Power Present.  
If the Auxiliary Power signal is high, then auxiliary power is present and the 82575device  
should support the D3  
power state.  
cold  
LAN0_DIS_N  
LAN1_DIS_N  
I
LAN Disables 0 and 1  
Disables individual Ethernet ports. State is latched upon a rising edge of PERST_N or a PCI  
Express reset event. This pin has an internal pull-up resistor.  
DEV_OFF_N  
I
I
Device Off  
Asynchronously disables Ethernet controller.  
MAIN_PWR_OK  
Main Power OK  
Indicates that platform main power is up. Must be connected externally.  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
12  
®
System Management Interface Signals — Intel 82575EB Gigabit Ethernet Controller  
3.4  
System Management Interface Signals  
Symbol  
Type  
Name and Function  
SMBCLK  
SMBD  
OD  
SMB Clock  
The SMB Clock signal is an open drain signals for the serial SMB interface.  
OD  
OD  
SMB Data  
The SMB Data signal is an open drain signal for the serial SMB interface.  
SMB Alert  
SMBALRT_N  
The SMB Alert signal is an open drain signal for serial SMB Port A.It acts as an alert input in  
82559 compatible mode.  
NCSI_CLK_IN  
I
NCSI Reference Clock Input. Synchronous clock reference for receive, transmit and control  
interface. It is a 50MHz clock /- 50 ppm.  
NCSI_CLK_OUT  
O
NCSI Reference Clock Output. Synchronous clock reference for receive, transmit and  
control interface. It is a 50MHz clock /- 50 ppm. Serves as a clock source to the BMC and  
the 82575EB (when configured so).  
NCSI_CRS_DV  
NCSI_RXD[1]  
NCSI_RXD[0]  
NCSI_TX_EN  
NCSI_TXD[1]  
NCSI_TXD[0]  
O
O
Carrier Sense / Receive Data Valid  
Receive Data. Data signals from the device to the BMC  
I
I
Transmit Enable  
Transmit Data. Data signals from BMC to the device  
3.5  
MDIO Signals  
Symbol  
Type  
Name and Function  
MDC  
O
Management Data Clock. Used by the PHY as a clock timing reference for information transfer on  
the MDIO signal. The MDC is not required to be a continuous signal and can be frozen when no  
management data is transferred. The MDC signal has a maximum operating frequency of  
2.5MHz.  
MDIO  
I/O  
Management Data I/O. This internal signaling between the MAC and PHY logically represents a  
bi-directional data signal used to transfer control information and status to and from the PHY (to  
read and write the PHY management registers ). Asserting and interpreting value(s) on this  
interface requires knowledge of the special MDIO protocol to avoid possible internal signal  
contention or miscommunication to/from the PHY  
3.6  
SPI EEPROM and FLASH Signals  
Symbol  
Type  
TS  
Name and Function  
EE_DI  
EEPROM Data Input  
The EEPROM Data Input pin is used for output to the SPI EEPROM memory device.  
EEPROM Data Output  
EE_DO  
I
The EEPROM Data Output pin is used for input from the SPI EEPROM memory device. The EE_DO  
includes an internal pull-up resistor.  
EE_CS_N  
TS  
EEPROM Chip Select  
The EEPROM Chip Select signal is used to enable the device.  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
13  
®
Intel 82575EB Gigabit Ethernet Controller — LED Signals  
Symbol  
EE_SK  
Type  
TS  
Name and Function  
EEPROM Serial Clock  
The EEPROM Shift Clock provides the clock rate for the SPI EEPROM interface, which is  
approximately 2 MHz.  
FLSH_CE_N  
FLSH_SCK  
FLSH_SI  
TS  
TS  
TS  
I
FLASH Chip Enable Output.  
Used to enable FLASH device.  
FLASH Serial Clock Output.  
FLASH Serial Data Input.  
This pin is an output to the memory device.  
FLASH Serial Data Output  
FLSH_SO  
This pin is an input from the memory device.  
3.7  
LED Signals  
Note:  
LED outputs are assumed to normally be connected to the negative side (cathode) of an  
external LED.  
Symbol  
Type  
Name and Function  
LED0_0  
O
LED0_0. Programmable LED output for Port A. As the Link LED, it indicates link connectivity on  
Port A.  
LED0_1  
LED0_2  
O
O
LED0_1. Programmable LED output for Port A. As the Activity LED, it flashes to indicate receive  
activity on Port A for packets destined for this node.  
LED0_2  
Programmable LED output for Port A. As the Link 100 LED, it indicates link at 100 Mbps for Port A.  
LED0_3  
LED0_3  
O
Programmable LED output for Port A. As the Link 1000 LED, it indicates link at 1000 Mbps for Port  
A.  
LED1_0  
LED1_1  
O
O
LED1_0.  
Programmable LED output for Port B. As the Link LED, it indicates link connectivity on Port B.  
LED1_1  
Programmable LED output for Port B. As the Activity LED, it flashes to indicate receive activity on  
Port B for packets destined for this node.  
LED1_2  
LED1_3  
O
O
LED1_2  
Programmable LED output for Port B. As the Link 100 LED, it indicates link at 100 Mbps for Port B.  
LED1_3  
Programmable LED output for Port B. As the Link 1000 LED, it indicates link at 1000 Mbps for Port  
B.  
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®
Other Signals — Intel 82575EB Gigabit Ethernet Controller  
3.8  
Other Signals  
Symbol  
Type  
Name and Function  
SDP0_0  
SDP0_1  
SDP0_2  
SDP0_3  
SDP1_0  
SDP1_1  
SDP1_2  
SDP1_3  
TS  
Software Defined Pin (SDP)  
The Software Defined Pins are programmable with respect to input and output capability. These pins  
also can optionally be configured as interrupt inputs. SDP signals default to inputs upon power-up, but  
can be configured differently by the EEPROM.  
3.9  
Crystal Signals  
Symbol  
Type  
Name and Function  
XTAL1  
AI  
Crystal One  
The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel resonant crystal with  
a frequency tolerance of 30 ppm or better. The other end of the crystal should be connected to XTAL2.  
XTAL2  
AO  
Crystal Two  
Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.  
3.10  
PHY Analog Signals  
Symbol  
Type  
Name and Function  
Compensation Reference Resistor.  
A 1.4 K, 1% tolerance resistor should be used. RBIAS_N should also be connected to  
ground (VSS).  
RBIAS0_P/RBIAS1_P  
A
A
MDI0_P_0  
MDI0_N_0  
MDI1_P_0  
MDI1_N_0  
Media Dependent Interface [0]  
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X  
configuration, MDIp0/MDIn0 corresponds to BI_DB+/-.  
100BASE-TX: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and  
in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair.  
10BASE-T: In MDI configuration, MDIAp0/MDI_MINUS0_0 is used for the transmit  
pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair.  
MDI0_P_1  
MDI0_N_1  
MDI1_P_1  
MDI1_N_1  
A
Media Dependent Interface [1]  
1000BASE-T: In MDI configuration, MDIp1/MDIn1 corresponds to BI_DB+/-, and in  
MDI-X configuration, MDIp1/MDIn1 corresponds to BI_DA+/-.  
100BASE-TX: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in  
MDI-X configuration, MDIp1/MDIn1 is used for the transit pair.  
10BASE-T: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in  
MDI-X configuration, MDIp1/MDIn1 is used for the transit pair.  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
15  
®
Intel 82575EB Gigabit Ethernet Controller — Serializer/Deserializer Signals  
Symbol  
MDI0_P_2  
Type  
Name and Function  
A
Media Dependent Interface [2]  
MDI0_N_2  
MDI1_P_2  
MDI1_N_2  
1000BASE-T: In MDI configuration, MDIp2/MDIn2 corresponds to BI_DC+/-, and in  
MDI-X configuration, MDIp2/MDIn2 corresponds to BI_DD+/-.  
100BASE-TX: Unused.  
10BASE-T: Unused.  
MDI0_P_3  
MDI0_N_3  
MDI1_P_3  
MDI1_N_3  
A
Media Dependent Interface [3]  
1000BASE-T: In MDI configuration, MDIp3/MDIn3 corresponds to BI_DD+/-, and in  
MDI-X configuration, MDIp3/MDIn3 corresponds to BI_DC+/-.  
100BASE-TX: Unused.  
10BASE-T: Unused.  
3.11  
Serializer/Deserializer Signals  
Symbol  
Type  
Name and Function  
SRDSI_0_P  
SRDSI_0_N  
SRDSI_1_P  
SRDSI_1_N  
SRDSO_0_P  
SRDSO_0_N  
SRDSO_1_P  
SRDSO_1_N  
AI  
SERDES Receive Pairs A and B  
These signals make the differential receive pair for the 1.25 GHz serial interface. For  
serializer/deserializer operation, the inputs should be coupled to ECL voltage levels. If the  
SERDES interface is not used, these pins should not be connected.  
AO  
SERDES Transmit Pairs A and B  
These signals make the differential transmit pair for the 1.25 GHz serial interface. For  
serializer/deserializer operation, the outputs drive the LVPECL voltage levels. If the SERDES  
interface is not used, these pins should not be connected.  
SRDS0_SIG_DET/  
SRDS1_SIG_DET  
I
Signal Detects A and B  
These pins indicate whether the SERDES signals (connected to the 1.25 GHz serial interface)  
have been detected by the optical transceivers. If the SERDES interface is not used with  
copper media, these can be left with no connection (NC). If the SERDES interface is not used  
with fiber media, the SIG_DET inputs should be tied high to VCC.  
SER_RCOMP  
A
SERDES Impedance Compensation. Connect the recommended resistor (1.4K from this  
ball to ground.  
SFP0_I2C_CLK  
SFP0_I2C_DATA  
O
Port 0 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be used as MDC pin.  
Port 0 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be used as MDIO pin  
TS/  
OD  
SFP1_I2C_CLK  
SFP1_I2C_DATA  
O
Port 1 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be used as MDC pin.  
Port 1 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be used as MDIO pin  
TS/  
OD  
3.12  
Test Interface Signals  
Note:  
Pull-up resistors are needed on these signals as shown in the reference schematic.  
Symbol  
Type  
Name and Function  
JTCK  
JTDI  
I
JTAG Test Access Port Clock  
JTAG Test Access Port Test Data In  
I
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
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January 2011  
Datasheet  
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®
Power Supply Connections — Intel 82575EB Gigabit Ethernet Controller  
Symbol  
Type  
Name and Function  
JTAG Test Access Port Test Data Out  
JTAG Test Access Port Mode Select  
JTDO  
JTMS  
OD  
I
3.13  
Power Supply Connections  
3.13.1 Digital and Analog Supplies  
Symbol  
VCC3P3  
Type  
Name and Function  
P
3.3 V Digital Power Supply.  
For I/O circuits.  
VCC1P8  
VCC1P0  
P
P
1.8 V Analog Power Supply  
For PHY analog, PHY I/O, PCI Express analog, and Phase Lock Loop circuits, Connect all 1.8 V pins to  
a single power supply.  
1.0 V Digital Power Supply  
For core digital, PHY digital, PCI Express digital and clock circuits, connect all 1.0 V pins to a single  
power supply.  
3.13.2 Grounds, Reserved Pins and No Connects  
Symbol  
VSS  
Type  
Name and Function  
P
Ground.  
RSVD_VCC  
RSVD_GND  
RSVD_ NC  
NC  
Reserved, VCC  
These pins are reserved by Intel and may have factory test functions. For normal operation, connect  
them directly to VCC. Do not connect them to pull-up resistors.  
P
P
P
Reserved, Ground  
These pins are reserved by Intel and may have factory test functions. For normal operation, connect  
them directly to ground. Do not connect them to pull-down resistors.  
Reserved, No Connect  
These pins are reserved by Intel and may have factory test functions. For normal operation, do not  
connect any circuitry to these pins. Do not connect pull-up or pull-down resistors.  
No Connect  
This pin is not connected internally.  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
17  
®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
4.0 Pinout/Signal Name  
The pinout table follows.  
Name  
Pin  
PE_CLK_P  
PE_CLK_N  
N2  
N1  
PET_0_P  
PET_0_N  
PET_1_P  
PET_1_N  
PET_2_P  
PET_2_N  
PET_3_P  
PET_3_N  
D2  
D1  
H2  
H1  
R2  
R1  
W2  
W1  
PER_0_P  
PER_0_N  
PER_1_P  
PER_1_N  
PER_2_P  
PER_2_N  
PER_3_P  
PER_3_N  
F2  
F1  
K2  
K1  
U2  
U1  
AA2  
AA1  
PE_WAKE_N  
PE_RST_N  
PE_RCOMP  
AC20  
AC9  
L1  
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Intel 82575EB Gigabit Ethernet Controller  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
RSVDM3_NC  
RSVDM2_NC  
M3  
M2  
FLSH_SI  
FLSH_SO  
AC14  
AD14  
AD15  
AC15  
FLSH_SCK  
FLSH_CE_N  
EE_DI  
EE_DO  
A21  
A20  
B20  
B21  
EE_SK  
EE_CS_N  
SMBD  
SMBCLK  
AD21  
AC21  
AD20  
SMBALRT_N  
FLBMD  
FLBMCK  
AD17  
AC17  
AC16  
AD16  
FLBSD  
FLBSINTCKEX  
NCSI_CLK_IN  
B5  
B4  
NCSI_CLK_OUT  
NCSI_CRS_DV  
NCSI_RXD_1  
NCSI_RXD_0  
A4  
A6  
B7  
®
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Intel 82575EB Gigabit Ethernet Controller  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
NCSI_TX_EN  
NCSI_TXD_1  
NCSI_TXD_0  
B6  
A7  
B8  
SDP0_0  
SDP0_1  
SDP0_2  
SDP0_3  
A16  
B16  
B17  
B15  
SDP1_0  
SDP1_1  
SDP1_2  
SDP1_3  
AD10  
A12  
A13  
AC10  
RSVDAB19_NC  
RSVDAB18_NC  
AB19  
AB18  
RSVDAD9_3P3  
MAIN_PWR_OK  
DEV_OFF_N  
AD9  
AD4  
B9  
RSVDL14_1P0  
RSVDP14_1P0  
L14  
P14  
XTAL1  
XTAL2  
N23  
N24  
SRDSI_0_P  
SRDSI_0_N  
SRDSO_0_P  
SRDSO_0_N  
J23  
J24  
K23  
K24  
®
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
SRDS0_SIG_DET  
A9  
SRDSI_1_P  
SRDSI_1_N  
SRDSO_1_P  
SRDSO_1_N  
T23  
T24  
R23  
R24  
SRDS1_SIG_DET  
SER_RCOMP  
A10  
L22  
RSVDM23_NC  
RSVDM24_NC  
M23  
M24  
SFP0_I2C_CLK/MDC0  
AD19  
AD18  
SFP0_I2C_DATA/MDIO0  
SFP1_I2C_CLK/MDC1  
AC19  
AC18  
SFP1_I2C_DATA/MDIO1  
LED0_0  
LED0_1  
LED0_2  
LED0_3  
A19  
B19  
B18  
A18  
LED1_0  
LED1_1  
LED1_2  
LED1_3  
AD13  
AC11  
AC13  
AC12  
MDI0_P_0  
MDI0_N_0  
MDI0_P_1  
MDI0_N_1  
MDI0_P_2  
C24  
C23  
D24  
D23  
F24  
®
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Intel 82575EB Gigabit Ethernet Controller  
Revision: 2.11  
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Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
MDI0_N_2  
MDI0_P_3  
MDI0_N_3  
F23  
G24  
G23  
RBIAS0_P  
VSS  
E22  
F22  
IEEE_TEST0_P  
IEEE_TEST0_N  
A22  
B22  
MDI1_P_0  
MDI1_N_0  
MDI1_P_1  
MDI1_N_1  
MDI1_P_2  
MDI1_N_2  
MDI1_P_3  
MDI1_N_3  
AB24  
AB23  
AA24  
AA23  
W24  
W23  
V24  
V23  
RBIAS1_P  
Y22  
IEEE_TEST1_P  
IEEE_TEST1_N  
AD22  
AC22  
RSVDAD8_VSS  
AD8  
JTCK  
JTDI  
AC6  
AD7  
AC8  
AC7  
AC5  
JTDO  
JTMS  
RSVDAC5_3P3  
AUX_PWR  
LAN1_DIS_N  
RSVDB12_3P3  
B14  
A15  
B12  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
LAN0_DIS_N  
RSVDA8_3P3  
RSVDA11_3P3  
RSVDB10_3P3  
RSVDB11_3P3  
RSVDA14_VSS  
B13  
A8  
A11  
B10  
B11  
A14  
NCB3  
NCAC3  
NCAD3  
B3  
AC3  
AD3  
VCC3P3  
VCC3P3  
VCC3P3  
VCC3P3  
AD6  
AD12  
A5  
A17  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
P5  
P4  
N9  
N8  
N5  
N4  
M9  
M8  
M5  
M4  
L9  
L8  
L5  
L4  
L15  
K15  
J15  
H15  
G15  
®
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Intel 82575EB Gigabit Ethernet Controller  
Revision: 2.11  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
E20  
E19  
D20  
D19  
Y20  
Y19  
V15  
U15  
T15  
R15  
P15  
AA20  
AA19  
N21  
N15  
M21  
M15  
P9  
P8  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
R14  
R13  
R12  
R11  
P13  
P12  
L13  
L12  
K14  
K13  
K12  
K11  
V5  
V4  
U5  
®
Intel 82575EB Gigabit Ethernet Controller  
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Datasheet  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
U4  
P11  
N11  
M11  
L11  
H5  
H4  
G5  
G4  
J21  
J20  
J18  
J17  
L21  
L20  
L18  
L17  
K21  
K20  
K18  
K17  
T21  
T20  
T18  
T17  
P21  
P20  
P18  
P17  
R21  
R20  
R18  
R17  
VSS  
Y9  
®
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
Y8  
Y7  
Y6  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
W9  
W8  
W7  
W22  
W14  
W13  
W12  
W11  
W10  
V9  
V8  
V14  
V13  
V12  
V11  
V10  
U9  
U14  
U13  
U12  
U11  
U10  
T14  
T13  
T12  
T11  
®
Intel 82575EB Gigabit Ethernet Controller  
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Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
N14  
N13  
N12  
M14  
M13  
M12  
J14  
J13  
J12  
J11  
H9  
H14  
H13  
H12  
H11  
H10  
G9  
G8  
G14  
G13  
G12  
G11  
G10  
F9  
F8  
F7  
F14  
F13  
F12  
F11  
F10  
E9  
E8  
E7  
E6  
®
317679-004  
Revision: 2.11  
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
27  
®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
E15  
E14  
E13  
E12  
E11  
E10  
D9  
D8  
D7  
D6  
D5  
D16  
D15  
D14  
D13  
D12  
D11  
D10  
C9  
C8  
C7  
C6  
C5  
C4  
C17  
C16  
C15  
C14  
C13  
C12  
C11  
C10  
B2  
B1  
AD5  
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Intel 82575EB Gigabit Ethernet Controller  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
AD2  
AD11  
AD1  
AC4  
AC2  
AC1  
AB9  
AB8  
AB7  
AB6  
AB5  
AB4  
AB17  
AB16  
AB15  
AB14  
AB13  
AB12  
AB11  
AB10  
AA9  
AA8  
AA7  
AA6  
AA5  
AA16  
AA15  
AA14  
AA13  
AA12  
AA11  
AA10  
A3  
A2  
A1  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
Y24  
Y23  
Y21  
Y18  
Y17  
Y16  
W21  
W20  
W19  
W18  
W17  
W16  
W15  
V22  
V21  
V20  
V19  
V18  
V17  
V16  
U24  
U23  
U22  
U21  
U20  
U19  
U18  
U17  
U16  
T22  
T19  
T16  
R22  
R19  
R16  
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Intel 82575EB Gigabit Ethernet Controller  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
P24  
P23  
P22  
P19  
P16  
N22  
N20  
N19  
N18  
N17  
N16  
M22  
M20  
M19  
M18  
M17  
M16  
L24  
L23  
L19  
L16  
K22  
K19  
K16  
J22  
J19  
J16  
H24  
H23  
H22  
H21  
H20  
H19  
H18  
H17  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
H16  
G22  
G21  
G20  
G19  
G18  
G17  
G16  
F21  
F20  
F19  
F18  
F17  
F16  
F15  
E24  
E23  
E21  
E18  
E17  
E16  
D22  
D21  
D18  
D17  
C22  
C21  
C20  
C19  
C18  
B24  
B23  
AD24  
AD23  
AC24  
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Intel 82575EB Gigabit Ethernet Controller  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
AC23  
AB22  
AB21  
AB20  
AA22  
AA21  
AA18  
AA17  
A24  
A23  
Y5  
Y4  
Y3  
Y2  
Y1  
W6  
W5  
W4  
W3  
V7  
V6  
V3  
V2  
V1  
U8  
U7  
U6  
U3  
T9  
T8  
T7  
T6  
T5  
T4  
T3  
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Intel 82575EB Gigabit Ethernet Controller  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
T2  
T10  
T1  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R10  
P7  
P6  
P3  
P2  
P10  
P1  
N7  
N6  
N3  
N10  
M7  
M6  
M10  
M1  
L7  
L6  
L3  
L2  
L10  
K9  
K8  
K7  
K6  
K5  
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Intel 82575EB Gigabit Ethernet Controller  
317679-004  
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®
Pinout/Signal Name — Intel 82575EB Gigabit Ethernet Controller  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
K4  
K3  
K10  
J9  
J8  
J7  
J6  
J5  
J4  
J3  
J2  
J10  
J1  
H8  
H7  
H6  
H3  
G7  
G6  
G3  
G2  
G1  
F6  
F5  
F4  
F3  
E5  
E4  
E3  
E2  
E1  
D4  
D3  
C3  
C2  
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Intel 82575EB Gigabit Ethernet Controller  
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®
Intel 82575EB Gigabit Ethernet Controller — Pinout/Signal Name  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
C1  
AB3  
AB2  
AB1  
AA4  
AA3  
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®
Power Requirements — Intel 82575EB Gigabit Ethernet Controller  
5.0 Power Requirements  
5.1  
Targeted Absolute Maximum Ratings  
Table 1.  
Absolute Maximum Ratings1  
Symbol  
Parameter  
Min  
VSS - 0.5  
Max  
Unit  
VCC(3.3)  
VCC(1.8)  
VCC(1.0)  
DC supply voltage on 3.3 V pins with  
respect to VSS  
4.6  
2.5  
1.7  
V
V
V
V
DC supply voltage on 1.8 V pins with  
VSS - 0.3  
VSS - 0.2  
2
respect to VSS  
DC supply voltage on 1.0 V pins with  
b
respect to VSS  
V / V  
3.3 V I/O Voltage  
VSS - 0.5  
VSS - 0.3  
VSS - 0.2  
N/A  
4.6  
2.5  
1.7  
TBD  
140  
I
O
1.8 V I/O Voltage  
1.0 V I/O Voltage  
I
DC output current  
Storage temperature range  
mA  
O
T
-65  
storage  
°C  
°C  
V
T
Case temperature under bias  
0
85  
case  
ESD per MIL_STD-883 Test Method  
3015, Specification 2001V Latchup  
Over/Undershoot: 150 mA, 125° C  
N/A  
VDD overstress:  
VDD(3.3) * (7.2 V)  
1. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are  
exceeded for an indefinite duration. These values should not be used as the limits for normal device operations.  
2. During normal device power up and power down, the 1.8 V and 1.0 V supplies must not ramp before the 3.3 V supply.  
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®
Intel 82575EB Gigabit Ethernet Controller — Targeted Recommended Operating Conditions  
5.2  
Targeted Recommended Operating  
Conditions  
5.2.1  
General Operating Conditions  
Table 2.  
Recommended Operating Conditions 1  
Symbol  
Parameter  
Min  
Max  
Unit  
VCC(3.3)  
VCC(1.8)  
VCC(1.0)  
tR / tF  
DC supply voltage on 3.3 V pins  
DC supply voltage on 1.8 V pins  
DC supply voltage on 1.0 V pins  
Input rise/fall time (normal input)  
Operating temperature range (ambient)  
Junction temperature  
3.0  
1.71  
0.95  
0
3.6  
1.89  
1.05  
200  
55  
V
V
V
ns  
°C  
°C  
T
0
a
T
N/A  
110  
J
1. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits,  
might result in permanent damage. Device functionality to stated DC and AC limits is not guaranteed, if conditions exceed  
recommended operating conditions.  
5.2.2  
Voltage Ramp and Sequencing Recommendations  
The following tables give the specifications for the power supply ramps:  
Table 3.  
3.3 V Supply Voltage Ramp  
Parameter  
Description  
Min  
Max  
Unit  
1
Rise Time  
Monotonicity  
Slope  
Time from 10% to 90% mark  
0.1  
N/A  
24  
3
100  
ms  
mV  
Voltage dip allowed in ramp  
0
Ramp rate at any time between 10% to 90%  
28800  
3.6  
mV/ms  
V
Operational  
Range  
Voltage range for normal operating  
conditions  
Ripple  
Maximum voltage ripple at a bandwidth  
equal to 50 MHz  
N/A  
70  
mV  
peak-peak  
2
Ripple  
Overshoot time upon ramp  
N/A  
N/A  
0.05  
100  
ms  
b
Overshoot  
Maximum voltage allowed  
mV  
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.  
2. Excessive overshoot can affect long term reliability.  
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Voltage Ramp and Sequencing Recommendations — Intel 82575EB Gigabit Ethernet Controller  
Table 4.  
1.8 V Supply Voltage Ramp  
Parameter  
Description  
Min  
Max  
Unit  
1
Rise Time  
Monotonicity  
Slope  
Time from 10% to 90% mark  
0.1  
N/A  
14  
100  
ms  
mV  
Voltage dip allowed in ramp  
0
Ramp rate at any time between 10% to 90%  
60000  
1.89  
mV/ms  
V
Operational  
Range  
Voltage range for normal operating  
conditions  
1.71  
Ripple  
Maximum voltage ripple at a bandwidth  
equal to 1 MHz  
N/A  
N/A  
N/A  
40  
0.1  
100  
mV  
peak-peak  
ms  
2
Overshoot  
SettlingTime  
Overshoot time upon ramp  
b
Overshoot  
Maximum voltage allowed  
mV  
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.  
2. Excessive overshoot can affect long term reliability.  
Table 5.  
1.0 V Supply Voltage Ramp  
Parameter  
Description  
Min  
Max  
Unit  
1
Rise Time  
Monotonicity  
Slope  
Time from 10% to 90% mark  
Voltage dip allowed in ramp  
0.1  
N/A  
7.6  
100  
ms  
mV  
0
Ramp rate at any time between 10% to  
90%  
33600  
mV/ms  
Operational  
Range  
Voltage range for normal operating  
conditions  
0.95  
1.05  
V
Ripple  
Maximum voltage ripple at a bandwidth  
equal to 1 MHz  
N/A  
N/A  
N/A  
40  
mV  
peak-peak  
ms  
2
Overshoot  
SettlingTime  
Overshoot time upon ramp  
0.05  
100  
b
Overshoot  
Maximum voltage allowed  
mV  
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.  
2. Excessive overshoot can affect long term reliability.  
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®
Intel 82575EB Gigabit Ethernet Controller — Thermal Information  
Table 6.  
Power Supply Sequencing  
Symbol  
Parameter  
Min  
Max  
Unit  
T
T
T
T
VCC3p3 (3.3 V) stable to VCC1p8 stable  
VCC1p8 stable to VCC (1.0 V) stable  
0
0
100  
ms  
ms  
mV  
ms  
3 18  
18 1  
3 1  
VCC3p3 (3.3 V) stable to VCC (1.0 V) stable  
0
100  
, T  
3.3 V core to GIO_PWR_GOOD and MAIN_PWR_OK  
on  
TBD  
m-per m-ppo  
T
, T  
GIO_PWR_GOOD, MAIN_PWR_OK off before 3.3 V  
core down  
0
ms  
per-m  
ppo-m  
Aux power stable  
VCCP (3.3V)  
VCC1p8 (1.8V)  
T3_18  
T18_1  
VCC/VCC1p0(1V)  
Tlpgw  
Power-on Reset  
(internal)  
T3_1  
Tlpg  
Main Power stable  
Main power stable  
GIO_PWR_GOOD  
MAIN_PWR_OK  
Tm-per  
Tm-ppo  
Tper-m  
Tppo-m  
Tlpg-per  
Figure 2.  
Voltage Power Sequencing Options  
To meet the 375 mA inrush current requirements (not including external capacitors) the ramp time  
should be 5 ms -100 ms on all power rails. For faster ramps (100 us - 5 ms), expect higher inrush  
current due to the high charging current of the decoupling capacitors of 3.3 V, 1.8 V and 1.0 V rails.  
5.3  
Thermal Information  
The 82575EB device is specified for operation when the ambient temperature (TA) is within the range of  
0 °C to 55 °C. For information about the thermal characteristics of the device, including operation  
outside this range, please refer to the 82575EB Thermal Application Note.  
®
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®
Electrical Specification — Intel 82575EB Gigabit Ethernet Controller  
6.0 Electrical Specification  
6.1  
DC Specifications  
Table 7.  
DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Units  
VCC(3.3)  
DC supply voltage on 3.3 V  
pins  
3.00  
3.30  
3.60  
V
VCC(1.8)  
VCC(1.0)  
DC supply voltage on 1.8 V  
pins  
1.71  
1.80  
1.89  
V
V
DC supply voltage on 1.0 V  
pins  
0.95  
1.00  
1.08  
Table 8.  
I/O Characteristics  
1
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Units  
V
V
Input high voltage  
2.0  
N/A  
VCC(3.3)  
+ 0.5  
V
IH  
Input low voltage  
Input current  
-0.5  
-15  
2.4  
N/A  
N/A  
N/A  
0.8  
15  
V
A  
V
IL  
I
V
= VDD(3.3) or V  
= -16 mA  
= Min  
IN  
IN  
SS  
V
Output high voltage  
I
N/A  
OH  
OH  
V
CC  
I
= -100 A  
= Min  
V
- 0.02  
N/A  
N/A  
N/A  
N/A  
N/A  
0.4  
0.2  
10  
OH  
CC  
V
CC  
V
Output low voltage  
I
= 14 mA  
= Min  
N/A  
N/A  
-10  
V
OL  
OL  
V
CC  
I
= 100 A  
= Min  
OL  
V
V
CC  
I
Off-state output leakage  
current  
= V or V  
SS  
A  
OZ  
O
CC  
2
C
Input capacitance  
Internal pull-up  
Overshoot  
N/A  
2.6  
2.5  
N/A  
N/A  
N/A  
N/A  
5.5  
pF  
k  
V
IN  
PU  
V
V
N/A  
N/A  
4.0  
OS  
US  
Undershoot  
-0.4  
V
1. The input buffer also has hysteresis > 160 mV.  
2. C = 2.5 pF(maximum input capacitance), C  
in  
= 16 pF (characterized max output load capacitance per 160 MHz).  
out  
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®
Intel 82575EB Gigabit Ethernet Controller — DC Specifications  
Table 9.  
Open Drain I/O  
Symbol  
Parameter  
Condition  
Min  
Max  
Units  
Note  
VCC3P3  
VCC  
Periphery supply  
Core supply  
3.0  
0.9  
2.1  
3.6  
V
V
1.32  
Vih  
Input High Voltage  
Input Low Voltage  
V
Vil  
0.8  
V
Ileakage  
Output Leakage  
Current  
0 < Vin < VCC3P3  
+/-10  
ìA  
2
4
Vol  
Ipullup  
Cin  
Output Low Voltage  
Current sinking  
@ Ipullup  
Vol=0.4V  
0.4  
V
mA  
pF  
pF  
ìA  
4
Input Pin Capacitance  
Output Pin Capacitance  
Input leakage current  
7
3
3
2
Cout  
30  
Ioffsmb  
VCC3P3 off or floating  
+/-10  
Notes:  
1. Applies to SMBD0, SMBCLK0, , SMBALRT _N, PE_WAKE_n, SFP1_I2C_Data, SFP0_I2C_Data pads.  
2. Device meets this whether powered or not.  
3. Characterized, not tested.  
4. OD no high output drive. VOL max=0.4V at 14mA, VOL max=0.2V at 0.1mA  
®
Intel 82575EB Gigabit Ethernet Controller  
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®
DC Specifications — Intel 82575EB Gigabit Ethernet Controller  
Table 10.  
Power Consumption  
D0a--Active Link  
@ 1000 Mbps  
(copper)  
@ 1000 Mbps  
(SERDES)  
@10 Mbps  
@100 Mbps  
1
1
1
1
1
2
Typ Icc (mA)  
Typ Icc (mA)  
Typ Icc (mA)  
Max Icc (mA)  
Typ Icc (mA)  
Max Icc (mA)  
18  
18  
18  
841  
23  
19  
142  
19  
3.3 V  
1.8 V  
1.0 V  
344  
304  
312  
388  
856  
1184  
203  
492  
856  
354  
0.98 W  
1.01 W  
2.43 W  
2.80 W  
0.67 W  
0.92 W  
Total Device  
Power  
1. Typical conditions: operating temperature (T ) = 25 C, nominal voltages and moderate network traffic at full duplex.  
A
2. Maximum conditions: maximum operating temperature (T ) values, typical voltage values and continuous network traffic at full  
J
duplex.  
D0a--Idle Link  
Unplugged--no link  
LOs only  
1
Typ Icc (mA)  
18  
3.3 V  
1.8 V  
129  
264  
0.56  
1.0 V  
2
Total Device Power  
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex  
2. Known errata on LOs & L1 states might impact devide power consumption  
D0a--Idle Link  
@10Mbps  
LOs only  
Typ Icc (mA)  
1
18  
140  
3.3 V  
1.8 V  
302  
1.0 V  
2
0.61 W  
Total Device Power  
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex  
2. Known errata on LOs & L1 states might impact devide power consumption  
®
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®
Intel 82575EB Gigabit Ethernet Controller — DC Specifications  
D0a--Idle Link  
@100Mbps (Copper)  
LOs only  
1
Typ Icc (mA)  
18  
837  
3.3 V  
1.8 V  
755  
1.0 V  
2
2.32 W  
Total Device Power  
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex  
2. Known errata on LOs & L1 states might impact devide power consumption  
D0a--Idle Link  
@1000Mbps (SERDES)  
1
Typ Icc (mA)  
17  
142  
3.3 V  
1.8 V  
341  
1.0 V  
2
0.65 W  
Total Device Power  
1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex  
2. Known errata on LOs & L1 states might impact devide power consumption  
D3cold - wake-up enabled  
D3cold-wake disabled  
@10 Mbps  
@100 Mbps  
Typ Icc (mA)  
18  
Typ Icc (mA)  
18  
Typ Icc (mA)  
18  
3.3 V  
1.8 V  
98  
168  
269  
249  
83  
70  
1.0 V  
0.40 W  
0.79 W  
0.29 W  
Total Device Power  
D(r) Uninitialized  
Disabled through DEV_OFF_N  
Typ Icc (mA)  
11  
3.3 V  
1.8 V  
1.0 V  
179  
283  
0.64  
Total Device Power  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
44  
®
Resets — Intel 82575EB Gigabit Ethernet Controller  
6.2  
Resets  
Power-on Reset (internal): The 82575EB has an internal mechanism for sensing the power pins.  
Once the power is up and stable, it creates an internal reset, this reset acts as a master reset of the  
entire chip. It is level sensitive, and while it is 0, will hold all of the registers in reset. Power-on Reset  
is interpreted to be an indication that device power supplies are all stable. Power-on Reset changes  
state during system power-up.  
In-band PCIe Reset: The 82575EB will generate an internal reset in response to a physical layer  
message from the PCIe or when the PCIe link halts (entry to Polling or Detect state). This reset is  
equivalent to PCI reset in previous (PCI) gigabit LAN controllers.  
Main_Power_Good: Used by the device to detect the D3Cold condition and activate part of the power  
saving scheme.  
®
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — Pull-up and Pull-down Specifications and Signals  
6.3  
Pull-up and Pull-down Specifications and  
Signals  
Table 11.  
Internal and External Pull-up and Pull-down Values  
Min  
Nominal  
5K  
Max  
Units  
PU (Internal)  
2.7K  
8.6K  
PU (External, recommended)  
PD (External, reccommended)  
<3K  
<400  
For external Pull-up requirements, see the 82575EB reference schematics.  
The table below lists internal & external pull-up resistors and whether they are activated in the different  
device states. Each internal PUP has a nominal value of 5k, ranging from 2.7Kto 8.6K.  
The device states are defined as follow:  
• Power-up = while 3.3 V is stable, but not 1.0 V  
• Active = normal mode (not power up nor disable)  
• Disable = device disabled  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
46  
®
Pull-up and Pull-down Specifications and Signals — Intel 82575EB Gigabit Ethernet Controller  
Table 12.  
Internal Pull-up and External Pull Up Requirements  
External  
Recomended?  
Signal Name  
Power up  
Active  
Disable  
Notes  
PE_WAKE_N  
PE_RST_N  
FLSH_SI  
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
N
N
N
N
Y
N
N
Y
Y
N
N
N
N
Y
FLSH_SO  
Y
FLSH_SCK  
FLSH_CE_N  
EE_DI  
N
N
N
Y
Y
Y
Y
N
N
N
Y
EE_DO  
Y
EE_SK  
N
N
N
N
N
N
N
N
Y
EE_CS_N  
Y
SMBD  
N
N
N
N
N
N
Y
SMBCLK  
Y
SMBALRT_N  
NCSI_CLK_IN  
NCSI_CLK_OUT  
NCSI_CRS_DV  
Y
N
N
Y
Pull down only if NCSI is NOT  
being used or configured for multi  
drop  
NCSI_RXD[1:0]  
NCSI_TX_EN  
N
N
N
N
N
N
N
N
N
Y
N
N
Pull Up only if NCSI is NOT being  
used or configured for multi drop  
Should be connected to external  
PD if NCSI is NOT used  
NCSI_TXD[1:0]  
Should be connected to external  
PD if NCSI is NOT used  
SDP0[3:0]  
SDP1[3:0]  
DEV_OFF_N  
Y
Y
Y
Y
Y
N
N
N
N
N
N
Mustbe connected  
on board  
MAIN_PWR_OK  
SRDS_0_SIG_DET  
SRDS_1_SIG_DET  
Y
Y
Y
N
N
N
N
N
N
Mustbe connected  
on board  
Mustbe connected  
externally  
Mustbe connected  
externally  
SFP0_I2C_CLK  
SFP0_I2C_DATA  
SFP1_I2C_CLK  
Y
Y
Y
N
N
N
Y
N
Y
Y if active  
Y
If used.  
If used.  
If used.  
Y if active  
®
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Intel 82575EB Gigabit Ethernet Controller  
Revision: 2.11  
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Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — Pull-up and Pull-down Specifications and Signals  
SFP1_I2C_DATA  
LED0_0  
LED0_1  
LED0_2  
LED0_3  
LED1_0  
LED1_1  
LED1_2  
LED1_3  
JTCK  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
If used.  
N
JTDI  
Y
JTDO  
Y
Y
JTMS  
AUX_PWR  
LAN1_DIS_N  
LAN0_DIS_N  
Y (or PD)  
Y
Y
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
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®
Targeted AC Characteristics — Intel 82575EB Gigabit Ethernet Controller  
6.4  
Targeted AC Characteristics  
Table 13.  
25 MHz Clock Input Requirements  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
f0  
Frequency  
N/A  
-50  
40  
25.000  
N/A  
N/A  
N/A  
N/A  
N/A  
20  
N/A  
+50  
60  
MHz  
ppm  
%
df0  
Dc  
tr  
Frequency Variation  
Duty Cycle  
Rise Time  
N/A  
N/A  
N/A  
N/A  
N/A  
1.0  
N/A  
5
ns  
tf  
Fall Time  
5
ns  
1
Jptp  
Clock Jitter (peak-to-peak)  
Input Capacitance  
Operating Temperature  
250  
N/A  
70  
ps  
C
pF  
°C  
V
in  
T
N/A  
1.2  
Aptp  
Vcm  
Input clock amplitude (peak-to-peak)  
Clock common mode  
1.3  
N/A  
0.6  
V
5
1. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000Base-T Standard (at least 10 clock edges,  
filtered by HPF with cut off frequency of 5000 Hz).  
Table 14.  
Link Interface Clock Requirements  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
1
fGTX  
GTX_CLK frequency  
N/A  
125  
N/A  
MHz  
1. GTX_CLK is used externally for test purposes only. See signals IEEE_TEST1_p and IEEE_TEST1_n.  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — EEPROM Interface  
6.4.1  
EEPROM Interface  
Applicable over recommended operating range from Ta = -40C to +85C, VCC3P3 = 3.3 V, Cload = 1 TTL  
Gate and 16pF (unless otherwise noted).  
Symbol  
t
Parameter  
Min  
Typ  
Max  
Units  
Note  
SCK clock frequency  
Input rise time  
Input fall time  
SCK high time  
SCK low time  
0
2
2.1  
2
MHz  
us  
us  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
[1]  
SCK  
t
2.5ns  
2.5ns  
250  
RI  
t
2
FI  
t
200  
200  
250  
250  
250  
50  
[2]  
WH  
t
250  
WL  
t
CS high time  
CS  
t
CS setup time  
CSS  
CSH  
t
CS hold time  
t
Data-in setup time  
Data-in hold time  
Output valid  
SU  
t
50  
H
t
0
200  
250  
V
t
Output hold time  
Output disable time  
0
HO  
t
DIS  
Notes:  
1. 1. Clock is 2MHz  
2. 2.50% duty cycle  
tCS  
VIH  
CS  
VIL  
tCSS  
tCSH  
VIH  
SCK  
tWL  
tWH  
VIL  
tSU  
tH  
VIH  
SI  
VALID IN  
VIL  
tV  
tHO  
tDIO  
VIH  
SO  
Hi-Z  
Hi-Z  
VIL  
Figure 3.  
EEPROM Interface Time Diagram  
®
Intel 82575EB Gigabit Ethernet Controller  
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®
FLASH Interface — Intel 82575EB Gigabit Ethernet Controller  
6.4.2  
FLASH Interface  
Applicable over recommended operating range from Ta = -40C to +85C, VCC3P3 = 3.3 V, Cload = 1 TTL  
Gate and 16 pF (unless otherwise noted)  
Table 15.  
FLASH Parameters  
Symbol  
t
Parameter  
Min  
Typ  
Max  
Units  
Note  
SCK clock frequency  
Input rise time  
Input fall time  
SCK high time  
SCK low time  
0
15.625  
2.5  
20  
20  
20  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
[1]  
SCK  
t
RI  
t
2.5  
FI  
t
20  
20  
25  
25  
25  
5
32  
[2]  
[2]  
WH  
t
32  
WL  
t
CS high time  
CS  
t
CS setup time  
CSS  
CSH  
t
CS hold time  
t
Data-in setup time  
Data-in hold time  
Output valid  
SU  
t
5
H
t
20  
V
t
Output hold time  
Output disable time  
0
HO  
t
100  
DIS  
tCS  
VIH  
CS  
VIL  
tCSH  
tcss  
VIH  
tWH  
tWL  
Sck  
SI  
VIL  
tSU  
tH  
VIH  
VALID IN  
VIL  
tHO  
tDIS  
tv  
VOH  
HI-Z  
HI-Z  
SO  
VOL  
Figure 4.  
FLASH Timing Diagram  
®
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Revision: 2.11  
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — NC-SI Interface  
6.4.3  
NC-SI Interface  
Table 16.  
NC-SI AC Specification  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Notes  
REF_CLK Frequency  
REF_CLK Duty Cycle  
REF_CLK accuracy  
50  
MHz  
%
2
1
35  
65  
100  
ppm  
ns  
Tsu  
Thold  
Tval  
TXD[1:0], TX_EN, Data Setup to REF_CLK rising  
edge  
3
TXD[1:0], TX_EN Data hold from REF_CLK rising  
edge  
1.5  
1.8  
ns  
ns  
6
RXD[1:0], CRS_DV Data valid from REF_CLK  
rising edge  
9
Tor  
Tof  
RXD[1:0], CRS_DV Output Time rise  
RXD[1:0], CRS_DV Output Time fall  
RXD[1:0], CRS_DV Output delay rise  
RXD[1:0], CRS_DV Output delay fall  
TXD[1:0], TX_EN Input delay rise  
TXD[1:0], TX_EN Input delay fall  
TXD[1:0], TX_EN Input Time rise  
TXD[1:0], TX_EN Input Time fall  
0.5  
0.5  
2
6
6
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3
3
Todr1  
Todf1  
Tidr2  
Tidf2  
Tir  
5.8  
5.8  
6
3
2
3
0.5  
0.5  
0.02  
0.02  
4, 5  
4, 5  
4, 5  
4, 5  
6
0.15  
0.15  
Tif  
Notes:  
1. Clock Duty cycle measurement: High interval measured from Vih to Vil points, Low from Vil to next Vih  
2. Clock interval measurement from Vih to Vih  
3. Cload = 25 pF  
4. Cload = 200 fF  
5. The input delay test conditions: Maximum input level = VIN = 2.7V; Input rise/fall time (0.2VIN to 0.8VIN) = 1ns (Slew Rate ~  
1.5ns).  
6. The NC-SI specification defines a hold time of 1.0 ns. In order to work with the 82575, the board designer should guarantee a hold  
time of 1.5 ns.  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
52  
®
SMBus Interface — Intel 82575EB Gigabit Ethernet Controller  
6.4.4  
SMBus Interface  
Table 17.  
SMBus AC Characteristics (master mode)  
Symbol  
Parameter  
Min  
Typ  
74.4  
6.56  
Max  
100  
Units  
kHz  
µs  
F
SMBus Frequency  
SMB  
T
Time between STOP and START condition driven  
by the device  
BUF  
T
Hold time after Start Condition. After this period,  
the first clock is generated.  
6.72  
µs  
HD:STA  
T
Start Condition setup time  
Stop Condition setup time  
Data hold time  
µs  
µs  
µs  
ms  
µs  
µs  
SU:STA  
SU:STO  
HD:DAT  
T
T
6.88  
0.48  
T
Detect SMBClk low timeout  
SMBClk low time  
26.2  
31.5  
TIMEOUT  
T
5.76  
6.56  
LOW  
T
SMBClk high time  
HIGH  
Table 18.  
SMBus AC Characteristics (slave mode)  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
F
SMBus Frequency  
74.4  
6.56  
100  
kHz  
µs  
SMB  
T
Time between STOP and START condition driven  
by the device  
BUF  
T
Hold time after Start Condition. After this period,  
the first clock is generated.  
6.72  
µs  
HD:STA  
T
Start Condition setup time  
Stop Condition setup time  
Data hold time  
TBD  
6.88  
0.48  
µs  
µs  
µs  
ms  
µs  
µs  
SU:STA  
SU:STO  
HD:DAT  
T
T
T
Detect SMBClk low timeout  
SMBClk low time  
26.2  
31.5  
TIMEOUT  
T
5.76  
6.56  
LOW  
T
SMBClk high time  
HIGH  
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
53  
®
Intel 82575EB Gigabit Ethernet Controller — SMBus Interface  
Table 19.  
AC Test Loads for General Output Pins  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
C
Capacitance of test load  
N/A  
16  
N/A  
pF  
L
CL  
Figure 5.  
AC Test Loads for General Output Pins  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
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®
Crystal Requirements — Intel 82575EB Gigabit Ethernet Controller  
7.0 Crystal Requirements  
Table 20.  
Reference Crystal Specification Requirements  
Parameter Name  
Symbol  
Recommended Value  
Conditions  
Frequency  
Vibration mode  
f
25.000 [MHz]  
Fundamental  
AT  
@25 [°C]  
o
Cut  
Operating /Calibration Mode  
Frequency Tolerance @25°C  
Temperature Tolerance  
Operating Temperature  
Parallel  
f/f @25°C  
±30 [ppm]  
@25 [°C]  
o
f/f  
±30 [ppm]  
o
T
-20 to +70 [°C]  
-40 to +90 [°C]  
50 [Ù] maximum  
20 [pF] (max 24pF)  
6 [pF] maximum  
15 [ppm/pF] maximum  
0.5 [mW]  
opr  
Non Operating Temperature Range  
Equivalent Series Resistance (ESR)  
Load Capacitance  
T
opr  
R
@25 [MHz]  
s
C
load  
Shunt Capacitance  
C
o
Pullability from Nominal Load Capacitance  
Max Drive Level  
f/C  
load  
D
L
Insulation Resistance  
IR  
500 [M] minimum  
±5 [ppm/year[  
2 [pF]  
@ 100V DC  
Aging  
f/f  
o
*
Differential board capacitance  
C
D
Board Capacitance  
External Capacitors  
Board Resistance  
C
4 [pF]  
s
C , C  
27 [pF]  
1
2
R
0.1 []  
s
®
317679-004  
Intel 82575EB Gigabit Ethernet Controller  
Revision: 2.11  
January 2011  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — LED Configuration  
8.0 LED Configuration  
The 82575EB provides 4 LEDs per port that may be used to indicate the status of the traffic. The  
default setup of the LEDs is done via the EEPROM words 1Ch and 1Fh. The default setup for both ports  
is the same. This setup is reflected in the LEDCTL register of each port. Each driver may change its  
setup individually. For each of the LEDs the following parameters can be defined:  
1. Mode: Defines which information is reflected by this LED. The encoding is described in the LEDCTL  
register.  
2. Polarity: Defines the polarity of the LED.  
3. Blink mode: should the LED blink or be stable.  
In addition, the blink rate of all LEDs can be defined. The possible rates are 200 ms or 83 ms for each  
phase. There is one rate for all LEDs  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
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January 2011  
Datasheet  
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®
Mechanical Information — Intel 82575EB Gigabit Ethernet Controller  
9.0 Mechanical Information  
This section describes device physical characteristics.  
The targeted signal names are subject to change without notice. Verify with your local Intel sales office  
that you have the latest information before finalizing a design.  
9.1  
Targeted Package Information  
The 82575EB device is a 576-lead flip-chip ball grid array (FC-BGA) measuring 25 mm by 25 mm. The  
nominal ball pitch is 1 mm. See the data in the printouts below.  
Detail Area  
0.43 mm  
Solder Resist Opening  
0.62 mm  
Metal Diameter  
®
317679-004  
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — Targeted Package Information  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
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January 2011  
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®
Pin Map — Intel 82575EB Gigabit Ethernet Controller  
9.2  
Pin Map  
This section provides a pin map. The map is divided into two sections (TOP view).  
®
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Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
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®
Intel 82575EB Gigabit Ethernet Controller — Pin Map  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
IEEE_T  
EST1_P  
SFP0_I2C_ SFP0_I2C_  
FLBSINTCK  
X
SMBD  
SMBALRT  
_N  
FLBMD  
FLSH_SCK FLSH_SO  
FLSH_CE_N FLSH_SI  
LED1_0  
VSS  
VSS  
AD  
AC  
AB  
AA  
CLK  
Data  
IEEE_T  
EST1_N  
SFP1_I2C_ SFP1_I2C_  
SMBCLK PE_WAKE  
_N  
FLBMCK  
VSS  
FLBSD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
LED1_2  
VSS  
VSS  
VSS  
CLK  
Data  
MDI1_P_0 MDI1_N_0  
MDI1_P_1 MDI1_N_1  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC1P8  
VCC1P8  
VSS  
RSVDAB19 RSVDAB18  
_NC _NC  
VSS  
VSS  
VSS  
VSS  
VCC1P8  
VSS  
VSS  
VSS  
RBIAS1  
_P  
VSS  
VSS  
VSS  
VCC1P8  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
Y
RBIAS1  
_N  
MDI1_P_2 MDI1_N_2  
MDI1_P_3 MDI1_N_3  
VSS  
VSS  
VSS  
VSS  
VSS  
W
V
U
T
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC1P8  
VCC1P8  
VCC1P8  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SRDSI_1_ SRDSI_1_  
VSS  
VSS  
VSS  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
N
P
SRDSO_1_ SRDSO_1_  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC1P8  
VCC1P8  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
R
N
P
VSS  
VSS  
RSVDP  
_1P014  
P
VSS  
VSS  
VCC1P8  
VCC1P8  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC1P8  
VCC1P8  
VSS  
VSS  
VSS  
VSS  
XTAL2  
XTAL1  
N
RSVDM  
24_NC  
RSVDM  
23_NC  
M
SER_  
RCOMP  
VSS  
VSS  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VSS  
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
RSVDL  
14_1P0  
VSS  
VSS  
L
K
J
SRDSO_0_ SRDSO_0_  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VSS  
N
P
SRDSI_0_ SRDSI_0_  
N
P
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
H
G
F
MDI0_P_3 MDI0_N_3  
MDI0_P_2 MDI0_N_2  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
RBIAS0  
_N  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
RBIAS0  
_P  
VSS  
VSS  
VSS  
VCC1P8  
VCC1P8  
VSS  
VCC1P8  
VCC1P8  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
E
D
C
B
A
MDI0_P_1 MDI0_N_1  
MDI0_P_0 MDI0_N_0  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
IEEE_T  
EST0_N  
EE_CS_N  
EE_DI  
EE_SK  
EE_DO  
LED0_1  
LED0_0  
LED0_2  
LED0_3  
SDP0_2  
SDP0_1  
SDP0_0  
SDP0_3 AUX_PWR LAN0_DIS_N  
VSS  
VSS  
VSS  
VSS  
LAN1_  
RSVDA14  
_NC  
IEEE_T  
EST0_P  
SDP1_2  
13  
VCC3P3  
17  
DIS_N  
15  
24  
23  
22  
21  
20  
19  
18  
16  
14  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Datasheet  
60  
Revision: 2.11  
January 2011  
®
Pin Map — Intel 82575EB Gigabit Ethernet Controller  
12  
11  
10  
9
8
7
6
5
4
3
2
1
SDP1_0  
RSVDAD9 RSVDAD8  
JTDI  
MAIN_PWR NCAD3  
_OK  
VSS  
VSS  
VSS  
VSS  
VCC3P3  
VCC3P3  
AD  
AC  
AB  
AA  
_NC  
_NC  
RSVDAC5  
_3P3  
LED1_3  
VSS  
LED1_1  
VSS  
SDP1_3  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
JTDO  
JTMS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
JTCK  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NCAC3  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PE_RST_  
N
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PER_3_  
P
PER_3_  
N
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
Y
PET_3_  
N
VSS  
VSS  
VSS  
VSS  
PET_3_P  
VSS  
W
V
U
T
VSS  
VSS  
VSS  
VSS  
VSS  
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VSS  
PER_2_  
P
PER_2_  
N
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PET_2_  
N
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VSS  
VSS  
VSS  
VSS  
PET_2_P  
VSS  
R
P
N
M
L
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VSS  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VSS  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VSS  
VCC1P8  
VCC1P8  
VCC1P8  
VCC1P8  
VSS  
VSS  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VCC1P0  
VSS  
PE_CLK  
_P  
PE_CLK  
_N  
RSVDM  
3_NC  
RSVDM  
2_NC  
VSS  
VSS  
PE_RCO  
MP  
VCC1P0  
VCC1P0  
VSS  
VSS  
VSS  
PER_1  
_P  
PER_1  
_N  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
K
J
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PET_1_  
N
PET_1  
_P  
VSS  
VSS  
VSS  
VSS  
VCC1P0  
VCC1P0  
VSS  
VCC1P0  
VCC1P0  
VSS  
H
G
F
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PER_0_  
P
PER_0_  
N
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
E
PET_0_  
N
PET_0_P  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
D
C
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
RSVDB12 RSVDB11 RSVDB10  
_3P3  
DEV_  
OFF_N  
RMII_  
TXD[0]  
RMII_  
RXD_0  
RMII_  
TX_EN  
RMII_  
CLK_IN  
RMII_  
CLK_OUT  
NCB3  
B
_NC  
_NC  
RSVDA11  
_NC  
RMII_  
CRS_DV  
SRDS1_  
SIG_DET SIG_DET  
SRDS0_  
RSVDA8  
_NC  
RMII_  
TXD[1]  
RMII_  
RXD_1  
SDP1_1  
VSS  
VCC3P3  
5
A
12  
11  
10  
9
8
7
6
4
3
2
1
®
317679-004  
Revision: 2.11  
January 2011  
Intel 82575EB Gigabit Ethernet Controller  
Datasheet  
61  
®
Intel 82575EB Gigabit Ethernet Controller — Pin Map  
NOTE:  
This page intentionally left blank.  
®
Intel 82575EB Gigabit Ethernet Controller  
317679-004  
Revision: 2.11  
January 2011  
Datasheet  
62  

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