82575_技术文档

®

Intel 82575 Gigabit Ethernet Controller

Datasheet v1.00

June 2007

317697-001

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characterized errata are available on request.

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ii

82575 Gigabit Ethernet Controller Datasheet

Contents

1.0 Introduction..............................................................................................................1

1.1

1.2

1.3

Document Scope.................................................................................................1

Reference Documents..........................................................................................1

Block Diagram ....................................................................................................3

2.0 Features of the 82575 Gigabit Ethernet Controller.....................................................5

2.1

2.2

2.3

2.4

2.5

2.6

2.7

PCI Express Features...........................................................................................5

MAC-Specific Features .........................................................................................5

PHY-Specific Features ..........................................................................................6

Host Offloading Features ......................................................................................7

Manageability Features ........................................................................................7

Additional Device Features....................................................................................8

Technology Features............................................................................................9

3.0 Signal Descriptions and Pinout List.......................................................................... 10

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Signal Type Definitions....................................................................................... 10

PCI Express Interface ........................................................................................ 10

Power Management Signals ................................................................................ 11

System Management Interface Signals................................................................. 12

MDIO Signals.................................................................................................... 12

SPI EEPROM and FLASH Signals .......................................................................... 13

LED Signals...................................................................................................... 13

Other Signals.................................................................................................... 14

Crystal Signals.................................................................................................. 14

3.10 PHY Analog Signals............................................................................................ 15

3.11 Serializer/Deserializer Signals ............................................................................. 16

3.12 Test Interface Signals ........................................................................................ 16

3.13 Power Supply Connections.................................................................................. 17

3.13.1 Digital and Analog Supplies ..................................................................... 17

3.13.2 Grounds, Reserved Pins and No Connects.................................................. 17

4.0 Pinout/Signal Name ................................................................................................ 17

5.0 Power Requirements ............................................................................................... 38

5.1

5.2

Targeted Absolute Maximum Ratings.................................................................... 38

Targeted Recommended Operating Conditions....................................................... 38

6.0 Thermal................................................................................................................... 42

7.0 Electrical Specification............................................................................................. 42

7.1

7.2

7.3

7.4

DC Specifications .............................................................................................. 42

Resets ............................................................................................................. 46

Pull-up and Pull-down Specifications and Signals ................................................... 46

Targeted AC Characteristics................................................................................ 49

8.0 Crystal Requirements .............................................................................................. 55

9.0 LED Configuration.................................................................................................... 55

10.0 Mechanical Information........................................................................................... 56

10.1 Targeted Package Information ............................................................................ 56

10.2 Visual Pin Assignments ...................................................................................... 59

iii

82575 Gigabit Ethernet Controller Datasheet

Revision History

Date

Revision Description

August 2005

January 2006

July 2006

0.10

0.25

0.50

Initial Release

Added general information, updated pins list

Removed information regarding Fast Management Link; added general information

Added measured power values; corrected Visual Pin Assignment Diagrams (RBIAS0_N and

RBIAS1_N corrected to VSS).

February 2007

June 2007

0.75

1.0

Updated classification, changed RMII to NC-SI, updated pin list, updated NC-SI timing specs.

changed LAN_PWR_GOOD to Internal_Power_On_Reset.

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82575 Gigabit Ethernet Controller Datasheet

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82575 Gigabit Ethernet Controller Datasheet

1.0

Introduction

®

The Intel 82575 Gigabit Ethernet Controller is a single, compact component with two

fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY)

ports. The device uses the PCI Express Base Specification, Rev.1.1RD.

The Intel 82575 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BASE-T applications (802.3z, 802.3u, and 802.3ab). Ports also

contain a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber)

and Gigabit backplane applications. In addition to managing MAC and PHY Ethernet

layer functions, the controller manages PCI Express packet traffic across its

transaction, link, and physical/logical layers. The SERDES can be used in SGMII mode

to connect to external PHY, either on-board or via the SFP connector.

The Intel 82575’s on-board System Management Bus (SMB) ports enable network

manageability implementations required by information technology personnel for

remote control and alerting via the LAN. With SMB, management packets can be routed

to or from a management processor. Enhanced pass-through capabilities also allow

system remote control over standardized interfaces. Also included is a new

manageability interface, NC-SI that supports the DMTF preOS sideband protocol. An

internal management interface called MDIO enables the MAC (and software) to monitor

and control the PHY. Both ports support the Wake on LAN feature.

The 82575 Gigabit Ethernet Controller with PCI Express architecture is designed for

high performance and low memory latency. The device is optimized to connect to a

system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the

82575 controller can connect to an I/O Control Hub that has a PCI Express interface.

Wide internal data paths eliminate performance bottlenecks by efficiently handling

large address and data words. Combining a parallel and pipe-lined logic architecture

optimized for Gigabit Ethernet and independent transmit and receive queues, the

82575 controller efficiently handles packets with minimum latency. The 82575

controller includes advanced interrupt handling features, including MSI-X support. The

82575 uses efficient ring buffer descriptor data structures, with up to 64 packet

descriptors cached on chip. A large 48 KByte per port on-chip packet buffer maintains

superior performance. In addition, using hardware acceleration, the controller offloads

tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation.

The 82575 operation can be configured using EEPROM and FLASH; it can be also be

used in EEPROM-less configurations.

The 82575 is packaged in a 25mm X 25mm, 576-pin flip chip ball grid array (FCBGA).

1.1

1.2

Document Scope

This document contains targeted datasheet specifications for the 82575 Gigabit

Ethernet Controller, including signal descriptions, DC and AC parameters, packaging

data, and pinout information.

Reference Documents

This application assumes that the designer is acquainted with high-speed design and

board layout techniques. The following documents provide additional information:

82575 Gigabit Ethernet Controller Design Guide. Intel Corporation.

Intel Ethernet Controllers Timing Device Selection Guide. Intel Corporation.

PCI Express Base Specification, Revision 1.1.

1

82575 Gigabit Ethernet Controller Datasheet

PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest

Group.

PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest

Group.

IEEE Standard 802.3, 2002 Edition. Institute of Electrical and Electronics Engineers

(IEEE). This version incorporates various IEEE standards previously published

separately.

System Management Bus (SMBus) Specification, SBS Implementers Forum, Ver. 2.0,

August 2000.

INF-8074i Specification for SFP (Small Form factor Pluggable) Transceiver.

2

82575 Gigabit Ethernet Controller Datasheet

1.3

Block Diagram

FLASH

EEPROM

LAN

PCI Express (x4)

Host

Port 0

Port 1

SerDes/SGMII/SFP

82575

RMII

SMB

SerDes/SGMII/SFP

LAN

Management

LEDs

SDP

JTAG

Figure 1.

82575 Gigabit Ethernet Controller Block Diagram

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82575 Gigabit Ethernet Controller Datasheet

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4

82575 Gigabit Ethernet Controller Datasheet

2.0

Features of the 82575 Gigabit Ethernet Controller

2.1

PCI Express Features

Features

Benefits

Bus sharing not required

Low latency path to memory

Relieves congestion for IO devices connected to

ICH

•

Uses x4 PCI Express interface on MCH device

Peak bandwidth 2 GB/s in each direction per

PCI Express lane

•

Supports Gigabit Ethernet at full wire speed

Compatible extensions to PCI power

management and ACPI

PE_WAKE_N available for wakeup event

PCI Express Power Management

High bandwidth density per pin

•

Less congested board routing

64-bit address support for systems using more

than 4 GB of physical memory

•

2.2

MAC-Specific Features

Features

Benefits

•

Accelerated TCP I/O.

I/O Acceleration Technology2 (IOAT2)

Network packets handled without waiting or

buffer overflow.

Four optimized transmit and receive queues

•

Control over the transmissions of pause frames

through software or hardware triggering

IEEE 802.3x compliant flow control support

with software controllable pause times and

threshold values

Frame loss reduced from receive overruns

Efficient use of PCI Express bandwidth

Efficient packet prioritization

Caches up to 64 packet descriptors (per

queue)

•

Separate transmit and receive queues per port

Programmable host memory receive buffers

(256 Bytes to 16 KBytes) and cache line size

(64 Bytes to 128 Bytes)

•

Efficient use of PCI Express bandwidth

•

Low latency data handling

Superior DMA transfer rate performance

Wide, pipelined internal data path architecture

•

No external FIFO memory requirements

FIFO size adjustable to application

Dual 8 KByte configurable Transmit and

Receive FIFO buffers

Descriptor ring management hardware for

transmit and receive

•

Simple software programming model

Optimized descriptor fetching and write-back

mechanisms

Efficient system memory and use of PCI Express

bandwidth

5

82575 Gigabit Ethernet Controller Datasheet

Features

Benefits

Mechanism available for reducing interrupts

generated by transmit and receive operations

•

Maximizes system performance and throughput

Support for transmission and reception of

packets up to 9.5 kB

•

Enables jumbo frames

Part of the PCI standard, enables sending

interrupt messages to specific CPUs in a multiple-

cores platform

MSI-X Support

2.3

PHY-Specific Features

Features

Benefits

Control over the transmissions of pause frames

through software or hardware triggering

IEEE 802.3x compliant flow control support

with software controllable pause times and

threshold values

Frame loss reduced from receive overruns

Reliable operation at greater distances

Reliability

Line Length >140m

Operates with worst-case cable

Supports carrier extension and packet bursting

(half duplex)

Improves performance

Auto-negotiation with support for Next Page

PMA loopback capable (No echo cancel)

Advanced Power Management -

Improves performance and reliability

Facillitates testing/troubleshooting

Improves power capabilities

•

Low power link up

•

"Smart Power Down - Link disconnect

Support for limited auto MDIO register init -

limited number of registers

Improves performance

Ease of design

Fiber/Copper switch support

SERDES Signal Detect and support of non-AN

partner

Smart Speed

Auto crossover for MDI

Smart Power Down

Advanced Cable Diagnostics

2.4

Host Offloading Features

Features

Benefits

Transmit and receive IP, TCP and UDP

checksum off-loading capabilities

•

Lower CPU utilization

•

Increased throughput and lower CPU utilization

Large send offload feature (in Microsoft*

Windows* XP) compatible

Transmit TCP segmentation

IPv6 Offloading

•

Checksum and segmentation capability extended

to new standard packet type

6

82575 Gigabit Ethernet Controller Datasheet

Features

Benefits

•

Helps the driver to focus on the relevant part of

the packet without the need to parse it.

Header split replication in receive

•

16 exact matched packets (unicast or multicast)

4096-bit hash filter for multicast frames

Promiscuous (unicast and multicast) transfer

mode support

Advanced packet filtering

•

Optional filtering of invalid frames

Ability to create multiple virtual LAN segments

Insert in Tx and extract in Rx

IEEE 802.1q VLAN support with VLAN tag

insertion, stripping and packet filtering for up

to 4096 VLAN tags

•

Double Vlan

Optimized fetching and write-back mechanisms

for efficient system memory and PCI bandwidth

usage

Descriptor ring management hardware for

transmit and receive

•

High throughput for large data transfers on

networks supporting jumbo frames

9.5 kByte jumbo frame support

Receive Side Scaling (RSS)

•

Multiple Rx queues

Virtualization environment. In this environment,

packets dedicated to different virtual machines

can be routed to different queues, thus easing

the routing of these packets to the target

machine.

VMDq

•

The IO device activates a pre-fetch engine in the

CPU that loads the data into the CPU cache ahead

of time, before use, eliminating cache misses and

reducing CPU load.

Direct Cache Access (DCA)

Fragmented UDP checksum offload for packet

reassembly

2.5

Manageability Features

Features

Benefits

Advance Pass Through-compatible

management packet Tx/Rx support

ASF 1.0 and Alert on LAN 2.0

Both ports support Wake on LAN (WoL)

SMBus port

Network management flexibility

Manageability DMTF preOS sideband protocol

support

NC-SI high-bandwidth interface

Promotes customized designs

On-board microcontroller

Allows packets routing to and from either LAN

port and a server management processor

Preboot eXecution Environment (PXE) Flash

interface support (32-bit and 64-bit)

Local Flash interface for PXE image

Network Management Feature

iSCSI Boot

7

82575 Gigabit Ethernet Controller Datasheet

Features

Benefits

Compliance with PCI Power Management 1.1

and ACPI 2.0 register set compliant including:

PCI power management capability

requirements for PC and embedded

applications

•

D0 and D3 power states

•

Network Device Class Power Management

Specification 1.1

Easy system monitoring with industry standard

consoles

SNMP and RMON statistic counters

Remote network management capabilities

through DMI 2.0 and SNMP software

SDG 3.0, WfM 3.0, and PC2001 compliance

Used to give an indication to the manageability

firmware or external devices that the 82575 or

the driver is not functioning.

Watchdog Timer

SGMII interface for embedded applications

with an I2C or MDC/MDIO control interface.

Ease of embedded designs

2.6

Additional Device Features

Features

Benefits

•

Inherent dual port teaming ability

High availability using one port for failover

Higher throughput than single Gigabit Ethernet

port

Two complete Gigabit Ethernet connections in

a single device

•

Lower latency due to one electrical load on the

bus

•

Saves critical board space

Reduced multi-port Gigabit Ethernet costs

•

Supports backplane and fiber applications as well

as copper-based Gigabit via the SGMII interface

Integrated SERDES

Four activity and link indication outputs (per

port) that directly drive LEDs

Link and activity indications (10, 100, and 1000

Mbps) on each port

Software definable function (speed, link, and

activity) and blinking allowing flexible LED

implementations

Programmable LED functionality

Internal PLL for clock generation can use a 25

MHz crystal

•

Lower component count and system cost

•

Simplified testing using boundary scan

Supports the IDCODE instruction

JTAG (IEEE 1149.1) Test Access Port built in

silicon

•

Additional flexibility for LEDs or other low speed

I/O devices

Four software definable pins per port

•

Validates silicon integrity

Standard

Provides loopback capabilities

Four-wire SPI EEPROM interface

8

82575 Gigabit Ethernet Controller Datasheet

2.7

Technology Features

Features

Benefits

25 mm X 25 mm

•

576-pin Flip-Chip Ball Grid Array (FC-BGA) package

Operating temperature:

1000BASE-T, 0 °C to 55 °C*

1000BASE-SX/LX (or SERDES backplane), 0 °C to 70 °C

Storage temperature 65 °C to 140 °C

Simple thermal design

Typical targeted power dissipation:

2.43 W @ D0 1000 Mbps

•

Conditions: FF materials, nominal

voltage, 115 °C

Minimizes impact of incorporating

Gigabit instead of Fast Ethernet.

0.79 W @ D3cold 100 Mbps (wakeup enabled)

0.29 W @ D3cold (wakeup disabled)

•

Maxmum Payload Size: 128 and 256

Max number of transactions (TLP) supported on PCIe:

Four TX DMA requests + 1 TX descriptor + 1 RX

descriptor

* For information about operating the 82575 outside of this range, please refer to the 82575 Thermal

Management Application Note.

9

82575 Gigabit Ethernet Controller Datasheet

3.0

Signal Descriptions and Pinout List

The targeted signal names are subject to change without notice. Verify with your local

Intel sales office that you have the latest information before finalizing a design.

3.1

Signal Type Definitions

The signals of the 82575 controller are electrically defined as follows:

Name

Definition

DC specification

Input

See Table 9

I

Standard input only digital signal.

Output

O

Standard output only digital signal.

Tri-state

See Table 9

TS

Bi-directional three-state digital input/

output signal.

Open Drain

Wired-OR with other agents.

The signaling agent asserts the OD

signal, but the signal is returned to the

inactive state by a weak pull-up

resistor. The pull-up resistor may

require two or three clock periods to

fully restore the signal to the de-

asserted state.

See Table 10

OD

Analog

See Table 10

A

P

PCI Express*, SERDES, or PHY analog

signal.

Power

Power connection, voltage reference, or

other reference connection.

3.2

PCI Express Interface

Symbol

Type

Name and Function

PER_0_N

PER_0_P

PER_1_N

High Speed Serial Receive Data

These signals connect to corresponding PETn and PETp signals on a

system motherboard or a PCI Express connector. Series AC coupling

capacitors are required at the transmitter end. The PCI Express

differential inputs are clocked at 2.5 Gb/s.

PER_1_P

PER_2_N

A(I)

PER_2_P

PER_3_N

PER_3_P

10

82575 Gigabit Ethernet Controller Datasheet

Symbol

Type

Name and Function

PET_0_N

PET_0_P

PET_1_N

PET_1_P

PET_2_N

PET_2_P

PET_3_N

PET_3_P

High Speed Serial Transmit Data

These signals connect to corresponding PERn and PERp signals on a

system motherboard or a PCI Express connector. Series AC coupling

capacitors are required at the 82575 controller end. The PCI Express

differential outputs are clocked at 2.5 Gb/s.

A(0)

High Speed Serial Impedance Compensation

PE_RCOMP

A

Connect the recommended resistor value 1.4K Ω from this ball to

ground.

100 MHz Differential Clock for the PCI Express Interface

PE_CLK_P

PE_CLK_N

The reference clock is furnished by the system and has a 300 ppm

frequency tolerance.

PCI Express Reset

When the signal is low, all PCI Express functions are held in reset.

When the signal is high, it denotes that main power is available to the

82575 controller and the reference clock is running.

PE_RST_N

I

In systems with a PCI Express add-in card, this signal routes to the

connector.

Wake

The device drives this signal low when it receives a wake-up event and

either the PME Enable bit in the Power Management Control/Status

Register or the Advanced Power Management Enable (APME) bit of the

Wake-up Control Register (WUC) is 1b.

PE_WAKE_N

OD

3.3

Power Management Signals

Symbol

Type

Name and Function

Auxiliary Power Present.

AUX_PWR

I

If the Auxiliary Power signal is high, then auxiliary power is present

and the 82575device should support the D3_coldpower state.

LAN Disables 0 and 1

LAN0_DIS_N

LAN1_DIS_N

Disables individual Ethernet ports. State is latched upon a rising edge

of PERST_N or a PCI Express reset event. This pin has an internal

pull-up resistor.

I

Device Off

DEV_OFF_N

I

Asynchronously disables Ethernet controller.

Main Power OK

MAIN_PWR_OK

Indicates that platform main power is up. Must be connected

externally.

11

82575 Gigabit Ethernet Controller Datasheet

3.4

System Management Interface Signals

Symbol

Type

Name and Function

SMB Clock

SMBCLK

OD

The SMB Clock signal is an open drain signals for the serial SMB

interface.

SMB Data

SMBD

OD

The SMB Data signal is an open drain signal for the serial SMB

interface.

SMB Alert

The SMB Alert signal is an open drain signal for serial SMB Port A. In

ASF mode, this signal acts as a power good input. It acts as an alert

input in 82559 compatible mode.

SMBALRT_N

NCSI Reference Clock Input. Synchronous clock reference for

receive, transmit and control interface. It is a 50MHz clock /- 50

ppm.

NCSI_CLK_IN

I

NCSI Reference Clock Output. Synchronous clock reference for

receive, transmit and control interface. It is a 50MHz clock /- 50

ppm. Serves as a clock source to the BMC and Zoar (when

configured so).

NCSI_CLK_OUT

NCSI_CRS_DV

O

I

Carrier Sense / Receive Data Valid

NCSI_RXD[1]

NCSI_RXD[0]

Receive Data. Data signals from the device to the BMC

Transmit Enable

NCSI_TX_EN

NCSI_TXD[1]

NCSI_TXD[0]

I

Transmit Data. Data signals from BMC to the device

3.5

MDIO Signals

Symbol

Type

Name and Function

Management Data Clock. Used by the PHY as a clock timing

reference for information transfer on the MDIO signal. The MDC is

not required to be a continuous signal and can be frozen when no

management data is transferred. The MDC signal has a maximum

operating frequency of 2.5MHz.

MDC

I

Management Data I/O. This internal signaling between the MAC and

PHY logically represents a bi-directional data signal used to transfer

control information and status to and from the PHY (to read and

write the PHY management registers ). Asserting and interpreting

value(s) on this interface requires knowledge of the special MDIO

protocol to avoid possible internal signal contention or

MDIO

I/O

miscommunication to/from the PHY

12

82575 Gigabit Ethernet Controller Datasheet

3.6

SPI EEPROM and FLASH Signals

Symbol

Type

Name and Function

EEPROM Data Input

EE_DI

TS

The EEPROM Data Input pin is used for output to the SPI EEPROM

memory device.

EEPROM Data Output

EE_DO

EE_CS_N

EE_SK

I

The EEPROM Data Output pin is used for input from the SPI EEPROM

memory device. The EE_DO includes an internal pull-up resistor.

EEPROM Chip Select

TS

The EEPROM Chip Select signal is used to enable the device.

EEPROM Serial Clock

The EEPROM Shift Clock provides the clock rate for the SPI EEPROM

interface, which is approximately 2 MHz.

FLASH Chip Enable Output.

Used to enable FLASH device.

FLSH_CE_N

FLSH_SCK

FLSH_SI

TS

I

FLASH Serial Clock Output.

FLASH Serial Data Input.

This pin is an output to the memory device.

FLASH Serial Data Output

FLSH_SO

This pin is an input from the memory device.

3.7

LED Signals

Note:

The LED signals are push-pull (active-high) outputs. They are fully programmable

through the EEPROM interface

Symbol

Type

Name and Function

LED0_0. Programmable LED output for Port A. As the Link LED, it

indicates link connectivity on Port A.

LED0_0

O

LED0_1. Programmable LED output for Port A. As the Activity LED, it

flashes to indicate receive activity on Port A for packets destined for this

node.

LED0_1

LED0_2

O

LED0_2

Programmable LED output for Port A. As the Link 100 LED, it indicates

link at 100 Mbps for Port A.

LED0_3

LED1_0

O

Programmable LED output for Port A. As the Link 1000 LED, it indicates

link at 1000 Mbps for Port A.

LED1_0.

Programmable LED output for Port B. As the Link LED, it indicates link

connectivity on Port B.

13

82575 Gigabit Ethernet Controller Datasheet

Symbol

Type

Name and Function

LED1_1

O

Programmable LED output for Port B. As the Activity LED, it flashes to

indicate receive activity on Port B for packets destined for this node.

LED1_2

LED1_3

O

Programmable LED output for Port B. As the Link 100 LED, it indicates

link at 100 Mbps for Port B.

LED1_3

Programmable LED output for Port B. As the Link 1000 LED, it indicates

link at 1000 Mbps for Port B.

3.8

Other Signals

Symbol

Type

Name and Function

SDP0_0

SDP0_1

SDP0_2

SDP0_3

SDP1_0

SDP1_1

SDP1_2

SDP1_3

Software Defined Pin (SDP)

The Software Defined Pins are programmable with respect to input and

output capability. These pins also can optionally be configured as interrupt

inputs. SDP signals default to inputs upon power-up, but can be configured

differently by the EEPROM.

TS

3.9

Crystal Signals

Symbol

Type

Name and Function

Crystal One

The Crystal One pin is a 25 MHz input signal. It should be connected to a

parallel resonant crystal with a frequency tolerance of 30 ppm or better. The

other end of the crystal should be connected to XTAL2.

XTAL1

AI

Crystal Two

XTAL2

AO

Crystal Two is the output of an internal oscillator circuit used to drive a

crystal into oscillation.

14

82575 Gigabit Ethernet Controller Datasheet

3.10

PHY Analog Signals

Symbol

Type

Name and Function

Compensation Reference Resistor.

RBIAS0_P/RBIAS1_P

A

A 1.4 KΩ, 1% tolerance resistor should be used. RBIAS_N

should also be connected to ground (VSS).

Media Dependent Interface [0]

1000BASE-T: In MDI configuration, these correspond to

BI_DA+/-, and in MDI-X configuration, MDIp0/MDIn0

corresponds to BI_DB+/-.

MDI0_P_0

MDI0_N_0

MDI1_P_0

MDI1_N_0

A

100BASE-TX: In MDI configuration, MDIp0/MDIn0 is used for

the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is

used for the receive pair.

10BASE-T: In MDI configuration, MDIAp0/MDI_MINUS0_0 is

used for the transmit pair, and in MDI-X configuration, MDIp0/

MDIn0 is used for the receive pair.

Media Dependent Interface [1]

1000BASE-T: In MDI configuration, MDIp1/MDIn1

corresponds to BI_DB+/-, and in MDI-X configuration, MDIp1/

MDIn1 corresponds to BI_DA+/-.

MDI0_P_1

MDI0_N_1

MDI1_P_1

MDI1_N_1

A

100BASE-TX: In MDI configuration, MDIp1/MDIn1 is used for

the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is

used for the transit pair.

10BASE-T: In MDI configuration, MDIp1/MDIn1 is used for the

receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used

for the transit pair.

Media Dependent Interface [2]

MDI0_P_2

MDI0_N_2

MDI1_P_2

MDI1_N_2

1000BASE-T: In MDI configuration, MDIp2/MDIn2

corresponds to BI_DC+/-, and in MDI-X configuration, MDIp2/

MDIn2 corresponds to BI_DD+/-.

A

100BASE-TX: Unused.

10BASE-T: Unused.

Media Dependent Interface [3]

MDI0_P_3

MDI0_N_3

MDI1_P_3

MDI1_N_3

1000BASE-T: In MDI configuration, MDIp3/MDIn3

corresponds to BI_DD+/-, and in MDI-X configuration, MDIp3/

MDIn3 corresponds to BI_DC+/-.

100BASE-TX: Unused.

10BASE-T: Unused.

15

82575 Gigabit Ethernet Controller Datasheet

3.11

Serializer/Deserializer Signals

Symbol

Type

Name and Function

SERDES Receive Pairs A and B

SRDSI_0_P

SRDSI_0_N

SRDSI_1_P

SRDSI_1_N

These signals make the differential receive pair for the 1.25 GHz serial

interface. For serializer/deserializer operation, the inputs should be

coupled to ECL voltage levels. If the SERDES interface is not used,

these pins should not be connected.

AI

SERDES Transmit Pairs A and B

SRDSO_0_P

SRDSO_0_N

SRDSO_1_P

SRDSO_1_N

These signals make the differential transmit pair for the 1.25 GHz

serial interface. For serializer/deserializer operation, the outputs drive

the LVPECL voltage levels. If the SERDES interface is not used, these

pins should not be connected.

AO

Signal Detects A and B

These pins indicate whether the SERDES signals (connected to the

1.25 GHz serial interface) have been detected by the optical

transceivers. If the SERDES interface is not used with copper media,

these can be left with no connection (NC). If the SERDES interface is

not used with fiber media, the SIG_DET inputs should be tied high to

VCC.

SRDS0_SIG_DET/

SRDS1_SIG_DET

I

SERDES Impedance Compensation. Connect the recommended

resistor (1.4K Ω) from this ball to ground.

SER_RCOMP

A

Port 0 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be

used as MDC pin.

SFP0_I2C_CLK

SFP0_I2C_DATA

SFP1_I2C_CLK

SFP1_I2C_DATA

O

TS/

OD

Port 0 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be

used as MDIO pin

Port 1 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be

used as MDC pin.

O

TS/

OD

Port 1 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be

used as MDIO pin

3.12

Test Interface Signals

Note:

Pull-up resistors are needed on these signals as shown in the reference schematic.

Symbol

Type

Name and Function

JTCK

JTDI

JTDO

JTMS

I

JTAG Test Access Port Clock

I

JTAG Test Access Port Test Data In

JTAG Test Access Port Test Data Out

JTAG Test Access Port Mode Select

OD

I

16

82575 Gigabit Ethernet Controller Datasheet

3.13

Power Supply Connections

3.13.1

Digital and Analog Supplies

Symbol

Type

Name and Function

3.3 V Digital Power Supply.

For I/O circuits.

VCC3P3

P

1.8 V Analog Power Supply

VCC1P8

VCC1P0

P

For PHY analog, PHY I/O, PCI Express analog, and Phase Lock Loop circuits,

Connect all 1.8 V pins to a single power supply.

1.0 V Digital Power Supply

For core digital, PHY digital, PCI Express digital and clock circuits, connect

all 1.0 V pins to a single power supply.

3.13.2

Grounds, Reserved Pins and No Connects

Symbol

Type

Name and Function

VSS

P

Ground.

Reserved, VCC

These pins are reserved by Intel and may have factory test functions. For

normal operation, connect them directly to VCC. Do not connect them to

pull-up resistors.

RSVD_VCC

RSVD_GND

Reserved, Ground

These pins are reserved by Intel and may have factory test functions. For

normal operation, connect them directly to ground. Do not connect them to

pull-down resistors.

P

Reserved, No Connect

These pins are reserved by Intel and may have factory test functions. For

normal operation, do not connect any circuitry to these pins. Do not connect

pull-up or pull-down resistors.

RSVD_ NC

NC

P

No Connect

This pin is not connected internally.

4.0

Pinout/Signal Name

Table 1.

Pinout

Name

PE_CLK_P

PE_CLK_N

N2

N1

17

82575 Gigabit Ethernet Controller Datasheet

PET_0_P

PET_0_N

PET_1_P

PET_1_N

PET_2_P

PET_2_N

PET_3_P

PET_3_N

D2

D1

H2

H1

R2

R1

W2

W1

PER_0_P

PER_0_N

PER_1_P

PER_1_N

PER_2_P

PER_2_N

PER_3_P

PER_3_N

F2

F1

K2

K1

U2

U1

AA2

AA1

PE_WAKE_N

PE_RST_N

PE_RCOMP

AC20

AC9

L1

RSVDM3_NC

RSVDM2_NC

M3

M2

FLSH_SI

FLSH_SO

AC14

AD14

AD15

AC15

FLSH_SCK

FLSH_CE_N

18

82575 Gigabit Ethernet Controller Datasheet

EE_DI

EE_DO

A21

A20

B20

B21

EE_SK

EE_CS_N

SMBD

SMBCLK

AD21

AC21

AD20

SMBALRT_N

RSVDAD17_NC

RSVDAC17_NC

RSVDAC16_NC

RSVDAD16_NC

AD17

AC17

AC16

AD16

NCSI_CLK_IN

B5

B4

NCSI_CLK_OUT

NCSI_CRS_DV

NCSI_RXD_1

NCSI_RXD_0

A4

A6

B7

NCSI_TX_EN

NCSI_TXD_1

NCSI_TXD_0

B6

A7

B8

SDP0_0

SDP0_1

SDP0_2

A16

B16

B17

19

82575 Gigabit Ethernet Controller Datasheet

SDP0_3

B15

SDP1_0

SDP1_1

SDP1_2

SDP1_3

AD10

A12

A13

AC10

RSVDAB19_NC

RSVDAB18_NC

AB19

AB18

RSVDAD9_3P3

MAIN_PWR_OK

DEV_OFF_N

AD9

AD4

B9

RSVDL14_1P0

RSVDP14_1P0

L14

P14

XTAL1

XTAL2

N23

N24

SRDSI_0_P

SRDSI_0_N

SRDSO_0_P

SRDSO_0_N

J23

J24

K23

K24

SRDS0_SIG_DET

A9

SRDSI_1_P

SRDSI_1_N

SRDSO_1_P

SRDSO_1_N

T23

T24

R23

R24

20

82575 Gigabit Ethernet Controller Datasheet

SRDS1_SIG_DET

SER_RCOMP

A10

L22

RSVDM23_NC

RSVDM24_NC

M23

M24

SFP0_I2C_CLK/

MDC0

AD19

AD18

SFP0_I2C_DATA/

MDIO0

SFP1_I2C_CLK/

MDC1

AC19

AC18

SFP1_I2C_DATA/

MDIO1

LED0_0

LED0_1

LED0_2

LED0_3

A19

B19

B18

A18

LED1_0

LED1_1

LED1_2

LED1_3

AD13

AC11

AC13

AC12

MDI0_P_0

MDI0_N_0

MDI0_P_1

MDI0_N_1

MDI0_P_2

MDI0_N_2

MDI0_P_3

C24

C23

D24

D23

F24

F23

G24

21

82575 Gigabit Ethernet Controller Datasheet

MDI0_N_3

G23

RBIAS0_P

VSS

E22

F22

IEEE_TEST0_P

IEEE_TEST0_N

A22

B22

MDI1_P_0

MDI1_N_0

MDI1_P_1

MDI1_N_1

MDI1_P_2

MDI1_N_2

MDI1_P_3

MDI1_N_3

AB24

AB23

AA24

AA23

W24

W23

V24

V23

RBIAS1_P

VSS

Y22

W22

IEEE_TEST1_P

IEEE_TEST1_N

AD22

AC22

RSVDAD8_VSS

AD8

JTCK

JTDI

AC6

AD7

AC8

AC7

AC5

JTDO

JTMS

RSVDAC5_NC

AUX_PWR

B14

A15

LAN1_DIS_N

22

82575 Gigabit Ethernet Controller Datasheet

RSVDB12_NC

LAN0_DIS_N

RSVDA8_3P3

RSVDA11_3P3

RSVDB10_3P3

RSVDB11_3P3

RSVDA14_VSS

B12

B13

A8

A11

B10

B11

A14

NCB3

NCAC3

NCAD3

B3

AC3

AD3

VCC3P3

AD6

AD12

A5

A17

VCC1P8

P5

P4

N9

N8

N5

N4

M9

M8

M5

M4

L9

L8

L5

L4

L15

K15

23

82575 Gigabit Ethernet Controller Datasheet

VCC1P8

J15

H15

G15

E20

E19

D20

D19

Y20

Y19

V15

U15

T15

R15

P15

AA20

AA19

N21

N15

M21

M15

P9

P8

VCC1P0

R14

R13

R12

R11

P13

P12

L13

L12

K14

K13

24

82575 Gigabit Ethernet Controller Datasheet

VCC1P0

K12

K11

V5

V4

U5

U4

P11

N11

M11

L11

H5

H4

G5

G4

J21

J20

J18

J17

L21

L20

L18

L17

K21

K20

K18

K17

T21

T20

T18

T17

P21

P20

P18

25

82575 Gigabit Ethernet Controller Datasheet

VCC1P0

P17

R21

R20

R18

R17

VSS

Y9

Y8

Y7

Y6

Y15

Y14

Y13

Y12

Y11

Y10

W9

W8

W7

W22

W14

W13

W12

W11

W10

V9

V8

V14

V13

V12

V11

V10

U9

26

82575 Gigabit Ethernet Controller Datasheet

VSS

U14

U13

U12

U11

U10

T14

T13

T12

T11

N14

N13

N12

M14

M13

M12

J14

J13

J12

J11

H9

H14

H13

H12

H11

H10

G9

G8

G14

G13

G12

G11

G10

F22

27

82575 Gigabit Ethernet Controller Datasheet

VSS

F9

F8

F7

F14

F13

F12

F11

F10

E9

E8

E7

E6

E15

E14

E13

E12

E11

E10

D9

D8

D7

D6

D5

D16

D15

D14

D13

D12

D11

D10

C9

C8

C7

28

82575 Gigabit Ethernet Controller Datasheet

VSS

C6

C5

C4

C17

C16

C15

C14

C13

C12

C11

C10

B2

B1

AD5

AD2

AD11

AD1

AC4

AC2

AC1

AB9

AB8

AB7

AB6

AB5

AB4

AB17

AB16

AB15

AB14

AB13

AB12

AB11

29

82575 Gigabit Ethernet Controller Datasheet

VSS

AB10

AA9

AA8

AA7

AA6

AA5

AA16

AA15

AA14

AA13

AA12

AA11

AA10

A3

A2

A1

Y24

Y23

Y21

Y18

Y17

Y16

W21

W20

W19

W18

W17

W16

W15

V22

V21

V20

V19

30

82575 Gigabit Ethernet Controller Datasheet

VSS

V18

V17

V16

U24

U23

U22

U21

U20

U19

U18

U17

U16

T22

T19

T16

R22

R19

R16

P24

P23

P22

P19

P16

N22

N20

N19

N18

N17

N16

M22

M20

M19

M18

31

82575 Gigabit Ethernet Controller Datasheet

VSS

M17

M16

L24

L23

L19

L16

K22

K19

K16

J22

J19

J16

H24

H23

H22

H21

H20

H19

H18

H17

H16

G22

G21

G20

G19

G18

G17

G16

F21

F20

F19

F18

F17

32

82575 Gigabit Ethernet Controller Datasheet

VSS

F16

F15

E24

E23

E21

E18

E17

E16

D22

D21

D18

D17

C22

C21

C20

C19

C18

B24

B23

AD24

AD23

AC24

AC23

AB22

AB21

AB20

AA22

AA21

AA18

AA17

A24

A23

Y5

33

82575 Gigabit Ethernet Controller Datasheet

VSS

Y4

Y3

Y2

Y1

W6

W5

W4

W3

V7

V6

V3

V2

V1

U8

U7

U6

U3

T9

T8

T7

T6

T5

T4

T3

T2

T10

T1

R9

R8

R7

R6

R5

R4

34

82575 Gigabit Ethernet Controller Datasheet

VSS

R3

R10

P7

P6

P3

P2

P10

P1

N7

N6

N3

N10

M7

M6

M10

M1

L7

L6

L3

L2

L10

K9

K8

K7

K6

K5

K4

K3

K10

J9

J8

J7

J6

35

82575 Gigabit Ethernet Controller Datasheet

VSS

J5

J4

J3

J2

J10

J1

H8

H7

H6

H3

G7

G6

G3

G2

G1

F6

F5

F4

F3

E5

E4

E3

E2

E1

D4

D3

C3

C2

C1

AB3

AB2

AB1

AA4

36

82575 Gigabit Ethernet Controller Datasheet

VSS

AA3

37

82575 Gigabit Ethernet Controller Datasheet

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38

82575 Gigabit Ethernet Controller Datasheet

5.0

Power Requirements

5.1

Targeted Absolute Maximum Ratings

Table 2.

Absolute Maximum Ratings¹

Symbol

Parameter

Min

Max

Unit

DC supply voltage on 3.3 V

pins with respect to VSS

VCC(3.3)

VSS - 0.5

4.6

2.5

1.7

V

DC supply voltage on 1.8 V

pins with respect to VSS²

VCC(1.8)

VCC(1.0)

VSS - 0.3

VSS - 0.2

DC supply voltage on 1.0 V

pins with respect to VSS^b

3.3 V I/O Voltage

1.8 V I/O Voltage

1.0 V I/O Voltage

VSS - 0.5

VSS - 0.3

VSS - 0.2

4.6

2.5

1.7

V_I/ V_O

V

I_O

DC output current

N/A

-65

0

TBD

140

85

mA

T_storage

T_case

Storage temperature range

°C

Case temperature under bias

ESD per MIL_STD-883 Test

Method 3015, Specification

2001V Latchup Over/

VDD overstress:

VDD(3.3) * (7.2

V)

N/A

V

Undershoot: 150 mA, 125° C

1. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings

in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal

device operations.

2. During normal device power up and power down, the 1.8 V and 1.0 V supplies must not ramp before the 3.3

V supply.

5.2

Targeted Recommended Operating Conditions

General Operating Conditions

5.2.1

Table 3.

Recommended Operating Conditions ¹

Symbol

Parameter

Min

Max

Unit

VCC(3.3)

VCC(1.8)

VCC(1.0)

DC supply voltage on 3.3 V pins

DC supply voltage on 1.8 V pins

DC supply voltage on 1.0 V pins

3.0

3.6

V

1.71

0.95

1.89

1.05

Input rise/fall time (normal

input)

tR / tF

0

200

ns

Operating temperature range

(ambient)

T_a

T_J

0

55

°C

Junction temperature

N/A

≤110

1. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute

maximum rating limits, might result in permanent damage. Device functionality to stated DC and AC limits is

not guaranteed, if conditions exceed recommended operating conditions.

39

82575 Gigabit Ethernet Controller Datasheet

5.2.2

Voltage Ramp and Sequencing Recommendations

The following tables give the specifications for the power supply ramps:

Table 4.

3.3 V Supply Voltage Ramp

Parameter

Description

Min

Max

Unit

Rise Time

Time from 10% to 90% mark

0.1

100¹

0

ms

Monotonicity Voltage dip allowed in ramp

N/A

mV

Ramp rate at any time between

Slope

24

3

28800

3.6

mV/ms

V

10% to 90%

Operational

Range

Voltage range for normal

operating conditions

Maximum voltage ripple at a

bandwidth equal to 50 MHz

Ripple

N/A

70

mV_peak-peak

Ripple

Overshoot time upon ramp²

Maximum voltage allowed^b

N/A

0.05

100

ms

Overshoot

mV

1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.

2. Excessive overshoot can affect long term reliability.

Table 5.

1.8 V Supply Voltage Ramp

Parameter

Description

Min

Max

Unit

Rise Time

Time from 10% to 90% mark

0.1

100¹

0

ms

Monotonicity Voltage dip allowed in ramp

N/A

mV

Ramp rate at any time between

Slope

14

60000

1.89

40

mV/ms

V

10% to 90%

Operational

Range

Voltage range for normal

operating conditions

1.71

N/A

Maximum voltage ripple at a

bandwidth equal to 1 MHz

Ripple

mV_peak-peak

Overshoot

Overshoot time upon ramp²

Maximum voltage allowed^b

N/A

0.1

ms

SettlingTime

Overshoot

100

mV

1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.

2. Excessive overshoot can affect long term reliability.

Table 6.

1.0 V Supply Voltage Ramp

Parameter

Description

Min

Max

Unit

Rise Time

Time from 10% to 90% mark

Voltage dip allowed in ramp

0.1

100¹

0

ms

Monotonicity

N/A

mV

Ramp rate at any time between

10% to 90%

Slope

7.6

33600

1.05

mV/ms

V

Operational

Range

Voltage range for normal

operating conditions

0.95

40

82575 Gigabit Ethernet Controller Datasheet

Maximum voltage ripple at a

Ripple

N/A

40

mV_peak-peak

bandwidth equal to 1 MHz

Overshoot time upon ramp²

Maximum voltage allowed^b

Overshoot

SettlingTime

N/A

0.05

100

ms

Overshoot

mV

1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.

2. Excessive overshoot can affect long term reliability.

Table 7.

Power Supply Sequencing

Symbol

Parameter

Min

Max

Unit

VCC3p3 (3.3 V) stable to VCC1p8

stable

T_{3 18}

T_{18 1}

T_{3 1}

0

100

ms

VCC1p8 stable to VCC (1.0 V)

stable

0

ms

mV

ms

VCC3p3 (3.3 V) stable to VCC

(1.0 V) stable

100

3.3 V core to GIO_PWR_GOOD

and MAIN_PWR_OK on

T_m-per, T_m-ppo

_per-m, T_ppo-m

TBD

0

GIO_PWR_GOOD,MAIN_PWR_OK

off before 3.3 V core down

T

Aux power stable

VCCP (3.3V)

VCC1p8 (1.8V)

T3_18

VCC/VCC1p0(1V)

Tlpgw

T18_1

Power-on Reset

(internal)

T3_1

Tlpg

Main Power stable

Main power stable

GIO_PWR_GOOD

MAIN_PWR_OK

Tm-per

Tm-ppo

Tper-m

Tppo-m

Tlpg-per

Figure 2.

Voltage Power Sequencing Options

To meet the 375 mA inrush current requirements (not including external capacitors)

the ramp time should be 5 ms -100 ms on all power rails. For faster ramps (100 us - 5

ms), expect higher inrush current due to the high charging current of the decoupling

capacitors of 3.3 V, 1.8 V and 1.0 V rails.

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82575 Gigabit Ethernet Controller Datasheet

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42

82575 Gigabit Ethernet Controller Datasheet

6.0

Thermal

The 82575 device is specified for operation when the ambient temperature (TA) is

within the range of 0 °C to 55 °C. For information about the thermal characteristics of

the device, including operation outside this range, please refer to the 82575 Thermal

Application Note.

7.0

Electrical Specification

7.1

DC Specifications

Table 8.

DC Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

DC supply voltage on

3.3 V pins

VCC(3.3)

3.00

3.30

3.60

V

DC supply voltage on

1.8 V pins

VCC(1.8)

VCC(1.0)

1.71

0.95

1.80

1.00

1.89

1.05

V

DC supply voltage on

1.0 V pins

Table 9.

I/O Characteristics

1

Symbol

Parameter

Condition

Min

Typ

Max

Units

VCC(3.3)

+ 0.5

V_IH

Input high voltage

Input low voltage

Input current

2.0

-0.5

-15

N/A

V

V_IL

I_IN

0.8

15

V_IN= VDD(3.3) or

V_SS

μA

I_OH= -16 mA

V_CC= Min

2.4

V_CC- 0.02

N/A

0.4

V_OH

Output high voltage

Output low voltage

V

I

_OH= -100 μA

V_CC= Min

I_OL= 14 mA

V_CC= Min

V_OL

V

I

_OL= 100 μA

N/A

-10

N/A

0.2

10

V_CC= Min

Off-state output

leakage current

I_OZ

V_O= V_CCor V_SS

μA

2

C_IN

PU

Input capacitance

Internal pull-up

Overshoot

N/A

2.6

2.5

N/A

5.5

pF

kΩ

V

V_OS

V_US

N/A

4.0

Undershoot

-0.4

V

1. The input buffer also has hysteresis > 160 mV.

43

82575 Gigabit Ethernet Controller Datasheet

2. C = 2.5 pF(maximum input capacitance), C

in

= 16 pF (characterized max output load capacitance per 160

out

MHz).

Table 10.

Open Drain I/O

Symbol

Parameter

Condition

Min

Max

Units

Note

VCC3P3

VCC

Vih

Periphery supply

Core supply

3.0

0.9

2.1

3.6

V

1.32

Input High Voltage

Input Low Voltage

Vil

0.8

+/-10

0.4

Output Leakage

Current

Ileakage

0 < Vin < VCC3P3

ìA

2

4

Vol

Output Low Voltage

Current sinking

@ Ipullup

Vol=0.4V

V

Ipullup

4

mA

Input Pin

Cin

Cout

7

pF

ìA

3

2

Capacitance

Output Pin

Capacitance

30

Input leakage

current

VCC3P3 off or

floating

Ioffsmb

+/-10

Notes:

1.

2.

3.

4.

Applies to SMBD0, SMBCLK0, , SMBALRT _N, PE_WAKE_n, SFP1_I2C_Data, SFP0_I2C_Data pads.

Device meets this whether powered or not.

Characterized, not tested.

OD no high output drive. VOL max=0.4V at 14mA, VOL max=0.2V at 0.1mA

Table 11.

Power Consumption

D0a--Active Link

@10

Mbps

@100

Mbps

@ 1000 Mbps

(copper)

@ 1000 Mbps

(SERDES)

Typ Icc Typ Icc Typ Icc MaxIcc

Typ Icc Max Icc

1

2

(mA)

3.3 V

1.8 V

1.0 V

18

23

19

344

304

312

388

841

856

142

354

203

492

1184

Total

Device

Power

0.98 W 1.01 W 2.43 W 2.80 W 0.67 W 0.92 W

1. Typical conditions: operating temperature (T ) = 25 C, nominal voltages

A

and moderate network traffic at full duplex.

2. Maximum conditions: maximum operating temperature (T ) values,

J

typical voltage values and continuous network traffic at full duplex.

44

82575 Gigabit Ethernet Controller Datasheet

D0a--Idle Link

Unplugged--no link

LOs only

1

Typ Icc (mA)

3.3 V

1.8 V

1.0 V

18

129

264

Total

Device

Power

0.56

2

1. Typical conditions: room

temperature (TA)=25C, nominal

voltages and idle network (no

traffic) at full duplex

2. Known errata on LOs & L1 states

might impact devide power

consumption

D0a--Idle Link

@10Mbps

LOs only

Typ Icc (mA)

1

3.3 V

1.8 V

1.0 V

18

140

302

Total

Device

Power

0.61 W

2

1. Typical

conditions:

room

temperature (TA)=25C, nominal

voltages and idle network (no

traffic) at full duplex

2. Known errata on LOs & L1 states

might impact devide power

consumption

D0a--Idle Link

@100Mbps

(Copper)

LOs only

Typ Icc (mA)

1

3.3 V

18

45

82575 Gigabit Ethernet Controller Datasheet

D0a--Idle Link

@100Mbps

(Copper)

LOs only

Typ Icc (mA)

1

1.8 V

1.0 V

837

755

Total

Device

Power

2.32 W

2

1. Typical

conditions:

room

temperature

(TA)=25C,

nominal voltages and idle

network (no traffic) at full

duplex

2. Known errata on LOs & L1

states might impact devide

power consumption

D0a--Idle Link

@1000Mbps

(SERDES)

1

Typ Icc (mA)

3.3 V

1.8 V

1.0 V

17

142

341

Total

Device

0.65 W

2

Power

1. Typical

conditions:

room

temperature

(TA)=25C,

nominal voltages and idle

network (no traffic) at full

duplex

2. Known errata on LOs & L1

states might impact devide

power consumption

D3cold - wake-up

enabled

D3cold-

wake

disabled

@10

Mbps

@100

Mbps

Typ Icc

(mA)

Typ Icc

(mA)

Typ Icc

(mA)

3.3 V

18

46

82575 Gigabit Ethernet Controller Datasheet

D3cold - wake-up

enabled

D3cold-

wake

disabled

@10

Mbps

@100

Mbps

Typ Icc

(mA)

Typ Icc

(mA)

Typ Icc

(mA)

1.8 V

1.0 V

98

269

249

83

70

168

Total

Device

Power

0.40 W

0.79 W

0.29 W

D(r) Uninitialized

Disabled through

DEV_OFF_N

Typ Icc (mA)

3.3 V

1.8 V

1.0 V

11

179

283

Total Device

Power

0.64

7.2

Resets

Power-on Reset (internal): The 82575 has an internal mechanism for sensing the

power pins. Once the power is up and stable, it creates an internal reset, this reset acts

as a master reset of the entire chip. It is level sensitive, and while it is 0, will hold all of

the registers in reset. Power-on Reset is interpreted to be an indication that device

power supplies are all stable. Power-on Reset changes state during system power-up.

In-band PCIe Reset: The 82575 will generate an internal reset in response to a

physical layer message from the PCIe or when the PCIe link halts (entry to Polling or

Detect state). This reset is equivalent to PCI reset in previous (PCI) gigabit LAN

controllers.

Main_Power_Good: Used by the device to detect the D3Cold condition and activate

part of the power saving scheme. Also used to change the state of the ASF

manageability firmware.

47

82575 Gigabit Ethernet Controller Datasheet

7.3

Pull-up and Pull-down Specifications and Signals

Table 12.

Internal and External Pull-up and Pull-down Values

Min

Nominal

5K

Max

Units

PU (Internal)

2.7K

8.6K

Ω

PU (External,

recommende

d)

<3K

Ω

PD (External,

reccommend

ed)

<400

For external Pull-up requirements, see the 82575 reference schematics.

The table below lists internal & external pull-up resistors and whether they are

activated in the different device states. Each internal PUP has a nominal value of 5kΩ,

ranging from 2.7KΩ to 8.6KΩ.

The device states are defined as follow:

Power-up = while 3.3 V is stable, but not 1.0 V

Active = normal mode (not power up nor disable)

Disable = device disabled

Table 13.

Internal Pull-up and External Pull Up Requirements

External

Recomended?

Signal Name

Power up

Active

Disable

Notes

PE_WAKE_N

PE_RST_N

FLSH_SI

FLSH_SO

FLSH_SCK

FLSH_CE_N

EE_DI

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

EE_DO

EE_SK

N

EE_CS_N

SMBD

Y

SMBCLK

SMBALRT_N

Y

48

82575 Gigabit Ethernet Controller Datasheet

NCSI_CLK_IN

N

Y

N

NCSI_CLK_OUT

Pull down only if NCSI is

NOT being used or

NCSI_CRS_DV

NCSI_RXD[1:0]

NCSI_TX_EN

N

Y

configured for multi drop

Pull Up only if NCSI is NOT

being used or configured

for multi drop

Should be connected to

external PD if NCSI is NOT

used

N

Should be connected to

external PD if NCSI is NOT

used

NCSI_TXD[1:0]

SDP0[3:0]

SDP1[3:0]

Y

N

Must be

connected on

board

DEV_OFF_N

Y

N

Must be

connected on

board

MAIN_PWR_OK

SRDS_0_SIG_DET

SRDS_1_SIG_DET

Must be

connected

externally

Must be

connected

externally

SFP0_I2C_CLK

SFP0_I2C_DATA

SFP1_I2C_CLK

SFP1_I2C_DATA

LED0_0

Y

N

Y

N

Y

Y if active

If used.

Y

Y if active

Y

N

LED0_1

LED0_2

LED0_3

LED1_0

LED1_1

LED1_2

LED1_3

JTCK

N

49

82575 Gigabit Ethernet Controller Datasheet

JTDI

JTDO

Y

N

Y

N

Y

JTMS

AUX_PWR

LAN1_DIS_N

LAN0_DIS_N

Y (or PD)

Y

7.4

Targeted AC Characteristics

Table 14.

25 MHz Clock Input Requirements

Symbol

Parameter

Min

Typ

Max

Unit

Frequency

f0

N/A

-50

40

25.000

N/A

20

N/A

+50

60

MHz

ppm

%

Frequency Variation

Duty Cycle

df0

Dc

tr

Rise Time

N/A

5

ns

Fall Time

tf

5

ns

1

Clock Jitter (peak-to-peak)

Input Capacitance

Operating Temperature

Jptp

C_in

T

250

N/A

70

ps

pF

N/A

°C

Input clock amplitude (peak-to-

peak)

Aptp

Vcm

1.0

1.2

0.6

1.3

V

Clock common mode

N/A

1. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000Base-T Standard (at

5

least 10 clock edges, filtered by HPF with cut off frequency of 5000 Hz).

Table 15.

Link Interface Clock Requirements

Symbol

Parameter

Min

Typ

Max

Unit

fGTX¹

GTX_CLK frequency

N/A

125

N/A

MHz

1. GTX_CLK is used externally for test purposes only. See signals IEEE_TEST1_p and IEEE_TEST1_n.

7.4.1

EEPROM Interface

Applicable over recommended operating range from Ta = -40C to +85C, VCC3P3 = 3.3

V, Cload = 1 TTL Gate and 16pF (unless otherwise noted).

Symbol

Parameter

Min

Typ

Max

Units

Note

50

82575 Gigabit Ethernet Controller Datasheet

t_SCK

t_RI

SCK clock frequency

Input rise time

Input fall time

SCK high time

SCK low time

0

2

2.1

2

MHz

us

ns

[1]

[2]

2.5ns

250

t_FI

2

t_WH

t_WL

t_CS

t_CSS

t_CSH

t_SU

t_H

200

250

50

250

CS high time

CS setup time

CS hold time

Data-in setup time

Data-in hold time

Output valid

50

t_V

0

200

250

t_HO

t_DIS

Output hold time

Output disable time

0

1.

2.

Clock is 2MHz

50% duty cycle

t_CS

V_IH

V_IL

CS

t_CSS

t_CSH

V_IH

V_IL

t_WL

SCK

t_WH

t_SU

t_H

V_IH

V_IL

SI

VALID IN

t_V

t_HO

t_DIO

V_IH

V_IL

Hi-Z

SO

Figure 3.

EEPROM Interface Time Diagram

7.4.2

FLASH Interface

Applicable over recommended operating range from Ta = -40C to +85C, VCC3P3 = 3.3

V, Cload = 1 TTL Gate and 16 pF (unless otherwise noted)

51

82575 Gigabit Ethernet Controller Datasheet

Table 16.

FLASH Parameters

Symbol

Parameter

Min

Typ

Max

Units

Note

t_SCK

t_RI

SCK clock frequency

Input rise time

Input fall time

SCK high time

SCK low time

0

15.625

2.5

20

MHz

ns

[1]

t_FI

2.5

t_WH

t_WL

t_CS

t_CSS

t_CSH

t_SU

t_H

20

25

5

32

[2]

32

CS high time

CS setup time

CS hold time

Data-in setup time

Data-in hold time

Output valid

5

t_V

20

t_HO

t_DIS

Output hold time

Output disable time

0

100

tCS

VIH

CS

VIL

tCSH

tcss

VIH

tWH

tWL

Sck

SI

VIL

tSU

tH

VIH

VALID IN

VIL

tHO

tDIS

tv

VOH

HI-Z

SO

VOL

Figure 4.

FLASH Timing Diagram

7.4.3

NC-SI Interface

Table 17.

NC-SI AC Specification

Symbol

Parameter

Min

Typ

Max

Units

Notes

52

82575 Gigabit Ethernet Controller Datasheet

REF_CLK Frequency

50

MHz

%

2

1

REF_CLK Duty Cycle

REF_CLK accuracy

35

65

100

ppm

TXD[1:0], TX_EN, Data Setup to REF_CLK

rising edge

Tsu

Thold

Tval

3

ns

TXD[1:0], TX_EN Data hold from REF_CLK

rising edge

1.5

1.8

6

RXD[1:0], CRS_DV Data valid from REF_CLK

rising edge

9

Tor

Tof

RXD[1:0], CRS_DV Output Time rise

RXD[1:0], CRS_DV Output Time fall

RXD[1:0], CRS_DV Output delay rise

RXD[1:0], CRS_DV Output delay fall

TXD[1:0], TX_EN Input delay rise

TXD[1:0], TX_EN Input delay fall

TXD[1:0], TX_EN Input Time rise

0.5

2

6

ns

3

Todr1

Todf1

Tidr2

Tidf2

Tir

5.8

6

3

2

3

0.5

0.02

4, 5

6

0.15

Tif

TXD[1:0], TX_EN Input Time fall

Notes:

1. Clock Duty cycle measurement: High interval measured from Vih to Vil points, Low from Vil to next Vih

2. Clock interval measurement from Vih to Vih

3. Cload = 25 pF

4. Cload = 200 fF

5. The input delay test conditions: Maximum input level = VIN = 2.7V; Input rise/fall time (0.2VIN to 0.8VIN)

= 1ns (Slew Rate ~ 1.5ns).

6. The NC-SI specification defines a hold time of 1.0 ns. In order to work with the 82575, the board designer

should guarantee a hold time of 1.5 ns.

7.4.4

SMBus Interface

Table 18.

SMBus AC Characteristics (master mode)

Symbol

F_SMB

Parameter

Min

Typ

Max

100

Units

kHz

SMBus Frequency

74.4

Time between STOP and START

condition driven by the device

T_BUF

6.56

6.72

µs

Hold time after Start Condition. After

this period, the first clock is generated.

T_HD:STA

T_SU:STA

T_SU:STO

T_HD:DAT

T_TIMEOUT

T_LOW

Start Condition setup time

Stop Condition setup time

Data hold time

µs

ms

µs

6.88

0.48

Detect SMBClk low timeout

SMBClk low time

26.2

31.5

5.76

53

82575 Gigabit Ethernet Controller Datasheet

T_HIGH

SMBClk high time

6.56

µs

Table 19.

SMBus AC Characteristics (slave mode)

Symbol

Parameter

Min

Typ

Max

Units

F_SMB

T_BUF

SMBus Frequency

74.4

100

kHz

Time between STOP and START

condition driven by the device

6.56

6.72

µs

Hold time after Start Condition. After

this period, the first clock is generated.

T_HD:STA

T_SU:STA

T_SU:STO

T_HD:DAT

T_TIMEOUT

T_LOW

Start Condition setup time

Stop Condition setup time

Data hold time

TBD

6.88

0.48

µs

ms

µs

Detect SMBClk low timeout

SMBClk low time

26.2

31.5

5.76

6.56

T_HIGH

SMBClk high time

Table 20.

AC Test Loads for General Output Pins

Symbol

Parameter

Min

Typ

Max

Unit

C_L

Capacitance of test load

N/A

16

N/A

pF

C_L

Figure 5.

AC Test Loads for General Output Pins

54

82575 Gigabit Ethernet Controller Datasheet

This page intentionally left blank.

55

82575 Gigabit Ethernet Controller Datasheet

8.0

Crystal Requirements

Table 21.

Reference Crystal Specification Requirements

Parameter Name

Symbol

Recommended Value

Conditions

Frequency

Vibration mode

f_o

25.000 [MHz]

Fundamental

AT

@25 [°C]

Cut

Operating /Calibration Mode

Frequency Tolerance @25°C

Temperature Tolerance

Operating Temperature

Parallel

Δf/f_o@25°C

Δf/f_o

T_opr

R_s

±30 [ppm]

@25 [°C]

±30 [ppm]

-20 to +70 [°C]

-40 to +90 [°C]

50 [Ù] maximum

20 [pF] (max 24pF)

6 [pF] maximum

15 [ppm/pF] maximum

0.5 [mW]

Non Operating Temperature Range

Equivalent Series Resistance (ESR)

Load Capacitance

@25 [MHz]

C_load

C_o

Shunt Capacitance

Pullability from Nominal Load Capacitance

Max Drive Level

Δf/C_load

D_L

Insulation Resistance

IR

500 [MΩ] minimum

±5 [ppm/year[

2 [pF]

@ 100V DC

Aging

Δf/f_o

C_D

Differential board capacitance^*

Board Capacitance

C_s

4 [pF]

External Capacitors

C₁, C₂

R_s

27 [pF]

Board Resistance

0.1 [Ω]

9.0

LED Configuration

The 82575provides 4 LEDs per port that may be used to indicate the status of the

traffic. The default setup of the LEDs is done via the EEPROM words 1Ch and 1Fh. The

default setup for both ports is the same. This setup is reflected in the LEDCTL register

of each port. Each driver may change its setup individually. For each of the LEDs the

following parameters can be defined:

1. Mode: Defines which information is reflected by this LED. The encoding is described

in the LEDCTL register.

2. Polarity: Defines the polarity of the LED.

3. Blink mode: should the LED blink or be stable.

In addition, the blink rate of all LEDs can be defined. The possible rates are 200 ms or

83 ms for each phase. There is one rate for all LEDs

56

82575 Gigabit Ethernet Controller Datasheet

10.0

Mechanical Information

This section describes the 82575 device physical characteristics.

The targeted signal names are subject to change without notice. Verify with your local

Intel sales office that you have the latest information before finalizing a design.

10.1

Targeted Package Information

The 82575device is a 576-lead flip-chip ball grid array (FC-BGA) measuring 25 mm by

25 mm. The nominal ball pitch is 1 mm. See Figure 9.

Detail Area

0.43 mm

Solder Resist Opening

0.62 mm

Metal Diameter

57

82575 Gigabit Ethernet Controller Datasheet

58

82575 Gigabit Ethernet Controller Datasheet

Figure 6.

82575 Mechanical Specifications

59

82575 Gigabit Ethernet Controller Datasheet

10.2

Visual Pin Assignments

This section contains the illustrations of the pin outs.

Figure 7.

82575 Visual Pin Assignment Part 1 (Top View)

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82575 Gigabit Ethernet Controller Datasheet

Figure 8.

82575 Visual Pin Assignment Part 2 (Top View)

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61

82575 Gigabit Ethernet Controller Datasheet

Figure 9.

82575 Visual Pin Assignment Part 3(Top View)

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82575 Gigabit Ethernet Controller Datasheet

Figure 10.

82575 Visual Pin Assignment Part 4 (Top View)

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63


型号：	82575
厂家：	INTEL
描述：	Gigabit Ethernet Controller 千兆位以太网控制器变压器控制器以太网
文件：	总69页 (文件大小：537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

82575 [INTEL]

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