TUA6010XS [INFINEON]
Wireless Components; 无线组件
| 型号： | TUA6010XS |
| 厂家： | 
Infineon |
| 描述： | Wireless Components |
| 文件： | 总32页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
TV Mixer-Oscillator-PLL
TUA 6010XS Version 1.0
Specification August 1999
preliminary
Revision History: Current Version: 08.99
Previous Version:Data Sheet
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
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Edition 03.99
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© Infineon Technologies AG i. Gr. 24.08.99.
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TUA 6010XS
preliminary
Product Info
Product Info
Package
General Description The TUA 6010XS device combines a
digitally programmable phase locked
loop (PLL), with a mixer-oscillator block
including two balanced mixers and
oscillators for use in TV tuners.
Features ■ PLL with short lock-in time; no
asynchronous divider stage
■ Fast I2C bus mode possible
■ 4 programmable chip addresses
■ Short pull-in time for quick channel
access and optimized loop stability
■ 3 high-current switch outputs
■ 2 TTL inputs
■ 5-level A/D converter
■ Lock-in flag
■ Double balanced mixer with wide
dynamic range and low-impedance
inputs for the VHF, HYPER and
UHF frequency range
■ Power-down flag
■ Few external components
■ Internal band switch
■ Frequency and amplitude-stable
balanced oscillator for the VHF,
HYPER and UHF frequency range
■ Internal low-noise reference volt-
age source
■ Package TSSOP 28
■ Full ESD protection
■ Optimum decoupling of input
frequency from oscillator
Application ■ The IC is suitable for all tuners in
TV- and VCR-sets or cable set-top
receivers for analog TV an Digital
Video Broadcasting.
Ordering Information
Type
Ordering Code
Q67007-A5211
Package
TUA 6010 XS
P-TSSOP-28-1
Wireless Components
Product Info
Specification, August 1999
1
Table of Contents
1
2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.1 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.2 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.3 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA 6010XS
preliminary
Product Description
2.1 Overview
The TUA 6010XS device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscilla-
tors for use in TV tuners.
The PLL block with four hard-switched chip addresses forms a digitally pro-
grammable phase locked loop. With a 4 MHz quartz crystal, the PLL permits
precise setting of the frequency of the tuner oscillator up to 900 MHz in incre-
ments of 62.5 kHz. The tuning process is controlled by a microprocessor via an
I2C bus. The device has three output ports, which all can also be used as input
ports (two TTL inputs and one A/D converter input). A flag is set when the loop
is locked. The input ports and lock flag can be read by the processor via the I2C
bus. The mixer-oscillator block includes two balanced mixers (double balanced
mixer with low-impedance input), two frequency and amplitude-stable balanced
oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and
a band switch.
2.2 Features
■ PLL with short lock-in time; no asynchronous divider stage
■ Fast I2C bus mode possible
■ 4 programmable chip addresses
■ Short pull-in time for quick channel access and optimized loop stability
■ 3 high-current switch outputs
■ 2 TTL inputs
■ 5-level A/D converter
■ Lock-in flag
■ Power-down flag
■ Few external components
■ Frequency and amplitude-stable balanced oscillator for the VHF, HYPER
and UHF frequency range
■ Optimum decoupling of input frequency from oscillator
■ Double balanced mixer with wide dynamic range and low-impedance inputs
for the VHF, HYPER and UHF frequency range
■ Internal band switch
■ Internal low-noise reference voltage source
■ Package TSSOP 28
■ Full ESD protection
Wireless Components
2 - 2
Specification, August 1999
TUA 6010XS
preliminary
Product Description
2.3 Application
■ The IC is suitable for all tuners in TV- and VCR-sets or cable set-top
receivers for analog TV an Digital Video Broadcasting.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2 - 3
Specification, August 1999
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
TUA 6010XS
preliminary
Functional Description
3.1 Pin Configuration
MIXU
MIXUx
MIXV
MIXVx
VVCCA
CAS
1
2
3
4
5
6
7
8
9
28 OU-B2
27 OU-C1
26 OU-C2
25 OU-B1
24 OV-B2
23 OV-C1
22 OV-C2
21 OV-B1
20 GNDA
IFout
TUA 6010XS
IFoutx
GNDD
SDA 10
SCL 11
VVCCD 12
19 TUNE
18 CHGPMP
17 P0 / I0
16 P1 / I1
15 P2 / ADC
Q
13
QX 14
Pin_config.wmf
Figure 3-1
Pin Configuration
Wireless Components
3 - 2
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No. Symbol
Function
UHF mixer input, low-impedance, symmetri-
cal to MIXUx
1
2
MIXU
UHF mixer input, low-impedance, symmetri-
cal to MIXU
MIXUx
1
2
3
4
MIXV
VHF or HYPER mixer input, low-imped-
ance, symmetrical to MIXVx
MIXVx
VHF or HYPER mixer input, low-imped-
ance, symmetrical to MIXV
3
4
5
6
VVCCA
CAS
Positive supply voltage for analog block
Chip address select
6
7
IFout
Open collector mixer output, high-imped-
ance, symmetrical to IFoutx
8
7
8
9
IFoutx
GNDD
Inverse open collector mixer output, high-
impedance, symmetrical to IFout
Digital Ground
Wireless Components
3 - 3
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
Data input/output for the I2C bus
10
SDA
10
Clock input for the I2C bus
11
SCL
11
12
13
VVCCD
Positive supply voltage for digital block
(PLL)
Q
4 MHz low-impedance crystal oscillator
input
13
14
Inverse 4 MHz low-impedance crystal oscil-
lator input
14
15
Qx
P2/ADC
Port output / ADC input
15
16
P1/I1
Port output / TTL input
16
Wireless Components
3 - 4
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
17
P0/I0
Port output / TTL input
17
18
19
CHGPMP
Charge pump output / loop filter
18
19
TUNE
VCO tuning voltage output
20
21
GNDA
OV-B1
Analog Ground
VHF oscillator amplifier, high-impedance
base input, symmetrical to OV-B2
22
23
24
OV-C2
OV-C1
OV-B2
VHF oscillator amplifier, high-impedance
collector output, symmetrical to OV-C1
VHF oscillator amplifier, high-impedance
collector output, symmetrical to OV-C2
22
23 24
21
VHF oscillator amplifier, high-impedance
base input, symmetrical to OV-B1
Wireless Components
3 - 5
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
25
26
OU-B1
OU-C2
UHF oscillator amplifier, high-impedance
base input, symmetrical to OU-B2
UHF oscillator amplifier, high-impedance
collector output, symmetrical to OU-C1
27
28
OU-C1
OU-B2
UHF oscillator amplifier, high-impedance
collector output, symmetrical to OU-C2
26
27 28
25
UHF oscillator amplifier, high-impedance
base input, symmetrical to OU-B1
Wireless Components
3 - 6
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
3.3 Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Phase-
Det.&
ChgPmp
I/O-PORTS
Oscillator
VHF/HYP
Oscillator UHF
VCO
VCOx
Cy
fref
Progr.
Divider
Isolation
Amplifier
Isolation
Amplifier
Ref.-
Divider
Mixer
VHF
HYP
Mixer
UHF
I2C-Bus
Interface
V/U
Crystal
Oscillator
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 3-2
Block Diagram
Wireless Components
3 - 7
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
3.4 Circuit Description
3.4.1 Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for VHF and/or HYPER and UHF, a reference
voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switch ensures that only one mixer-oscillator block at a time
is activated. In the activated band the signal passes a frontend stage with MOS-
FET amplifier, a double-tuned bandpass filter and is then fed to the balanced
mixer input of the IC which has a low-impedance input.
The input signal is mixed there with the on chip oscillator signal from the acti-
vated oscillator section.
3.4.2 PLL block
The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential
signal at the programmable divider inputs. The signal subsequently passes
through a programmable divider with ratio N = 256 through 32767 and is then
compared in a digital frequency / phase detector to a reference frequency
fref = 62.5 kHz.
This frequency is derived from a balanced, low-impedance 4 MHz crystal oscil-
lator (pin Q, Qx) divided by Q = 64.
The phase detector has two outputs UP and DOWN that drive two current
sources I+ and I- of a charge pump. If the negative edge of the divided VCO sig-
nal appears prior to the negative edge of the reference signal, the I+ current
source pulses for the duration of the phase difference. In the reverse case the
I- current source pulses. If the two signals are in phase, the charge pump output
(CHGPMP) goes into the high-impedance state (PLL is locked). An active low-
pass filter integrates the current pulses to generate the tuning voltage for the
VCO (internal amplifier, external pullup resistor at TUNE and external RC cir-
cuitry). The charge pump output is also switched into the high-impedance state
when the control bit T0 = 1. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of
self-discharge in the peripheral circuity. TUNE may be switched off by the con-
trol bit OS to allow external adjustments.
When the VCO is not working the PLL locks to a tuning voltage of 33V.
By means of control bit 5I the pump current can be switched between two val-
ues by software. This programmability permits alteration of the control response
of the PLL in the locked-in state. In this way different VCO gains can be com-
pensated, for example.
Wireless Components
3 - 8
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
The software-switched ports P0, P1, P2 are general-purpose open-collector
outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 64) and Cy
(divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump cur-
rent pulses is greater than the period of the crystal oscillator (i.e. 250 ns).
Hence, when FL = 1, the maximum deviation of the input frequency from the
programmed frequency is given by
∆f = ± IP (KVCO / fQ) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscilla-
tor frequency and C1, C2 the capacitances in the loop filter (see application cir-
cuit). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of
16 µs for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144 µs for FL to be set after the loop regains lock.
2
3.4.3 I C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table 1 ”bit allocation” should be referred to the following description. All
telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during
which the control logic returns the SDA line to LOW (acknowledge condition).
The first byte is comprised of seven address bits. These are used by the pro-
cessor to select the PLL from several peripheral components (chip select). The
LSB bit (R/W) determines whether data are written into (R/W = 0) or read from
(R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
Wireless Components
3 - 9
Specification, August 1999
TUA 6010XS
preliminary
Functional Description
is released to allow the processor to generate a stop condition. The status word
consists of two bits from the TTL input ports, three bits from the A/D converter,
the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate connection of pin CAS
(see table 2 ”address selection”).
When the supply voltage is applied, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when VVCCD goes below 3.2 V. It will be
reset at the end of a READ operation.
Wireless Components
3 - 10
Specification, August 1999
4
Applications
Contents of this Chapter
4.1 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
TUA 6010XS
preliminary
Applications
4.1 Application Circuit
+33V
4.7n
1k
1k
BB639C
4.7n
4.7n
82p
1k
4.7k
2.2k
2.2k
470p
4.7n
33k
3.3k
BA 592
1k
2.2p
100p
4.7p
4.7p
BB639C
100k
22k
4.7n
4.7n
1.2p
1.2p
1.2p
1.2p
2.7p
2.2p
2.2p
2.7p
22n
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
TUA 6010XS
1
2
3
4
5
6
7
8
9
10
11
12
13
2.2p
22p
47
4MHz
4.7n
1n
1n
22p
18p
4.7n
100p
100p
220
1
6
3
1
3
220
4.7n
1:1 *)
1:1 *)
47p
27p
4
4
6
12p
SCL
SDA
UHF
VHF
V
VVCCD
VCCA CAS
IF output
*) TOKO B4F Type
617DB-1023
Figure 4-1
Evaluation Board
Wireless Components
4 - 2
Specification, August 1999
TUA 6010XS
preliminary
Applications
4.2 Hints
See separate available Application Note TUA 6010XS.
Wireless Components
4 - 3
Specification, August 1999
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
TUA 6010XS
preliminary
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-20°C ... + 80°C
AMB
Parameter
Symbol
Limit Values
Unit
Remarks
min
max
PLL
Supply voltage
VVCCD
-0.3
-0.3
+6
V
CHGPMP
VCHGPMP
ICHGPMP
V
mA
1
Crystal oscillator pins Q, Qx
VQ
IQ
VVCCD
V
mA
-5
Bus input/output SDA
Bus output current SDA
VSDA
-0.3
+6
5
V
mA
ISDA(L)
Bus input SCL
VSCL
VP
-0.3
-0.3
-0.3
-0.3
-1
+6
+13
VVCCD
+35
5
V
Port outputs P0, P1, P2
Chip address switch CAS
VCO tuning output (loop filter)
Bus output SDA
V
VCAS
VTUNE
ISDAL
IP(L)
V
V
mA
mA
mA
°C
°C
K/W
open collector
Port outputs P0, P1, P2
Total port output current
Junction temperature
-1
15
open collector
ΣIP(L)
TJ
20
tmax = 0,1 sec. at 6 V
+125
+125
130
Storage temperature
TStg
-40
Thermal resistance (junction to ambient)
RthSA
Wireless Components
5 - 2
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-20°C ... + 80°C (continued)
AMB
Parameter
Symbol
Limit Values
Unit
Remarks
min
max
Mixer-Oscillator
Supply voltage
VVCCA
-0.3
+6
V
Mix inputs VHF/UHF
VMIX V/U
IMIX V/U
2
6
V
mA
-5
VCO base voltage
VCO collector voltage
IF output
VOU-B/OV-B
VOU-C/OV-C
-0.3
3
VVCCA
6
V
V
V
VIFout
VIFoutx
All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
ESD-Protection*
all pins unless otherwise specified
Mixer inputs MIXU / MIXV
Mixer outputs IFout / IFoutx
Ports
VESD
-1
1
kV
V
VESD MIX
VESD IF
VESD P
VESD CP
-500
-500
-500
-500
500
500
500
500
Pin 1, 2, 3, 4
Pin 7, 8
V
V
Pin 15, 16, 17
Pin 18
Charge pump
V
*according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
5.1.2 Operating Range
Within the operational range the IC operates as described in the circuit
description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
max
+5.5
Supply voltage
VVCCD
VVCCA
+4.5
+4.5
+4.5
V
V
V
Supply voltage
+5.5
+5.5
Mixer output voltage
VIFout
open collector
VIFoutx
Programmable divider factor
N
256
30
32767
500
VHF Mixer input frequency range
fMIXV
MHz
MHz
MHz
MHz
°C
UHF Mixer input frequency range
VHF Oscillator frequency range
UHF Oscillator frequency range
Ambient temperature
fMIXU
fOV
400
30
900
500
900
+80
fOU
400
-20
Tamb
Wireless Components
5 - 3
Specification, August 1999
TUA 6010XS
preliminary
Reference
5.1.3 AC/DC Characteristics
Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V
Symbol
Limit Values
Unit
Test Conditions
L
Item
1.1
min
typ
max
Digital Unit
PLL
Supply current
IVCCD
19
24
29
mA
VVCCD = 5 V
Crystal oscillator connections Q, Qx
Crystal frequency
Crystal resistance
Oscillation frequency
Input impedance
fQ
3.2
10
4.0
4.8
MHz
series resonance
series resonance
fQ = 4 MHz
RQ
fQ
100
Ω
3,99975
-600
20
4,000
-750
4,00025 MHz
ZQ
aH
-900
Ω
fQ = 4 MHz
Margin from 1st
dB
fQ = 4 MHz
(fundamental) to 2nd and
3rd harmonics
Charge pump output CHGPMP
HIGH output current
LOW output current
Tristate current
ICPH
ICPL
ICPZ
VCP
±90
±22
±220
±50
+1
±300
±75
µA
µA
nA
V
5I = 1, VCP = 2 V
5I = 0, VCP = 2 V
T0 = 1, VCP = 2 V
locked
Output voltage
1.0
2.5
Drive output TUNE (open collector)
HIGH output current
LOW output voltage
ITH
10
µA
VTH = 33 V, T0 = 1
ITL = 1.0 mA
VTL
0.5
V
I2C-Bus
1.2
Bus inputs SCL, SDA
HIGH input voltage
VIH
VIL
IIH
3
0
5.5
1.5
10
V
LOW input voltage
HIGH input current
LOW input current
V
µA
µA
VIH = VS
VIL = 0 V
IIL
-10
Bus output SDA (open collector)
HIGH output current
LOW output voltage
IOH
10
µA
VOH = 5.5 V
IOL = 3 mA
VOL
0.4
V
Edge speed SCL,SDA
Rise time
tr
tf
300
300
ns
ns
Fall time
Wireless Components
5 - 4
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V (Continued)
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
400
Clock timing SCL
Frequency
fSCL
tH
0
kHz
HIGH pulse width
LOW pulse width
0.6
1.3
µs
µs
tL
Start condition
Set-up time
tsusta
thsta
0.6
0.6
µs
µs
Hold time
Stop condition
Set up time
tsusto
tbuf
0.6
1.3
µs
µs
Bus free
Data transfer
Set-up time
tsudat
thdat
Vhys
0.1
0
µs
Hold time
µs
Input hysteresis
SCL, SDA (1)
200
mV
Pulse width of spikes
which are suppressed
tsp
CL
0
50
ns
Capacitive load for each
bus line
400
pF
Port outputs P0, P1, P2 (open collector)
HIGH output current
LOW output voltage
IPOH
1
µA
VPOH = 5 V
VPOL
0.5
V
IPOL = 15 mA
TTL port inputs P0, P1
HIGH input voltage
VPIH
VPIL
IPIH
IPIL
2.7
V
LOW input voltage
HIGH input current
LOW input current
0.8
10
V
µA
µA
VPIH = 13.5 V
VPIL = 0 V
-10
-10
-50
ADC port input P2
HIGH input current
IADCH
IADCL
10
50
µA
µA
LOW input current
Address selection input CAS
HIGH input current
LOW input current
ICASH
ICASL
µA
µA
VCASH = 5 V
VCASL = 0 V
Wireless Components
5 - 5
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V (Continued)
Symbol
Limit Values
Unit
Test Conditions
L
Item
2.1
min
typ
max
Analog Unit
Mixer-Oscillator
Current consumption
IVCCA
11
14
4
15
18
6
19
22
8
mA
Bit V/U = Low
Bit V/U = High
IVCCA
mA
mA
kΩ
Mixer current
IIF-V/IF-U
Mixer output impedance
RIFout,IF
outx
20
Parallel equivalent
circuit,
fIF = 38,9 MHz
CIFout,IF
outx
0.5
pF
Parallel equivalent
circuit,
fIF = 38,9 MHz
VHF and Hyper Band Section
2.2
Oscillator frequency
range
fOscV
80
170
450
MHz
MHz
Vd = 0,5..28 V;
VHF
fOscH
140
Vd = 0,5..28 V;
HYP
Oscillator drift
∆fOscV
∆fOscV
∆fOscV
400
500
100
kHz
kHz
kHz
VS = 5 V±10%
∆T = 25 °C
t = 5 s up to 15 min
after switching on
Oscillator pulling
VMIXV
VMIXV
VMIXV
100
100
80
108
108
88
dBµV
dBµV
dBµV
∆f = 10 kHz in
channel E2
∆f = 10 kHz in
channel S10
∆fint = E2 + N + 5 -
1 MHz
VMIXV
80
88
dBµV
∆fint = S10 + N + 5 -
1 MHz
Oscillator phase noise
L(fm)VH
F
-80
11
-86
dBc/
Hz
fm = 10 kHz,
application circuit
Mixer gain
GMixV
FMixV
FMixV
VMixV
14
5
17
8
dB
dB
dB
Mixer noise figure
Channel E2 (DSB)
Channel 10 (DSB)
5
8
Crosstalk fin/LO
150
1000
mVrms max. input level for
10 dB distance
fin/LO
Wireless Components
5 - 6
Specification, August 1999
TUA 6010XS
preliminary
Reference
Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V (Continued)
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
20
max
Mixer input impedance
RMixV
W
serial equivalent
circuit,
f
MixV = 300 MHz
LMixV
10
20
nH
serial equivalent
circuit,
f
MixV = 300 MHz
IF suppression
aIF
dB
VMixB = 80 dBµV
UHF Section
2.3
Oscillator frequency
range
fOscU
440
900
MHz
Vt = 0,5...28 V
Oscillator drift
∆fOscU
∆fOscU
∆fOscU
400
800
100
kHz
kHz
kHz
VS = 5 V±10%
∆T = 25 °C
t = 5 s up to 15 min
after switching on
Oscillator pulling
VMIXU
VMIXU
VMIXU
100
100
80
108
108
88
dBµV
dBµV
dBµV
∆f = 10 kHz in
channel E21
∆f = 10 kHz in
channel E68
∆fint = E21 + N + 5 -
1 MHz
VMIXU
80
88
dBµV
∆fint = E68 + N + 5 -
1 MHz
Oscillator phase noise
L(fm)UH
F
-80
11
-86
dBc/
Hz
fm = 10 kHz,
application circuit
Mixer gain
GMixU
FMixU
14
6
17
9
dB
dB
Mixer noise figure
Channel E21
(DSB)
7
10
dB
Channel E68
(DSB)
Crosstalk fin/LO
VMixU
RMixU
LMixU
aIF
150
1000
mVrms max. input level for
10 dB distance
fin/LO
Mixer input impedance
20
10
20
W
serial equivalent
circuit,
fMixU = 600 MHz
nH
dB
serial equivalent
circuit,
fMixU = 600 MHz
IF suppression
VMixB = 80 dBµV
■ This value is only guaranteed in lab.
Wireless Components
5 - 7
Specification, August 1999
TUA 6010XS
preliminary
Reference
5.2 Bit Allocation Read / Write
Table 5-4
Byte
MSB*) bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
Ack
Remarks
Write Data
Address Byte
Progr. Divider Byte 1
Progr. Divider Byte 2
Control Byte 1
Control Byte 2
Read Data
1
0
1
n14
n6
5I
0
n13
n5
T1
x
0
n12
n4
T0
x
0
n11
n3
1
MA1
n10
n2
MA0
n9
n1
1
0
A
A
A
A
A
n8
n0
OS
P0
n7
1
1
V/U
x
x
P2
P1
Address Byte
Status Byte
1
1
0
x
0
0
MA1
A2
MA0
A1
1
A
A
POR
FL
I1
I0
A0
*) MSB shifted first.
Divider ratio:
N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512
x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2
+ 2 x n1 + n0
Control Bytes:
■ Ports P0, P1, P2:
P0...P2=1
P0...P2=0
open-collector output is active
open-collector output is inactive, TTL-inputs I1, I0 and
ADC available
■ Bandswitch V/U:
V/U=1
V/U=0
switch to OSC/MIX UHF
switch to OSC/MIX VHF
■ Pump current 5I:
5I=1
5I=0
high PD output current
low PD output current
■ Disabling tuning voltage OS:
OS=1
OS=0
disables TUNE
enables TUNE
Wireless Components
5 - 8
Specification, August 1999
TUA 6010XS
preliminary
Reference
Status Byte:
■ Power On Reset flag POR:
flag is set at power-on and reset at the end of READ operation
■ PLL lock flag FL:
flag is set to 1 when loop is locked
■ TTL-inputs I1, I0:
input data from pins P1/I1, P0/I0
■ ADC bits A2,A1,A0:
digital outputs of the 5-level ADC
Table 5-5 Address Selection
Voltage at CAS
MA1
MA0
(0...0.1) * VVCC
0
0
open circuit
0
1
1
0
(0.4...0.6) * VVCC
(0.9...1) * VVCC
1
1
Table 5-6 Test Modes
Test mode
T1
0
T0
0
Normal operation
P1 = Cy output, P0 = fref output
1
0
Charge pump output, CHGPMP is in high-impedance state
TTL-inputs I1/I0 are Cy/fref inputs of phase detector
0
1
1
1
Table 5-7 A/D Converter Levels
Voltage at P2 / ADC
A2
0
A1
0
A0
0
(0...0.15) * VVCC
(0.15...0.3) * VVCC
(0.3...0.45) * VVCC
(0.45...0.6) * VVCC
(0.6...1) * VVCC
0
0
1
0
1
0
0
1
1
1
0
0
Wireless Components
5 - 9
Specification, August 1999
TUA 6010XS
preliminary
Reference
2
5.3 I C Bus Timing Diagram
Wireless Components
5 - 10
Specification, August 1999
TUA 6010XS
preliminary
Reference
5.4 Test Circuits
+33V
1n
33k
33k
BB639C
4.7n
470n
82p
1k
33k
33k
470p
1n
1k
100p
3.3k
BB639C
BA 592
39k
1k
2.2p
100p
4.7p
1.2p
5.6p
12k
10n
56n
100k
1.2p
1.2p
1.2p
2.2p
2.2p
2.2p
2.2p
28
27
26
25
24
23
22
21
20
19
18
17
12
16
13
15
14
TUA 6010XS
1
2
3
4
5
6
7
8
9
10
11
22p
22p
22p
22p
1n
1n
10
18p
100p
100
2
1
4
2
1
4
4.7n
SMT4
1:1
SMT4
1:1
100
470n
33p
5
5
1n
IF output
SCL
SDA
UHF
VHF
V
VVCCD
VCCA CAS
Figure 5-1
DC and RF Parameter Measurement
Wireless Components
5 - 11
Specification, August 1999
TUA 6010XS
preliminary
Reference
Test mode:
T1 = HIGH
T0 = LOW
VVCC
IVCC
5V
5 k
fref
5 k
fcy
Q
fQ = fref * 64
Counter
Counter
P0
P1
18 pF
TUA
6010XS
fVCO = fcy * N
N: divider ratio
4 MHz
GNDD
Figure 5-2
Measurement of Crystal Oscillator Frequency
Wireless Components
5 - 12
Specification, August 1999
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