IRFH7110PBF_15 [INFINEON]
Secondary Side Synchronous Rectification;型号: | IRFH7110PBF_15 |
厂家: | Infineon |
描述: | Secondary Side Synchronous Rectification |
文件: | 总9页 (文件大小:276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IRFH7110PbF
HEXFET® Power MOSFET
VDS
Vgs max
100
V
V
± 20
RDS(on) max
(@VGS = 10V)
13.5
m
Ω
58
nC
QG (typical)
RG (typical)
0.6
Ω
PQFN 5X6 mm
ID
50
A
(@Tc(Bottom) = 25°C)
Applications
• Secondary Side Synchronous Rectification
• Inverters for DC Motors
• DC-DC Brick Applications
• Boost Converters
FeaturesandBenefits
Features
Benefits
Low RDSon (< 13.5mW)
Low Thermal Resistance to PCB (< 1.2°C/W)
Low Profile (<0.9 mm)
Lower Conduction Losses
Enables better thermal dissipation
results in Increased Power Density
Industry-Standard Pinout
⇒
Multi-Vendor Compatibility
Compatible with Existing Surface Mount Techniques
RoHS Compliant Containing no Lead, no Bromide and no Halogen
MSL1, Industrial Qualification
Easier Manufacturing
Environmentally Friendlier
Increased Reliability
Standard Pack
Form
Orderable part number
Package Type
Note
Quantity
4000
IRFH7110TRPBF
IRFH7110TR2PBF
PQFN 5mm x 6mm
PQFN 5mm x 6mm
Tape and Reel
Tape and Reel
400
EOL notice # 259
Absolute Maximum Ratings
Max.
100
± 20
11
Parameter
Units
VDS
Drain-to-Source Voltage
Gate-to-Source Voltage
V
V
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
I
I
I
I
I
I
@ TA = 25°C
D
D
D
D
D
@ TA = 70°C
8.6
58
@ TC(Bottom) = 25°C
@ TC(Bottom) = 100°C
@ TC = 25°C
A
37
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
50
240
3.6
104
DM
Power Dissipation
P
P
@TA = 25°C
D
D
W
Power Dissipation
@TC(Bottom) = 25°C
Linear Derating Factor
Operating Junction and
Storage Temperature Range
0.029
-55 to + 150
W/°C
°C
T
T
J
STG
Notes through are on page 9
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IRFH7110PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250μA
BVDSS
ΔΒ
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
100
–––
–––
2.0
–––
0.09
10.6
3.0
–––
–––
13.5
4.0
V
Δ
VDSS/ TJ
V/°C Reference to 25°C, ID = 1.0mA
Ω
m
RDS(on)
VGS(th)
VGS = 10V, ID = 35A
V
VDS = VGS, ID = 100μA
ΔVGS(th)
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
74
-9.0
–––
–––
–––
–––
–––
58
––– mV/°C
IDSS
20
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
VGS = 20V
μA
250
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
100
nA
-100
V
V
GS = -20V
gfs
–––
87
S
DS = 50V, ID = 35A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
11
–––
–––
–––
–––
–––
–––
VDS = 50V
GS = 10V
ID = 35A
3.6
V
nC
16
Gate Charge Overdrive
27.4
19.6
17
Switch Charge (Qgs2 + Qgd
Output Charge
)
nC VDS = 16V, VGS = 0V
Gate Resistance
0.6
Ω
–––
–––
–––
–––
–––
–––
–––
–––
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
–––
–––
11
23
V
DD = 50V, VGS = 10V
I
D = 35A
ns
Ω
RG=1.8
Turn-Off Delay Time
Fall Time
22
18
3240
300
140
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
V
V
GS = 0V
pF
DS = 25V
Reverse Transfer Capacitance
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Typ.
–––
–––
Max.
Units
mJ
Single Pulse Avalanche Energy
Avalanche Current
EAS
IAR
110
35
A
Diode Characteristics
Parameter
Continuous Source Current
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
S
IS
–––
–––
50
(Body Diode)
showing the
A
G
ISM
Pulsed Source Current
integral reverse
–––
–––
240
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
–––
–––
–––
–––
27
1.3
41
V
T
T
= 25°C, I = 35A, V
= 0V
GS
J
J
S
ns
= 25°C, I = 35A, VDD = 50V
F
Qrr
ton
Reverse Recovery Charge
Forward Turn-On Time
140
210
nC di/dt = 500A/μs
Time is dominated by parasitic Inductance
Thermal Resistance
Parameter
Typ.
–––
–––
–––
–––
Max.
1.2
32
Units
Junction-to-Case
RθJC (Bottom)
RθJC (Top)
RθJA
Junction-to-Case
°C/W
Junction-to-Ambient
Junction-to-Ambient
35
RθJA (<10s)
22
2
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IRFH7110PbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
6.0V
5.5V
5.0V
4.8V
4.5V
4.3V
4.0V
6.0V
5.5V
5.0V
4.8V
4.5V
4.3V
4.0V
BOTTOM
BOTTOM
4.0V
1
4.0V
≤ 60μs PULSE WIDTH
Tj = 25°C
≤ 60μs PULSE WIDTH
Tj = 150°C
0.1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
I
= 35A
D
V
= 10V
GS
100
T
= 150°C
J
10
1
T
V
= 25°C
= 50V
J
DS
≤
60μs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
T
0
20 40 60 80 100 120 140 160
V
, Gate-to-Source Voltage (V)
GS
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
16
V
C
= 0V,
f = 1 MHZ
GS
I = 35A
D
= C + C , C SHORTED
iss
gs
gd ds
C
= C
V
V
V
= 80V
= 50V
= 20V
rss
gd
DS
DS
DS
C
= C + C
ds
12
8
10000
1000
100
oss
gd
Ciss
Coss
Crss
4
0
10
0
20
40
60
80
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
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IRFH7110PbF
1000
100
10
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100μsec
T
= 150°C
J
1msec
imited by Package
L
DC
10
T
= 25°C
V
1
J
1
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
= 0V
GS
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
0.1
1
100
1000
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4.5
60
LIMITED BY PACKAGE
50
40
30
20
10
0
4.0
3.5
3.0
2.5
2.0
1.5
I
I
I
I
= 100μA
= 250μA
= 1.0mA
= 1.0A
D
D
D
D
25
50
75
100
125
150
-75 -50 -25
0
25
50
75 100 125 150
T , Case Temperature (°C)
C
T
, Temperature ( °C )
J
Fig 9. Maximum Drain Current vs.
Fig 10. Threshold Voltage vs. Temperature
Case(Bottom)Temperature
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
Notes:
SINGLE PULSE
( THERMAL RESPONSE )
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom)
4
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IRFH7110PbF
40
30
20
10
0
500
400
300
200
100
0
I
= 35A
I
D
D
TOP
4.7A
9.6A
BOTTOM 35A
T
T
= 125°C
J
= 25°C
16
J
4
8
12
20
25
50
75
100
125
150
V
, Gate-to-Source Voltage (V)
GS
Starting T , Junction Temperature (°C)
J
Fig 13. Maximum Avalanche Energy vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
V
(BR)DSS
t
p
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
I
AS
20V
Ω
0.01
t
p
Fig 14b. Unclamped Inductive Waveforms
Fig 14a. Unclamped Inductive Test Circuit
RD
VDS
VDS
90%
VGS
D.U.T.
RG
+VDD
-
10%
VGS
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1
td(on)
td(off)
tr
tf
Fig 15a. Switching Time Test Circuit
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Fig 15b. Switching Time Waveforms
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IRFH7110PbF
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 18. Gate Charge Waveform
Fig 17. Gate Charge Test Circuit
6
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IRFH7110PbF
PQFN 5x6 Outline "E" Package Details
PQFN 5x6 Outline "G" Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application note AN-1136:
http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
7
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IRFH7110PbF
PQFN 5x6 Outline Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
PART NUMBER
XXXX
XYWWX
(“4 or 5 digits”)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
MARKING CODE
(Per Marking Spec)
XXXXX
PIN 1
IDENTIFIER
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
PQFN 5x6 Outline Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
DESCRIPTION
Ao
Bo
Ko
W
Dimens ion des ign to accommodate the component width
Dimens ion des ign to accommodate the component lenght
Dimens ion des ign to accommodate the component thicknes s
Overall width of the carrier tape
P
1
Pitch between s ucces s ive cavi ty centers
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Note: All dimens ion are nominal
Package
Type
Reel
Diameter
(Inch)
QT Y
Reel
Width
W1
Ao
Bo
Ko
P1
W
Pin 1
(mm)
(mm)
(mm)
(mm)
(mm)
Quadrant
(mm)
5 X 6 PQFN
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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IRFH7110PbF
Qualification information†
Industrial††
(per JEDEC JESD47F ††† guidelines )
Qualification level
MS L 1
Moisture Sensitivity Level
RoHS compliant
PQFN 5mm x 6mm
(per JEDEC J-ST D-020D†††
Yes
)
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
Applicable version of JEDEC standard at the time of product release.
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.174mH, RG = 50Ω, IAS = 35A.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
R is measured at TJ of approximately 90°C.
θ
ꢀ When mounted on 1 inch square 2 oz copper pad on 1.5x1.5 in. board of FR-4 material.
Calculated continuous current based on maximum allowable junction temperature.
Package is limited to 50A by die-source to lead-frame bonding technology
Revision History
Date
Comment
Updated ordering information to reflect the End-Of-life (EOL) of the mini-reel option (EOL notice #259)
Updated Package outline on page 7.
•
•
•
5/13/2014
Updated Tape and Reel on page 8.
•
•
•
•
•
Updated data sheet based on corporate template.
Corrected typo test condition for GFS from "25V" to "50V" on page 2.
Updated package outline for “option E” and added package outline for “option G” on page 7
Updated "IFX" logo on page 1 & 9.
6/2/2015
Updated tape and reel on page 8.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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