ICE3BS03LJGXT [INFINEON]
Switching Controller, Current-mode, 73.7kHz Switching Freq-Max, BICMOS, PDSO8, ROHS COMPLIANT, PLASTIC, SOP-8;
| 型号： | ICE3BS03LJGXT |
| 厂家： | 
Infineon |
| 描述： | Switching Controller, Current-mode, 73.7kHz Switching Freq-Max, BICMOS, PDSO8, ROHS COMPLIANT, PLASTIC, SOP-8 电池 开关 控制器 |
| 文件： | 总25页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Version 2.0, 6 Dec 2007
F3 PWM controller
ICE3BS03LJG
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell ( Latched and
frequency jitter Mode )
Power Management & Supply
N e v e r s t o p t h i n k i n g .
F3 PWM controller
ICE3BS03LJG
Revision History:
2007-12-6
Datasheet
Previous Version: 1.0
Page
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com
Edition 2007-12-6
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2007 Infineon Technologies AG.
All Rights Reserved.
Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
F3 PWM controller
ICE3BS03LJG
Off-Line SMPS Current Mode Controller with
integrated 500V Startup Cell ( Latched and
frequency jitter Mode )
Product Highlights
•
•
•
Active Burst Mode to reach the lowest Standby Power
Requirements < 100mW
PG-DSO-8
Built-in latched Off protection Mode and external latch enable
function to increase robustness of the system
Built-in and extendable blanking Window for high load jumps to
increase system reliability
•
•
Frequency jitter for low EMI
Pb-free lead plating; RoHS compilant
Features
Description
•
•
•
•
•
500V Startup Cell switched off after Start Up
The ICE3BS03LJG is the latest version of the F3 controller
for lowest standby power and low EMI features with both
auto-restart and latch off protection features to enhance
the system robustness. It targets for off-Line battery
adapters, and low cost SMPS for low to medium power
range such as application for the DVD R/W, DVD Combi,
Active Burst Mode for lowest Standby Power
Fast load jump response in Active Burst Mode
65kHz internally fixed switching frequency
Built-in Latched Off Protection Mode for
Overtemperature, Overvoltage & Short Winding
•
Auto Restart Protection Mode for Overload, Open Blue Ray DVD player and recorder, set top box, charger,
Loop & VCC Undervoltage
Built-in Soft Start
note book adapter, etc. The inherited outstanding features
includes 500V startup cell, active burst mode (achieve the
•
•
Built-in blanking window with extendable blanking lowest standby power; i.e. <100mV at no load with
time for short duration high current
External latch off enable function
Max Duty Cycle 75%
Vin=270Vac) and propagation delay compensation
(accurate output power limit for wide range input),
modulated gate drive (low EMI), etc. The newly added
technology and features can further enhance the features.
It includes BiCMOS technology (further lower power
consumption and extend Vcc operating range to 26V),
•
•
•
•
•
•
Overall tolerance of Current Limiting < ±5%
Internal PWM Leading Edge Blanking
BiCMOS technology provide wide VCC range
Frequency jitter and soft gate driving for low EMI frequency jittering feature (low EMI), built-in soft start,
built-in blanking window with extendable blanking time for
high load jump, external latch off enable pin (feasible for
extra protection), etc. Therefore, ICE3BS03LJG is a
versatile PWM controller for low to medium power
application.
Typical Application
+
CBulk
Converter
Snubber
DC Output
85 -- 270 VAC
-
CVCC
HV
Startup Cell
VCC
PWM Controller
Current Mode
Gate
CS
Precise Low
Tolerance Peak
Current Limitation
Power
Management
RSense
Control Unit
Active Burst Mode
Latch off Mode
FB
GND
BL
Auto Restart Mode
ICE3BS03LJ ( Latch & Jitter )
Type
Marking
Package
FOSC
ICE3BS03LJG
3BS3LJ
PG-DSO-8
65kHz
Version 2.0
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F3 PWM controller
ICE3BS03LJG
Table of Contents
Page
1
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration with PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
1.2
2
Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PWM-Latch FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.2.1
3.7.2.2
3.7.2.3
3.7.3
3.7.3.1
3.7.3.2
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
5
6
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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ICE3BS03LJG
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1
Pin Configuration with PG-DSO-8
1.2
Pin Functionality
BL (extended Blanking and Latch off enable)
The BL pin combines the functions of extendable
blanking time for entering the Auto Restart Protection
Mode and the external latch off enable. The extendable
blanking time function is to extend the built-in 20ms
blanking time by adding an external capacitor at BL to
ground. The external latch off enable function is an
external access to latch off the IC. It is triggered by
pulling down the BL pin to less than 0.25V.
Pin
Symbol Function
1
BL
extended Blanking and Latch off
enable
2
3
4
5
6
7
8
FB
CS
Feedback
Current Sense
Gate
HV
Gate driver output
High Voltage input
Not Connected
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FB-
Signal is the only control in case of light load at the
Active Burst Mode.
n.c.
VCC
GND
Controller Supply Voltage
Controller Ground
CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
Power MOSFET. If CS reaches the internal threshold
of the Current Limit Comparator, the Driver output is
immediately switched off. Furthermore, this current
information can be used to realize the Current Mode
operation through the PWM-Comparator where it
compares with FB signal.
Package PG-DSO-8
BL
1
8
7
6
5
GND
VCC
N.C.
Gate
FB
2
The Gate pin is the output of the internal driver stage
connected to the Gate of an external power MOSFET.
CS
3
4
HV (High Voltage)
The high voltage Pin is connected to the rectified DC
input voltage. It is the input for the integrated 500V
Startup cell.
Gate
HV
VCC (Power supply)
The VCC pin is the positive supply of the IC. The
operating range is between 10.5V and 26V.
Figure 1
Pin Configuration PG-DSO-8(top view)
GND (Ground)
The GND pin is the ground of the controller.
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ICE3BS03LJG
Representative Blockdiagram
2
Representative Blockdiagram
Figure 2
Representative Blockdiagram
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F3 PWM controller
ICE3BS03LJG
Functional Description
3
Functional Description
All values which are used in the functional description components are necessary to adjust the blanking
are typical values. For calculating the worst cases the window.
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
In order to increase the robustness and safety of the
system, the IC provides 2 levels of protection modes:
Latched Off Mode and Auto Restart Mode. The
Latched Off Mode is only entered under dangerous
conditions which can damage the SMPS if not switched
off immediately. A restart of the system can only be
done by recycling the AC line. In addition, for this
enhanced version, there is an external Latch Enable
function provided to increase the flexibility in protection.
When the BL pin is pulled down to less than 0.25V, the
Latch Off Mode is triggered.
The Auto Restart Mode reduces the average power
conversion to a minimum under unsafe operating
conditions. This is necessary for a prolonged fault
condition which could otherwise lead to a destruction of
the SMPS over time. Once the malfunction is removed,
normal operation is automatically retained after the
next Start Up Phase.
The internal precise peak current control reduces the
costs for the transformer and the secondary diode. The
influence of the change in the input voltage on the
maximum power limitation can be avoided together
with the integrated Propagation Delay Compensation.
Therefore the maximum power is nearly independent
on the input voltage, which is required for wide range
SMPS. Thus there is no need for the over-sizing of the
SMPS, e.g. the transformer and the output diode.
3.1
Introduction
ICE3BS03LJG is an enhanced version of the F3 PWM
controller (ICE3xS02) for the low to medium power
application. The particular enhanced features are the
built-in features for soft start, blanking window and
frequency jitter. It also provides the flexibility to
increase the blanking window by simply adding
capacitor in BL pin. To increase the robustness and
flexibility of the protection feature, an external latch-off
enable feature is added. Moreover, the proven
outstanding features in F3 PWM controller are still
remained such as the active burst mode, propagation
delay compensation, modulated gate drive, protection
for Vcc overvoltage, over temperature, over load, open
loop, etc.
The intelligent Active Burst Mode at Standby Mode can
effective obtain the lowest Standby Power at minimum
load and no load conditions. After entering this burst
mode, there is still a full control of the power conversion
by the secondary side via the same optocoupler that is
used for the normal PWM control. The response on
load jumps is optimized. The voltage ripple on Vout is
minimized. Vout is on well controlled in this mode.
The usual externally connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore, a high voltage Startup Cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 18V is exceeded. The external
startup resistor is no longer necessary as this Startup
Cell can directly connected to the input bulk capacitor.
Power losses are therefore reduced. This increases the
efficiency under light load conditions drastically.
Adopting the BiCMOS technology, it can further
decrease the power consumption and provide a even
better standby input power. Besides, it also increases
the design flexibility as the Vcc voltage range is
extended to 26V.
Furthermore, this enhanced version implements the
frequency jitter mode to the switching clock and
modulated gate drive signal at the Gate pin such that
the EMI noise will be effectively reduced.
3.2
Power Management
The Undervoltage Lockout monitors the external
supply voltage VVCC. When the SMPS is plugged to the
main line, the internal Startup Cell is biased and starts
to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current is
controlled to 0.9mA by the Startup Cell. When the VVCC
exceeds the on-threshold VCCon=18V, the bias circuit
The built-in soft start time at 20ms can provide are switched on. Then the Startup Cell is switched off
sufficient timing to reduce the over-stress at power by the Undervoltage Lockout and therefore no power
MOSFET and the output rectifier during startup.
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place after
Active Mode was entered and VVCC falls below 10.5V.
The maximum current consumption before the
controller is activated is about 250µA.
There are 2 modes of blanking time for high load
jumps; the basic mode and the extendable mode. The
blanking time for the basic mode is set at 20ms while
the extendable mode will increase the blanking time at
basic mode by adding external capacitor at the BL pin.
During this time window the overload detection is
disabled. With this concept no further external When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit switched off and the soft start counter is
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F3 PWM controller
ICE3BS03LJG
Functional Description
reset. Thus it is ensured that at every startup cycle the
soft start starts at zero.
3.3
Improved Current Mode
Soft-Start Comparator
HV
VCC
Startup Cell
PWM-Latch
FB
R
Q
C8
Driver
S
Q
Power Management
0.6V
Undervoltage Lockout
18V
Internal Bias
10.5V
Latched Off Mode
Reset
PWM OP
x3.2
VVCC < 6.23V
5.0V
Voltage
Power-Down Reset
CS
Reference
Improved
Current Mode
Auto Restart
Mode
Soft Start block
Active Burst
Mode
Figure 4
Current Mode
Current Mode means the duty cycle is controlled by the
slope of the primary current. This is done by comparing
the FB signal with the amplified current sense signal.
Latched Off
Mode
Figure 3
Power Management
Amplified Current Signal
FB
The internal bias circuit is switched off if Latched Off
Mode or Auto Restart Mode is entered. The current
consumption is then reduced to 250µA.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line. In case
Latched Off Mode is entered, VCC needs to be
dropped below 6.23V to reset the Latched Off Mode.
This is done usually by re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 450µA.
0.6V
Driver
t
t
Ton
Figure 5
Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal, the on-time Ton of the driver is finished by
resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
resistor RSense inserted in the source of the external
power MOSFET. By means of Current Mode
regulation, the secondary output voltage is insensitive
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ICE3BS03LJG
Functional Description
to the line variations. The current waveform slope will
change with the line variation, which controls the duty
cycle.
The external RSense allows an individual adjustment of
the maximum source current of the external power
MOSFET.
VOSC
max.
Duty Cycle
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted VOSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
threshold.
t
Voltage Ramp
0.6V
FB
t
Gate Driver
156ns time delay
t
Figure 7
Light Load Conditions
Soft-Start Comparator
PWM Comparator
3.3.1
PWM-OP
FB
The input of the PWM-OP is applied over the internal
C8
leading edge blanking to the external sense resistor
R
Sense connected to pin CS. RSense converts the source
PWM-Latch
Oscillator
current into a sense voltage. The sense voltage is
amplified with a gain of 3.2 by PWM OP. The output of
the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
VOSC
time delay
circuit (156ns)
Gate Driver
0.6V
10kΩ
3.3.2
PWM-Comparator
X3.2
The PWM-Comparator compares the sensed current
signal of the external power MOSFET with the
feedback signal VFB (see Figure 8). VFB is created by an
external optocoupler or external transistor in
combination with the internal pull-up resistor RFB and
provides the load information of the feedback circuitry.
When the amplified current signal of the external power
MOSFET exceeds the signal VFB the PWM-
Comparator switches off the Gate Driver.
R1
T2
V1
PWM OP
C1
Voltage Ramp
Figure 6
Improved Current Mode
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ICE3BS03LJG
Functional Description
is a built-in function and it is controlled by an internal
counter.
5V
Soft-Start Comparator
RFB
FB
PWM-Latch
C8
PWM Comparator
0.6V
VSoftS
Optocoupler
PWM OP
CS
VSoftS2
VSoftS1
X3.2
Improved
Current Mode
Figure 10
Soft Start Phase
Figure 8
PWM Controlling
When the VVCC exceeds the on-threshold voltage, the
IC starts the Soft Start mode (see Figure 10).
3.4
Startup Phase
The function is realized by an internal Soft Start
resistor, an current sink and a counter. And the
amplitude of the current sink is controlled by the
counter (see Figure 11).
Soft S tart counter
5V
SoftS
Soft Start
RSoftS
SoftS
Soft Start
Soft-Start
C om parator
G ate D river
C 7
&
G 7
32I
4I
8I
2I
I
Soft Start
Counter
0.6V
C S
x3.2
PW M O P
Figure 11
Soft Start Circuit
After the IC is switched on, the VSFOFTS voltage is
controlled such that the voltage is increased step-
wisely (32 steps) with the increase of the counts. The
Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
Figure 9
Soft Start
In the Startup Phase, the IC provides a Soft Start
period to control the maximum primary current by
means of a duty cycle limitation. The Soft Start function
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F3 PWM controller
ICE3BS03LJG
Functional Description
decrease gradually and the duty ratio of the gate drive In addition to Start-Up, Soft-Start is also activated at
increases gradually. The Soft Start will be finished in each restart attempt during Auto Restart.
20ms (TSoft-Start) after the IC is switched on. At the end
of the Soft Start period, the current sink is switched off.
The Start-Up time TStart-Up before the converter output
voltage VOUT is settled, must be shorter than the Soft-
Start Phase TSoft-Start (see Figure 13).
By means of Soft-Start there is an effective
minimization of current and voltage stresses on the
external power MOSFET, the clamp circuit and the
output overshoot and it helps to prevent saturation of
the transformer during Start-Up.
VSoftS
TSoft-Start
VSOFTS32
3.5
PWM Section
0.75
PWM Section
t
Oscillator
Gate
Driver
Duty Cycle
max
Clock
Frequency
Jitter
t
Figure 12 Gate drive signal under Soft-Start Phase
Within the soft start period, the duty cycle is increasing
from zero to maximum gradually (see Figure 12).
Soft Start
Block
FF1
Q
Gate Driver
&
S
R
Soft Start
1
VSoftS
Comparator
G8
PWM
G9
TSoft-Start
Comparator
VSOFTS32
Current
Limiting
Gate
VFB
t
t
Figure 14
PWM Section Block
4.0V
3.5.1
Oscillator
The oscillator generates a fixed frequency of 65KHz
with frequency jittering of ±4% (which is ±2.6KHz) at a
jittering period of 4ms.
A capacitor, a current source and a current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.75.
VOUT
VOUT
TStart-Up
t
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Figure 13
Start Up Phase
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ICE3BS03LJG
Functional Description
Start block. Then the switching frequency is varied in Thus the leading switch on spike is minimized.
range of 65KHz ± 2.6KHz at period of 4ms.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold VVCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.5.2
PWM-Latch FF
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the external
power MOSFET. After the PWM-Latch is set, it is reset
by the PWM comparator, the Soft Start comparator or
the Current -Limit comparator. When it is in reset mode,
the output of the gate driver is shut down immediately.
3.6
Current Limiting
PWM Latch
Latched Off
Mode
3.5.3
Gate Driver
FF1
Current Limiting
Spike
Blanking
190ns
1.66V
VCC
C11
PWM-Latch
Over Power Protection
OPP
1
Gate
Vcsth
Leading
C10
C12
Edge
Blanking
220ns
PWM-OP
&
G10
0.25V
Gate Driver
Figure 15
Gate Driver
1pF
10k
Active Burst
Mode
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external power
MOSFET threshold. This is achieved by a slope control
of the rising edge at the gate driver’s output (see Figure
16).
D1
CS
Figure 17
Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the external power MOSFET is
sensed via an external sense resistor RSense. By means
of RSense the source current is transformed to a sense
voltage VSense which is fed into the pin CS. If the voltage
ca. t = 130ns
V
Sense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
5V
A Propagation Delay Compensation is added to
support the immediate shut down of the external power
MOSFET with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
t
Figure 16
Gate Rising Slope
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
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ICE3BS03LJG
Functional Description
Blanking is integrated in the current sense path for the induced to the delay, which depends on the ratio of dI/
comparators C10, C12 and the PWM-OP.
dt of the peak current (see Figure 19).
The output of comparator C12 is activated by the AND The overshoot of Signal2 is larger than of Signal1 due
Gate G10 if Active Burst Mode is entered. When it is to the steeper rising waveform. This change in the
activated, the current limiting is reduced to 0.25V. This slope is depending on the AC input voltage.
voltage level determines the maximum power level in Propagation Delay Compensation is integrated to
Active Burst Mode.
reduce the overshoot due to dI/dt of the rising primary
current. Thus the propagation delay time between
exceeding the current sense threshold Vcsth and the
switching off of the external power MOSFET is
compensated over temperature within a wide range.
Current Limiting is then very accurate.
Furthermore, the comparator C11 is implemented to
detect dangerous current levels which could occur if
there is a short winding in the transformer or the
secondary diode is shorten. To ensure that there is no
accidentally entering of the Latched Mode by the
comparator C11, a 190ns spike blanking time is For example, Ipeak = 0.5A with RSense = 2. The current
integrated in the output path of comparator C11.
sense threshold is set to a static voltage level Vcsth=1V
without Propagation Delay Compensation. A current
ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a
propagation delay time of tPropagation Delay =180ns leads
to an Ipeak overshoot of 14.4%. With the propagation
delay compensation, the overshoot is only around 2%
(see Figure 20).
3.6.1
VSense
Leading Edge Blanking
Vcsth
tLEB = 220ns
with compensation
without compensation
V
1,3
1,25
1,2
t
1,15
1,1
Figure 18
Leading Edge Blanking
1,05
1
Whenever the power MOSFET is switched on, a
leading edge spike is generated due to the primary-
side capacitances and reverse recovery time of the
secondary-side rectifier. This spike can cause the gate
drive to switch off unintentionally. In order to avoid a
premature termination of the switching pulse, this spike
is blanked out with a time constant of tLEB = 220ns.
0,95
0,9
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
V
dVSense
dt
µs
Figure 20
Overcurrent Shutdown
3.6.2
Propagation Delay Compensation
Signal2 Signal1
VOSC
max. Duty Cycle
ISense
tPropagation Delay
IOvershoot2
Ipeak2
Ipeak1
ILimit
off time
VSense
t
Propagation Delay
IOvershoot1
Vcsth
t
Signal1
Signal2
Figure 19
Current Limiting
t
In case of overcurrent detection, there is always
propagation delay to switch off the external power
MOSFET. An overshoot of the peak current Ipeak is
Figure 21
Dynamic Voltage Threshold Vcsth
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Functional Description
The Propagation Delay Compensation is realized by blanking time is passed, the switch S1 is opened by
means of a dynamic threshold voltage Vcsth (see Figure G2. Then the 0.9V clamped voltage at BL pin is
21). In case of a steeper slope the switch off of the charged to 4.0V through the internal IBK constant
driver is earlier to compensate the delay.
current. Then G5 is enabled by comparator C3. After
the 30us spike blanking time, the Auto Restart Mode is
activated.
3.7
Control Unit
For example, if CBK = 0.22uF, IBK = 13uA
The Control Unit contains the functions for Active Burst
Mode, Auto Restart Mode and Latched Off Mode. The
Active Burst Mode and the Auto Restart Mode both
have 20ms internal Blanking Time. For the Auto
Restart Mode, a further extendable Blanking Time is
achieved by adding external capacitor at BL pin. By
means of this Blanking Time, the IC avoids entering
into these two modes accidentally. Furthermore those
buffer time for the overload detection is very useful for
the application that works in low current but requires a
short duration of high current occasionally.
Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 72ms
The 20ms blanking time circuit after C4 is disabled by
the soft stat block such that the controller can start up
properly.
The Active Burst Mode has basic blanking mode only
while the Auto Restart Mode has both the basic and the
extendable blanking mode.
3.7.2
Active Burst Mode
The IC enters Active Burst Mode under low load
conditions. With the Active Burst Mode, the efficiency
increases significantly at light load conditions while still
maintaining a low ripple on VOUT and a fast response on
load jumps. During Active Burst Mode, the IC is
controlled by the FB signal. Since the IC is always
active, it can be a very fast response to the quick
change at the FB signal. The Start up Cell is kept OFF
in order to minimize the power loss.
3.7.1
Basic and Extendable Blanking Mode
BL
CBK
5.0V
#
IBK
Soft Start
block
0.9V
C3
1
S1
G2
Internal Bias
Current
Limiting
&
20 ms Blanking
Time
Spike
Blanking
30us
4.0V
G10
&
4.0V
C4
20ms
Blanking
Time
G5
Auto
Restart
Mode
4.0V
C4
C5
Active
FB
Burst
Mode
C5
&
G6
1.23V
3.5V
3.0V
&
Active
Burst
Mode
FB
20ms
Blanking
Time
G6
1.23V
C6a
C6b
Control Unit
&
G11
Figure 22
Basic and Extendable Blanking Mode
Control Unit
There are 2 kinds of Blanking mode; basic mode and
the extendable mode. The basic mode has an internal
pre-set 20ms blanking time while the extendable mode
has extended blanking time to basic mode by
connecting an external capacitor to the BL pin. For the
extendable mode, the gate G5 is blocked even though
the 20ms blanking time is reached if an external
capacitor CBK is added to BL pin. While the 20ms
Figure 23
Active Burst Mode
The Active Burst Mode is located in the Control Unit.
Figure 23 shows the related components.
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Functional Description
3.7.2.1
Entering Active Burst Mode
The FB signal is kept monitoring by the comparator C4.
During normal operation, the internal blanking time
counter is reset to 0. When FB signal falls below 1.23V,
it starts to count. When the counter reach 20ms and FB
signal is still below 1.23V, the system enters the Active
Burst Mode. This time window prevents a sudden
entering into the Active Burst Mode due to large load
jumps.
VFB
Leaving
Active Burst
Mode
Entering
Active Burst
Mode
4.0V
3.5V
3.0V
1.23V
After entering Active Burst Mode, a burst flag is set and
the internal bias is switched off in order to reduce the
current consumption of the IC to approx. 450uA.
Blanking Timer
t
20ms Blanking Time
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.
VCS
t
t
t
t
t
3.7.2.2
Working in Active Burst Mode
After entering the Active Burst Mode, the FB voltage
rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FB signal. If the voltage level is larger than 3.5V, the
internal circuit will be activated; the Internal Bias circuit
resumes and starts to provide switching pulse. In
Active Burst Mode the gate G10 is released and the
current limit is reduced to 0.25V. In one hand, it can
reduce the conduction loss and the other hand, it can
reduce the audible noise. If the load at VOUT is still kept
unchanged, the FB signal will drop to 3.0V. At this level
the C6b deactivates the internal circuit again by
switching off the internal Bias. The gate G11 is active
again as the burst flag is set after entering Active Burst
Mode. In Active Burst Mode, the FB voltage is changing
like a saw tooth between 3.0V and 3.5V (see Figure
24).
Current limit level
during Active Burst
Mode
1.06V
0.25V
VVCC
10.5V
IVCC
2.5mA
3.7.2.3
Leaving Active Burst Mode
The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4.
As the current limit is app. 25% during Active Burst
Mode, a certain load jump is needed so that the FB
signal can exceed 4.0V. At that time the comparator C4
resets the Active Burst Mode control which in turn
blocks the comparator C12 by the gate G10. The
maximum current can then be resumed to stabilize
VOUT.
450uA
VOUT
Figure 24
Signals in Active Burst Mode
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Functional Description
3.7.3
Protection Modes
The VCC voltage is observed by comparator C1. If the
VCC voltage is > 25.5V, the overvoltage detection is
activated. It enters the latch off mode.
The IC provides several protection features which are
separated into two categories. Some enter Latched Off
Mode and the others enter Auto Restart Mode. Besides The internal Voltage Reference is switched off most of
the pre-defined protection feature for the Latch off the time once Latched Off Mode is entered in order to
mode, there is also an external Latch off Enable pin for minimize the current consumption of the IC. This
customer defined Latch off protection features. The Latched Off Mode can only be reset if the VVCC < 6.23V.
Latched Off Mode can only be reset if VCC falls below In this mode, only the UVLO is working which controls
6.23V. Both modes prevent the SMPS from destructive the Startup Cell by switching on/off at VVCCon/VVCCoff
.
states.The following table shows the relationship During this phase, the average current consumption is
between possible system failures and the chosen only 250µA. As there is no longer a self-supply by the
protection modes.
VCC Overvoltage
Overtemperature
auxiliary winding, the VCC drops. The Undervoltage
Lockout switches on the integrated Startup Cell when
VCC falls below 10.5V. The Startup Cell is switched off
again when VCC has exceeded 18V. Once the Latched
Off Mode was entered, there is no Start Up Phase
whenever the VCC exceeds the switch-on level of the
Undervoltage Lockout. Therefore the VCC voltage
changes between the switch-on and switch-off levels of
the Undervoltage Lockout with a saw tooth shape (see
Figure 26).
Latched Off Mode
Latched Off Mode
Short Winding/Short Diode Latched Off Mode
BL pin < 0.25V
Overload
Latched Off Mode
Auto Restart Mode
Auto Restart Mode
Auto Restart Mode
Auto Restart Mode
Open Loop
VCC Undervoltage
Short Optocoupler
VVCC
18V
3.7.3.1
Latched Off Mode
10.5V
CS
BL
Spike
Latched Off
Mode Reset
VVCC < 6.23V
C11
Blanking
190ns
1.66V
IVCCStart
t
UVLO
1ms
1
0.9mA
Latched
G3
Off Mode
counter
30us
Blanking
Time
C2
T
LE
#
VOUT
t
0.25V
Latch
Enable
signal
Figure 26
Signals in Latched Off Mode
VCC
The Thermal Shutdown block monitors the junction
temperature of the IC. After detecting a junction
temperature higher than latched thermal shutdown
temperature; TjSD, the Latched Off Mode is entered.
Spike
&
C1
Blanking
25.5V
G1
30us
The signals coming from the temperature detection and
VCC overvoltage detection are fed into a spike
blanking with a time constant of 30µs in order to ensure
the system reliability.
Furthermore, a short winding or short diode on the
secondary side can be detected by the comparator C11
which is in parallel to the propagation delay
compensated current limit comparator C10. In normal
operating mode, comparator C10 controls the
maximum level of the CS signal at 1.06V. If there is a
Voltage
Thermal Shutdown
Reference
T >130°C
j
Control Unit
Figure 25
Latched Off Mode
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ICE3BS03LJG
Functional Description
failure such as short winding or short diode, C10 is no generated which prevents the system to enter Auto
longer able to limit the CS signal at 1.06V. Instead the Restart Mode due to large load jumps.
comparator C11 detects the peak current voltage >
1.66V and enters the Latched Off Mode immediately in
order to keep the SMPS in a safe stage.
In case of VCC undervoltage, the IC enters into the
Auto Restart Mode and starts a new startup cycle.
Short Optocoupler also leads to VCC undervoltage as
there is no self supply after activating the internal
reference and bias.
In contrast to the Latched Off Mode, there is always a
Startup Phase with switching cycles in Auto Restart
Mode. After this Start Up Phase, the conditions are
again checked whether the failure mode is still present.
Normal operation is resumed once the failure mode is
removed that had caused the Auto Restart Mode.
In case the pre-defined Latch Off features are not
sufficient, there is a customer defined external Latch
Enable feature. The Latch Off Mode can be triggered
by pulling down the BL pin to < 0.25V. It can simply add
a trigger signal to the base of the externally added
transistor, TLE at the BL pin. To ensure this latch
function will not be mis-triggered during start up, a 1ms
delay time is implemented to blank the unstable signal.
3.7.3.2
Auto Restart Mode
BL
5.0V
CBK
#
IBK
0.9V
1
S1
G2
C3
C4
Spike
Blanking
30us
4.0V
&
20ms
Blanking
Time
G5
Auto
Restart
Mode
4.0V
FB
Control Unit
Figure 27
Auto Restart Mode
In case of Overload or Open Loop, the FB exceeds
4.0V which will be observed by comparator C4. Then
the internal blanking counter starts to count. When it
reaches 20ms, the switch S1 is released. Then the
clamped voltage 0.9V at VBL can increase. When there
is no external capacitor CBK connected, the VBL will
reach 4.0V immediately. When both the input signals at
AND gate G5 is positive, the Auto-Restart Mode will be
activated after the extra spike blanking time of 30us is
elapsed. However, when an extra blanking time is
needed, it can be achieved by adding an external
capacitor, CBK. A constant current source of IBK will start
to charge the capacitor CBK from 0.9V to 4.0V after the
switch S1 is released. The charging time from 0.9V to
4.0V are the extendable blanking time. If CBK is 0.22uF
and IBK is 13uA, the extendable blanking time is around
52ms and the total blanking time is 72ms. In combining
the FB and blanking time, there is a blanking window
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Electrical Characteristics
4
Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.
4.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
500
27
HV Voltage
VHV
VVCC
VFB
VCS
Tj
-
V
VCC Supply Voltage
FB Voltage
-0.3
-0.3
-0.3
-40
-55
-
V
5.0
V
CS Voltage
5.0
V
Junction Temperature
Storage Temperature
150
150
185
°C
°C
K/W
TS
Thermal Resistance
Junction -Ambient
RthJA
ESD Capability (incl. Drain Pin)
VESD
-
2
kV
Human body model1)
1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)
4.2
Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
26
VCC Supply Voltage
VVCC
TjCon
VVCCoff
-25
V
Junction Temperature of
Controller
130
°C
Max value limited due to thermal
shut down of controller
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Electrical Characteristics
4.3
Characteristics
4.3.1
Supply Section
Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from – 25 °C to 125 °C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Start Up Current
IVCCstart
-
150
250
µA
V
VCC =16.5V
VCC Charge Current
IVCCcharge1
-
-
5.0
1.60
-
mA
mA
mA
µA
V
V
V
VCC = 0V
IVCCcharge2 0.55
0.90
0.7
0.2
VCC = 1V
IVCCcharge3
IStartLeak
-
-
VCC =16.5V
Leakage Current of
Start Up Cell
50
V
HV = 450V,
VCC=18V
V
Supply Current with
Inactive Gate
IVCCsup1
-
1.5
2.5
mA
Supply Current with Active Gate
IVCCsup2
IVCClatch
-
-
2.5
4.2
-
mA
I
I
FB = 0A, CLoad=1nF
FB = 0A
Supply Current in Latched Off
Mode
250
µA
Supply Current in
Auto Restart Mode with Inactive
Gate
IVCCrestart
-
250
-
µA
I
FB = 0A
Supply Current in Active Burst
Mode with Inactive Gate
IVCCburst1
IVCCburst2
-
-
450
450
950
950
µA
µA
V
V
FB = 2.5V
VCC = 11.5V,VFB = 2.5V
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
VVCCon
VVCCoff
VVCChys
17.0
9.8
-
18.0
10.5
7.5
19.0
11.2
-
V
V
V
4.3.2
Internal Voltage Reference
Symbol
Parameter
Limit Values
Unit
Test Condition
min.
typ.
max.
Trimmed Reference Voltage
VREF
4.90
5.00
5.10
V
measured at pin FB
I
FB = 0
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Electrical Characteristics
4.3.3
PWM Section
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
56.5
59.8
-
typ.
65
max.
Fixed Oscillator Frequency
fOSC1
fOSC2
fjitter
73.7
70.2
-
kHz
kHz
kHz
65.0
±2.6
0.75
Tj = 25°C
Tj = 25°C
Frequency Jittering Range
Max. Duty Cycle
Dmax
0.70
0.80
Min. Duty Cycle
PWM-OP Gain
Dmin
0
3.0
-
-
-
VFB < 0.3V
AV
3.2
0.6
0.5
-
3.4
-
Voltage Ramp Offset
VOffset-Ramp
V
V
FB Operating Range Min Level VFBmin
FB Operating Range Max level VFBmax
-
-
V
V
-
4.3
22
V
CS=1V, limited by
Comparator C41)
FB Pull-Up Resistor
RFB
9
15.4
kΩ
1)
The parameter is not subjected to production test - verified by design/characterization
4.3.4
Soft Start time
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Soft Start time
tSS
-
20
-
ms
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Electrical Characteristics
4.3.5
Control Unit
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Clamped VBL voltage during
Normal Operating Mode
VBLclmp
VBKC3
0.85
0.90
0.95
4.15
4.15
1.34
3.65
3.12
26.5
0.33
16.9
V
V
V
V
V
V
V
V
µA
VFB = 4V
Blanking time voltage limit for
Comparator C3
3.85
3.85
1.12
3.35
2.88
24.5
0.17
9.1
4.00
4.00
1.23
3.50
3.00
25.5
0.25
13.0
Over Load & Open Loop Detection VFBC4
Limit for Comparator C4
Active Burst Mode Level for
Comparator C5
VFBC5
VFBC6a
VFBC6b
VVCCOVP
VLE
Active Burst Mode Level for
Comparator C6a
After Active Burst
Mode is entered
Active Burst Mode Level for
Comparator C6b
After Active Burst
Mode is entered
Overvoltage Detection Limit
Latch Enable level at BL pin
Charging current at BL pin
> 30µs
IBK
Charge starts after the
built-in 20ms blanking
time elapsed
Latched Thermal Shutdown1)
TjSD
tBK
130
-
140
20
150
-
°C
Built-in Blanking Time for
Overload Protection or enter
Active Burst Mode
ms
without external
capacitor at BL pin
Inhibit Time for Latch Enable
function during Start up
tIHLE
-
1.0
30
-
ms
µs
V
After IC turns on
Spike Blanking Time before Latch off tSpike
-
-
or Auto Restart Protection
Power Down Reset for
Latched Mode
VVCCPD
5.2
6.23
7.8
After Latched Off Mode
is entered
1)
The parameter is not subjected to production test - verified by design/characterization. The thermal shut down
temperature refers to the junction temperature of the controller.
Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
and VVCCPD
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Electrical Characteristics
4.3.6
Current Limiting
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Peak Current Limitation
(incl. Propagation Delay)
Vcsth
0.99
1.06
1.13
0.31
-
V
dVsense / dt = 0.6V/µs
(see Figure 20)
Peak Current Limitation during VCS2
0.21
-
0.25
220
V
Active Burst Mode
Leading Edge Blanking
tLEB
ns
CS Input Bias Current
ICSbias
VCS1
-1.5
-0.2
-
µA
VCS =0V
Over Current Detection for
Latched Off Mode
1.57
1.66
1.76
V
CS Spike Blanking for
Comparator C11
tCSspike
-
190
-
ns
4.3.7
Driver Section
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
GATE Low Voltage
GATE High Voltage
VGATElow
-
-
1.2
V
V
V
VCC = 5 V
I
Gate = 1 mA
-
-
1.5
VVCC = 5 V
I
I
I
I
Gate = 5 mA
-
0.8
1.6
-
V
V
V
V
Gate = 0 A
-
2.0
Gate = 20 mA
Gate = -20 mA
-0.2
-
0.2
10.0
-
-
VGATEhigh
V
VCC = 26V
CL = 680pF
-
9.0
8.0
150
55
-
-
V
V
VCC = 15V
CL = 680pF
-
-
V
V
VCC = VVCCoff + 0.2V
CL = 680pF
Gate = 2V ...9V1)
CL = 680pF
GATE Rise Time
trise
-
-
ns
ns
A
V
(incl. Gate Rising Slope)
GATE Fall Time
tfall
-
-
V
Gate = 9V ...2V1)
CL = 680pF
CL = 680pF2)
GATE Current, Peak,
Rising Edge
GATE Current, Peak,
Falling Edge
IGATE
IGATE
-0.17
-
-
-
0.39
A
CL = 680pF2)
1)
Transient reference value
2)
The parameter is not subjected to production test - verified by design/characterization
Version 2.0
22
6 Dec 2007
F3 PWM controller
ICE3BS03LJG
Outline Dimension
5
Outline Dimension
PG-DSO-8
(Plastic Dual Small
Outline)
Figure 28 PG-DSO-8 (PB-free Plating Plastic Dual Small Outline)
Dimensions in mm
Version 2.0
23
6 Dec 2007
F3 PWM controller
ICE3BS03LJG
Marking
6
Marking
Marking
Figure 29 Marking for ICE3BS03LJG
Version 2.0
24
6 Dec 2007
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere Anstrengungen gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Quality takes on an allencompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Dazu gehört eine bestimmte
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener
Sichtweise auch über den eigenen
Arbeitsplatz hinaus – und uns ständig
zu verbessern.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit den entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe
Leistung durch umfassende Qualität zu
beweisen.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.
Wir werden Sie überzeugen.
h t t p : / / w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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