ICE3PCS02G [INFINEON]

Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM); 单机功率因数校正（ PFC ）控制器在连续导通模式（ CCM ）


型号：	ICE3PCS02G
厂家：	Infineon
描述：	Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) 单机功率因数校正（ PFC ）控制器在连续导通模式（ CCM ）稳压器开关式稳压器或控制器电源电路开关式控制器功率因数校正光电二极管
文件：	总20页 (文件大小：438K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Version 2.0, 5 May 2010

CCM-PFC

ICE3PCS02G

Standalone Power Factor

Correction (PFC) Controller in

Continuous Conduction Mode

(CCM)

Power Management & Supply

CCM-PFC

Revision History:

Datasheet

Edition 2010-05-05

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

CCM-PFC

ICE3PCS02G

Standalone Power Factor Correction

(PFC) Controller in Continuous

Conduction Mode (CCM)

Product Highlights

•

High efficiency over the whole load range

Lowest count of external components

Accurate and adjustable switching frequency

Integrated digital voltage loop compensation

Fast output dynamic response during load jump

External synchronization

ICE3PCS02G

PG-DSO-8

Low peak current limitation

Features

Description

•

Continuous current operation mode PFC

Wide input range of Vcc up to 25V

The ICE3PCS02G is a 8-pins wide input range controller

IC for active power factor correction converters. It is de-

Enhanced dynamic response without input current signed for converters in boost topology, and requires few

distortion

external components. Its power supply is recommended to

•

External current loop compensation for greater be provided by an external auxiliary supply which will

user flexibility

switch on and off the IC.

•

Open loop protection

Second over bulk voltage protection

Maximum duty cycle of 95% (typical)

D_BYP

D_B

L_Boost

R_GATE

R_BVS

R_{BVS 4}

Line

Filter

C_B

90 ~ 270 Vac

C_E

R_GS

R_BVS

R_{BVS 5}

R_SHUNT

R_BVS

R_{BVS 6}

R_CS

ISENSE

GND

GATE

VSENSE

OVP

FREQ

ICOMP VCC

V_CC

R_FREQ

C_VCC

C_ICOMP

Type

Package

ICE3PCS02G

PG-DSO-8

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.1

1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . .8

Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

First Over-Voltage Protection (OVP1) . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Second Over Voltage Protection (OVP2) . . . . . . . . . . . . . . . . . . . . . . . .12

Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1

3.2

3.3

3.4

3.4.1

3.4.2

3.5

3.5.1

3.5.2

3.6

3.6.1

3.6.2

3.6.3

3.7

3.8

3.8.1

3.8.2

3.8.3

3.8.4

3.9

3.10

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.1

4.2

4.3

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

4.3.8

4.3.9

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Version 2.0

5 May 2010

CCM-PFC

Preliminary Datasheet ICE3PCS02G

Pin Configuration and Functionality

ratings. Therefore a series resistor (R_CS) of around 50Ω

1.1

Pin Configuration

is recommended in order to limit this current into the IC.

GND (IC Ground)

Pin Symbol

Function

The ground potential of the IC.

ISENSE

GND

Current Sense Input

ICOMP (Current Loop Compensation)

IC Ground

Low pass filter and compensation of the current control

loop. The capacitor which is connected at this pin

integrates the output current of OTA6 and averages the

current sense signal.

ICOMP

FREQ

OVP

Current Loop Compensation

Switching Frequency Setting

Over Voltage Protection

VSENSE Bulk Voltage Sense

FREQ (Frequency Setting)

This pin allows the setting of the operating switching

frequency by connecting a resistor to ground. The

frequency range is from 21kHz to 250kHz.

VCC

IC Supply Voltage

Gate Drive

GATE

OVP

A resistive voltage divider from bulk voltage to GND

can set the over voltage protection threshold. This

additional OVP is able to ensure system safety

operation.

Package PG-DSO-8

VSENSE

VSENSE is connected via a resistive divider to the bulk

voltage. The voltage of VSENSE relative to GND

represents the output voltage. The bulk voltage is

monitored for voltage regulation, over voltage

protection and open loop protection.

ISENSE

GATE

VCC

GND

ICOMP

FREQ

P-DSO-8

VSENSE

OVP

VCC

VCC provides the power supply of the ground related

to IC section.

GATE

GATE is the output for driving the PFC MOSFET.Its

gate drive voltage is clamped at 15V (typically).

Figure 1 Pin Configuration (top view)

1.2

Pin Functionality

ISENSE (Current Sense Input)

The ISENSE Pin senses the voltage drop at the

external sense resistor (R_SHUNT). This is the input signal

for the average current regulation in the current loop. It

is also fed to the peak current limitation block.

During power up time, high inrush currents cause high

negative voltage drop at R_SHUNT, driving currents out of

pin 1 which could be beyond the absolute maximum

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Block Diagram

A functional block diagram is given in Figure 2. Note that the figure only shows the brief functional block and does

not represent the implementation of the IC.

Figure 2 Block Diagram

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Block Diagram

Table 1

Bill Of Material

Component

Rectifier Bridge

C_E

L_Boost

Q_B

D_BYP

D_B

C_B

R_shunt

C_isense

R_CS

Parameters

GBU8J

100nF/X2/275V

750uH

IPP60R199CP

MUR360

IDT04S60C

220µF/450V

60mΩ

1nF

50Ω

R_GATE

R_FREQ

C_ICOMP

R_BVS1...2

R_BVS3

R_BVS4...5

R_BVS6

3.3Ω

67kΩ

4.7nF/25V

1.5MΩ

18.85kΩ

2MΩ

23kΩ

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Functional Description

Functional

Description

V_BULK

100%

95%

20%

3.1

General

V_CC

The ICE3PCS02G is a 8-pins control IC for power

factor correction converters. It is suitable for wide range

line input applications from 85 to 265 VAC with overall

efficiency above 90%. The IC supports converters in

boost topology and it operates in continuous

conduction mode (CCM) with average current control.

The IC operates with a cascaded control; the inner

current loop and the outer voltage loop. The inner

current loop of the IC controls the sinusoidal profile for

the average input current. It uses the dependency of

the PWM duty cycle on the line input voltage to

determine the corresponding input current. This means

the average input current follows the input voltage as

long as the device operates in CCM. Under light load

condition, depending on the choke inductance, the

system may enter into discontinuous conduction mode

(DCM) resulting in a higher harmonics but still meeting

the Class D requirement of IEC 1000-3-2.

26V

12V

I_VCC

<6.4mA

with 1nF external cap. at gate drive pin

3.5mA

1.4mA

Standby mode

(V_VSENSE< 0.5V)

Bulk voltage rises to 95% rated value

within 200ms

Normal

UVLO

operation

Figure 3 State of Operation respect to VCC

3.3

Start-up

During power up when the Vout is less than 95% of the

rated level, internal voltage loop output increases from

initial voltage under the soft-start control. This results in

a controlled linear increase of the input current from 0A

thus reducing the stress in the external components.

Once Vout has reached 95% of the rated level, the soft-

start control is released to achieve good regulation and

dynamic response in normal operation.

The outer voltage loop controls the output bulk voltage,

integrated digitally within the IC. Depending on the load

condition, internal PI compensation output is converted

to an appropriate DC voltage which controls the

amplitude of the average input current.

The IC is equipped with various protection features to

ensure safe operating condition for both the system

and device.

3.4

Frequency Setting and External

Synchronization

3.2

Power Supply

The IC can provide external switching frequency

setting by an external resistor R_FREQand the online

synchronization by external pulse signal at FREQ pin.

An internal under voltage lockout (UVLO) block

monitors the VCC power supply. As soon as it exceeds

12.0V and voltage at pin 6 (VSENSE) >0.5V, the IC

begins operating its gate drive and performs its startup

as shown in Figure 3.

3.4.1

Frequency Setting

If VCC drops below 11V, the IC is off. The IC will then

be consuming typically 1.4mA, whereas consuming

6.4mA during normal operation

The switching frequency of the PFC converter can be

set with an external resistor R_FREQat FREQ pin as

shown Figure 2. The pin voltage at V_FREQis typical 1V.

The corresponding capacitor for the oscillator is

integrated in the device and the R_FREQ/frequency is

given in Figure 4. The recommended operating

frequency range is from 21kHz to 250kHz. As an

example, a R_FREQof 67kΩ at pin FREQ will set a

switching frequency F_SWof 65kHz typically.

The IC can be turned off and forced into standby mode

by pulling down the voltage at pin 6 (VSENSE) below

0.5V.

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Functional Description

3.5

Voltage Loop

Frequency vs Resistance

The voltage loop is the outer loop of the cascaded

control scheme which controls the PFC output bus

voltage V_OUT. This loop is closed by the feedback

sensing voltage at VSENSE which is a resistive divider

tapping from V_OUT. The pin VSENSE is the input of

sigma-delta ADC which has an internal reference of

2.5V and sampling rate of 3.55kHz (typical). The

voltage loop compensation is integrated digitally for

better dynamic response and saving design effort.

Figure 6 shows the important blocks of this voltage

loop.

260

240

220

200

180

160

140

120

100

Resistance

/kohm

Frequency

/kHz

Resistance

/kohm

Frequency

/kHz

278

249

211

141

106

110

120

130

140

150

169

191

200

210

221

31.5

29.5

26.2

21.2

20.2

100

232

19.2

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250

Resistance/kohm

L_Boost

D_B

R_BVS1

Figure 4

3.4.2

Frequency Versus R_FREQ

External Synchronization

Q_B

Rectified

R_GATE

R_BVS2

Input Voltage

C_B

The switching frequency can be synchronized to the

external pulse signal after 6 external pulses delay once

the voltage at the FREQ pin is higher than 2.5V. The

synchronization means two points. Firstly, the PFC

switching frequency is tracking the external pulse

signal frequency. Secondly, the falling edge of the PFC

signal is triggered by the rising edge of the external

pulse signal. Figure 5 shows the blocks of frequency

setting and synchronization. The external R_SYN

combined with R_FREQand the external diode D_SYNcan

ensure pin voltage to be kept between 1.0V (clamped

externally) and 5V (maximum pin voltage). If the

external pulse signal has disappeared longer than

108µs (typical) the switching frequency will be

synchronized to internal clock set by the external

R_BVS3

Gate Driver

Current Loop

PWM Generation

GATE

V_IN

Sigma-

delta

ADC

Nonlinear

Gain

Notch

Filter

PI Filter

Av(I_IN

)

2.5V

VSENSE

500 ns

OLP

OVP

C2a

C1a

C1b

0.5V

2.5V

2.7V

OVP

resistor R_FREQ

Syn. clock

I_OSC

1. 0V

Figure 6

3.5.1

Voltage Loop

Notch Filter

D_SYN

OTA7

In the PFC converter, an averaged current through the

output diode of rectified sine waveform charges the

output capacitor and results in a ripple voltage at the

output capacitor with a frequency two times of the line

frequency. In this digital PFC, a notch filter is used to

remove the ripple of the sensed output voltage while

keeping the rest of the signal almost uninfluenced. In

this way, an accurate and fast output voltage regulation

without influence of the output voltage ripple is

achieved.

R_SYN

SYN

FREQ

2.5V/1.25V

Figure 5

Frequency Setting and

Synchronization

3.5.2

Voltage Loop Compensation

The Proportion-Integration (PI) compensation of the

voltage loop is integrated digitally inside the IC. The

digital data out of the PI compensator is converted to

analog voltage for current loop control.

Version 2.0

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CCM-PFC

ICE3PCS02G

Functional Description

The nonlinear gain block controls the amplitude of the

regulated inductor current. The input of this block is the

L_Boost

D_B

output voltage of integrated PI compensator. This block

has been designed to reduce the voltage loop

dependency on the input voltage in order to support the

wide input voltage range (85VAC-265VAC). Figure 7

gives the relative output power transfer curve versus

the digital word from the integrated PI compensator.

The output power at the input voltage of 85VAC and

maximum digital word of 256 from PI compensator is

set as the normative power and the power curves at

different input voltage present the relative power to the

normative one.

Q_B

Rectified

R_GATE

Input Voltage

C_B

R_shunt

GATE

R_CS

Current Loop

voltage

proportional to

averaged

Gate

Inductor current

Driver

ISENSE

ICOMP

Current Loop

Compensation

PWM

power at 85V

power at 265V

Comparator

10.00000

1.00000

0.10000

0.01000

0.00100

0.00010

0.00001

C10

OTA6

5.0mS

PWM Logic

C_ICOMP

+/-50uA (linear range)

Input From

Nonlinear

Gain

Voltage Loop

Fault

Figure 8

3.6.2

Complete System Current Loop

Current Loop Compensation

91 110 128 146 165 183 201 219 238 256

The compensation of the current loop is implemented

at the ICOMP pin. This is OTA6 output and a capacitor

C_ICOMPhas to be installed at this node to ground (see

Figure 8). Under normal mode of the operation, this pin

gives a voltage which is proportional to the averaged

inductor current. This pin is internally shorted to 5V in

the event of standby mode.

PI digital output

Figure 7

Power Transfer Curve

3.6

Average Current Control

The choke current is sensed through the voltage

across the shunt resistor and averaged by the ICOMP

pin capacitor so that the IC can control the choke

current to track the instant variation of the input voltage.

3.6.3

Pulse Width Modulation (PWM)

The IC employs an average current control scheme in

continuous mode (CCM) to achieve the power factor

correction. Assuming the loop voltage is working and

output voltage is kept constant, the off duty cycle D_OFF

for a CCM PFC system is given as:

3.6.1

Complete Current Loop

The complete system current loop is shown in Figure 8.

It consists of the current loop block which averages the

voltage at ISENSE pin resulted from the inductor

current flowing across R_shunt. The averaged waveform

is compared with an internal ramp in the ramp

generator and PWM block. Once the ramp crosses the

average waveform, the comparator C10 turns on the

driver stage through the PWM logic block. The

Nonlinear Gain block defines the amplitude of the

inductor current. The following sections describe the

functionality of each individual blocks.

D_OFF=V_IN/V_OUT

From the above equation, D_OFFis proportional to V_IN.

The objective of the current loop is to regulate the

average inductor current such that it is proportional to

the off duty cycle D_OFF, and thus to the input voltage

V_IN. Figure 9 shows the scheme to achieve the

objective.

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Functional Description

immediately and maintained in off state for the current

PWM cycle. The signal T_OFFMINresets (highest priority,

overriding other input signals) both the current limit

latch and the PWM on latch as illustrated in Figure 11.

Ramp Profile

Ave(I_in) at ICOMP

Current

T_{off_min}

limit Latch

600ns

High = turn on Gate

Peak current limit

Gate

Drive

PWM on

Latch

Current loop

PWM on signal

Figure 9

Average Current Control in CCM

The PWM is performed by the intersection of a ramp

signal with the averaged inductor current at pin 3

(ICOMP). The PWM cycles starts with the Gate turn off

for a duration of T_OFFMIN(600ns typ.) and the ramp is

kept discharged. The ramp is allowed to rise after the

T_OFFMINexpires. The off time of the boost transistor

ends at the intersection of the ramp signal and the

averaged current waveform. This results in the

proportional relationship between the average current

Figure 11

PWM LOGIC

3.8

System Protection

The IC provides numerous protection features in order

to ensure the PFC system in safe operation.

and the off duty cycle D_OFF

Figure 10 shows the timing diagrams of the T_OFFMINand

3.8.1

Peak Current Limit (PCL)

the gate waveforms.

The IC provides a cycle by cycle peak current limitation

(PCL). It is active when the voltage at pin 1 (ISENSE)

reaches -0.4V. This voltage is amplified by a factor of -

2.5 and connected to comparator with a reference

voltage of 1.0V as shown in Figure 12. A deglitcher with

200ns after the comparator improves noise immunity to

the activation of this protection.

_{off_min}600 ns

Clock

PWM Cycle

(1 )

V_C,ref

V_ramp

Full-wave

rectifier

Ramp

Released

ISENSE

R_CS

GATE

G=-2.5

200ns

AO2

PCL

R_shunt

I_in

(1)

V_c,refis a function of V_ICOMP

Figure 10

Ramp and PWM waveforms

SGND

3.7

PWM Logic

The PWM logic block prioritizes the control input signal

and generates the final logic signal to turn on the driver

stage. The speed of the logic gates in this block,

together with the width of the reset pulse T_OFFMIN, are

designed to meet a maximum duty cycle D_MAXof 95%

at the GATE output under 65kHz of operation.

Figure 12 Peak Current Limit (PCL)

3.8.2 Open Loop Protection (OLP)

Whenever VSENSE voltage falls below 0.5V, or

equivalently V_OUTfalls below 20% of its rated value, it

indicates an open loop condition (i.e. VSENSE pin not

connected) or an insufficient input voltage V_INfor

normal operation. It is implemented using comparator

In case of high input currents which results in Peak

Current Limitation, the GATE will be turned off

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Functional Description

C2a with a threshold of 0.5V as shown in the IC block

diagram in Figure 6.

VCC

Reg (17V)

3.8.3

First Over-Voltage Protection (OVP1)

Whenever V_OUTexceeds the rated value by 8%, the

over-voltage protection OVP1 is active as shown in

Figure 6. This is implemented by sensing the voltage at

VSENSE pin with respect to a reference voltage of

2.7V. A VSENSE voltage higher than 2.7V will

immediately turn off the gate, thereby preventing

damage to bus capacitor. After bulk voltage falls below

the rated value, gate drive resumes switching again.

Gate Driver

PWM Logic

HIGH to

turn on

External

MOS

GATE

3.8.4

Second Over Voltage Protection (OVP2)

* LV: Level Shift

The second OVP is provided in case that the first one

fails due to the aging or incorrect resistors connected to

the VSENSE pin. This is implemented by sensing the

voltage at pin OVP with respect to a reference voltage

of 2.5V. When voltage at OVP pin is higher than 2.5V,

the IC will immediately turn off the gate, thereby

preventing damage to bus capacitor.

Figure 13 Gate Driver

When the bulk voltage drops out of the hysteresis the

IC will begin auto soft-start.

In normal operation the trigger level of second OVP

should be designed higher than the first OVP. However

in the condition of mains transient overshoot the bulk

voltage may be pulled up to the peak value of mains

that is higher than the threshold of OVP1 and OVP2. In

this case the OVP1 and OVP2 are triggered in the

same time the IC will shut down the gate drive until bulk

voltage falls out of the two protection hysteresis, then

resume the gate drive again.

3.9

Output Gate Driver

The output gate driver is a fast totem pole gate drive. It

has an in-built cross conduction currents protection and

a Zener diode Z1 (see Figure 13) to protect the external

transistor switch against undesirable over voltages.

The maximum voltage at pin 8 (GATE) is typically

clamped at 15V.

The output is active HIGH and at VCC voltages below

the under voltage lockout threshold V_CCUVLO, the gate

drive is internally pull low to maintain the off state.

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Functional Description

3.10

Protection Function

Description of Fault

Fault-Type Min. Duration Consequence

of Effect

Voltage at Pin ISENSE <

-400mV

PCL

200 ns

Gate Driver is turned off immediately during

current switching cycle

Voltage at Pin VSENSE < 0.5V OLP

1 µs

Power down. Soft-restart after VSENSE voltage

> 0.5V

Voltage at Pin VSENSE >

108% of rated level

OVP1

12 µs

Gate Driver is turned off until VSENSE voltage <

2.5V.

Voltage at Pin OVP > 2.5V and OVP1 and

Voltage at Pin VSENSE >

108% of rated level

Gate Driver is turned off until bulk voltage drops

out of both OVP hysteresis

OVP2

Voltage at Pin OVP > 2.5V

OVP2

(auto-

restart

mode)

12 µs

Gate Driver is turned off. Soft-restart after OVP

voltage < 2.3V

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Electrical Characteristics

All voltages are measured with respect to ground (pin 2). The voltage levels are valid if other ratings are not

violated.

4.1

Absolute Maximum Ratings

Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the

integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is

discharged before assembling the application circuit.

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition

Min.

-0.3

Max.

VCC Supply Voltage

GATE Voltage

V_VCC

V_GATE

Clamped at 15V if

driven internally.

ISENSE Voltage

ISENSE Current

VSENSE Voltage

VSENSE Current

ICOMP Voltage

V_ISENSE

I_ISENSE

V_VSENSE

I_VSENSE

V_ICOMP

V_FREQ

V_OVP

-20

-1

5.3

-0.3

-1

5.3

-0.3

-40

-55

5.3

150

185

260

FREQ Voltage

OVP Voltage

Junction Temperature

Storage Temperature

Thermal Resistance

Soldering Temperature

T_J

°C

T_A,STO

R_THJA

T_SLD

K/W Junction to Air

°C Wave Soldering²⁾

kV Human Body Model³⁾

ESD Capability

V_ESD

Absolute ISENSE current should not be exceeded

According to JESD22A111

According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5kΩ series resistor)

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Electrical Characteristics

4.2

Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition

Min.

V_VCC,OFF

-25

Max.

VCC Supply Voltage @ 25°C

Junction Temperature

V_VCC

T_J

T_J=25°C

125

250

°C

PFC switching frequency

F_PFC

kHz

4.3

Characteristics

Note: The electrical Characteristics involve the spread of values given within the specified supply voltage and

junction temperature range T_Jfrom -25 °C to 125 °C. Typical values represent the median values, which

are related to 25 °C. If not otherwise stated, a supply voltage of V_VCC= 18V, a typical switching frequency

of f_freq=65kHz are assumed and the IC operates in active mode. Furthermore, all voltages are referring to

GND if not otherwise mentioned.

4.3.1

Supply Section

Parameter

Symbol

Limit Values

Unit Note/Test Condition

Min.

Typ.

Max.

VCC Turn-On Threshold

V_CCon

11.5

12.9

11.9

1.45

VCC Turn-Off Threshold/

Under Voltage Lock Out

V_CCUVLO

V_CChy

10.5

11.0

VCC Turn-On/Off Hysteresis

0.7

Start Up Current

Before V_CCon

I_CCstart1

I_CCstart2

I_CCHG

380

1.4

6.4

3.5

680 µA

V_CCon-1.2V

Start Up Current

Before V_CCon

2.4

8.5

4.7

mA V_CCon-0.2V

mA C_L= 1nF

Operating Current with active GATE

Operating Current during Standby

I_CCStdby

mA V_VSENSE= 0.4V

_ICOMP= 4V

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Electrical Characteristics

4.3.2

Variable Frequency Section

Parameter

Symbol

Limit Values

Unit Test Condition

Min.

Typ.

Max.

67.5 kHz R5 = 67kΩ

Switching Frequency (Typical)

Switching Frequency (Min.)

Switching Frequency (Max.)

Voltage at FREQ pin

F_SWnom

F_SWmin

F_SWmax

V_FREQ

Dmax

62.5

250

kHz R5 = 212kΩ

kHz R5 = 17kΩ

Max. Duty Cycle

98.5

f_SW=f_SWnom

(R_FRE=67kΩ)

4.3.3

PWM Section

Parameter

Symbol

Limit Values

Unit Test Condition

Min.

Typ.

Max.

Min. Duty Cycle

Min. Off Time

D_MIN

V_VSENSE= 2.5V

_ICOMP= 4.3V

T_OFFMIN

310

600

920

V_VSENSE= 2.5V

_ISENSE= 0V

(R5 = 67kΩ)

4.3.4

External Synchronization

Parameter

Symbol

Values

Typ.

2.5

Unit Note / Test Condition

Min.

Max.

150

Detection threshold of external clock

Synchronization range

V_{thr_EXT}

f_{EXT_range}

kHz

Synchronization frequency ratio

f_EXT:f_PFC

1:1

propagation delay from rising edge of

external clock to falling edge of PFC

gate drive

T_EXT2GATE

500

f_EXT=65kHz

Allowable external duty on time

T_{D_on}

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Electrical Characteristics

4.3.5

System Protection Section

Parameter

Symbol

Values

Typ.

2.7

Unit Note / Test Condition

Min.

Max.

Over Voltage Protection (OVP1) Low to V_{OVP1_L2H}

High

2.65

2.77

108%V_BULKRated

Over Voltage Protection (OVP1) High to V_{OVP1_H2L}

Low

2.45

150

2.5

2.55

270

Over Voltage Protection (OVP1)

Hysteresis

V_{OVP1_HYS}

200

Blanking time for OVP1

T_OVP1

µs

Over Voltage Protection (OVP2) Low to V_{OVP2_L2H}

High

2.45

2.25

2.5

2.55

2.35

Over Voltage Protection (OVP2) High to I_{OVP2_H2L}

Low

2.3

Blanking time for OVP2

T_OVP2

0.5

µs

OVP2 mode detection threshold

V_{OVP2_mode}

I_{OVP2_mode}

comparator at VBTHL pin

Current source for OVP2 mode

detection¹⁾

µA current source at VBTHL

Peak Current Limitation (PCL) ISENSE V_PCL

Threshold

-365

-400

-435 mV

Blanking time for PCL turn_on

T_PCLon

200

The parameter is not subject to production test - verified by design/characterization

4.3.6

Current Loop Section

Parameter

Symbol

Values

Typ.

5.0

Unit Note / Test Condition

Min.

Max.

OTA6 Transconductance Gain

OTA6 Output Linear Range¹⁾

Gm_OTA6

I_OTA6

3.5

6.35

mS At Temp = 25°C

± 50

5.0

µA

ICOMP Voltage during OLP

V_ICOMPF

4.8

5.2

V_VSENSE= 0.4V

The parameter is not subject to production test - verified by design/characterization

4.3.7

Voltage Loop Section

Parameter

Symbol

Values

Typ.

2.5

Unit Note / Test Condition

Min.

2.47

0.45

Max.

2.53

0.55

Trimmed Reference Voltage

V_VSREF

±1.2%

Open Loop Protection (OLP) VSENSE V_{VS_OLP}

Threshold

0.5

VSENSE Input Bias Current

I_VSENSE

-1

µA

V_VSENSE= 2.5V

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Electrical Characteristics

4.3.8

Driver Section

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition

Min.

Max.

GATE Low Voltage

V_GATEL

1.2

V_CC=10V

_GATE= 5 mA

0.4

1.4

_GATE= 0 A

_GATE= 20 mA

_GATE= -20 mA

-0.2

0.8

GATE High Voltage

V_GATEH

_CC= 25V

C_L= 1nF

12.4

_CC= 15V

C_L= 1nF

8.0

_CC= V_VCCoff+ 0.2V

C_L= 1nF

4.3.9

Gate Drive Section

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition

Min.

Max.

GATE Rise Time

GATE Fall Time

t_r

t_f

_Gate= 20% - 80%

V_GATEHC_L= 1nF

_Gate= 80% - 20%

V_GATEHC_L= 1nF

Version 2.0

5 May 2010

CCM-PFC

ICE3PCS02G

Outline Dimension

PG-DSO-8 Outline Dimension

±0.08

0.33

x 45˚

4_-0.2

1.27

0.1

±0.25

0.64

+0.1

-0.05

0.41

0.2 A C x8

±0.2

Index

Marking

5_-0.2

Index Marking (Chamfer)

¹⁾Does not include plastic or metal protrusion of 0.15 max. per side

Notes:

1. You can find all of our packages, sorts of packing and others in our Infineon

Internet Page “Products”: http://www.infineon.com/products.

2. Dimensions in mm.

Version 2.0

5 May 2010

Total Quality Management

Qualität hat für uns eine umfassende

Bedeutung. Wir wollen allen Ihren

Ansprüchen in der bestmöglichen

Weise gerecht werden. Es geht uns also

nicht nur um die Produktqualität –

unsere Anstrengungen gelten

gleichermaßen der Lieferqualität und

Logistik, dem Service und Support

sowie allen sonstigen Beratungs- und

Betreuungsleistungen.

Quality takes on an allencompassing

significance at Semiconductor Group.

For us it means living up to each and

every one of your demands in the best

possible way. So we are not only

concerned with product quality. We

direct our efforts equally at quality of

supply and logistics, service and

support, as well as all the other ways in

which we advise and attend to you.

Dazu gehört eine bestimmte

Part of this is the very special attitude of

our staff. Total Quality in thought and

deed, towards co-workers, suppliers

and you, our customer. Our guideline is

“do everything with zero defects”, in an

open manner that is demonstrated

beyond your immediate workplace, and

to constantly improve.

Throughout the corporation we also

think in terms of Time Optimized

Processes (top), greater speed on our

part to give you that decisive

competitive edge.

Geisteshaltung unserer Mitarbeiter.

Total Quality im Denken und Handeln

gegenüber Kollegen, Lieferanten und

Ihnen, unserem Kunden. Unsere

Leitlinie ist jede Aufgabe mit „Null

Fehlern“ zu lösen – in offener

Sichtweise auch über den eigenen

Arbeitsplatz hinaus – und uns ständig

zu verbessern.

Unternehmensweit orientieren wir uns

dabei auch an „top“ (Time Optimized

Processes), um Ihnen durch größere

Schnelligkeit den entscheidenden

Wettbewerbsvorsprung zu verschaffen.

Geben Sie uns die Chance, hohe

Leistung durch umfassende Qualität zu

beweisen.

Give us the chance to prove the best of

performance through the best of quality

– you will be convinced.

Wir werden Sie überzeugen.

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

ICE3PCS02G [INFINEON]

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