ICE3PCS03GXUMA1 [INFINEON]
Power Factor Controller, Current-mode, 250kHz Switching Freq-Max, PDSO8, GREEN, PLASTIC, SOP-8;型号: | ICE3PCS03GXUMA1 |
厂家: | Infineon |
描述: | Power Factor Controller, Current-mode, 250kHz Switching Freq-Max, PDSO8, GREEN, PLASTIC, SOP-8 光电二极管 |
文件: | 总20页 (文件大小:210K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Version 2.0, 5 May 2010
CCM-PFC
ICE3PCS03G
Standalone Power Factor
Correction (PFC) Controller in
Continuous Conduction Mode
(CCM)
Power Management & Supply
CCM-PFC
Revision History:
Datasheet
Edition 2010-05-12
Published by
Infineon Technologies AG
81726 Munich, Germany
©Infineon Technologies AG 05/05/10.
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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question, please contact the nearest Infineon Technologies Office.
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
CCM-PFC
ICE3PCS03G
Standalone Power Factor Correction
(PFC) Controller in Continuous
Conduction Mode (CCM)
Product Highlights
•
•
•
•
•
•
•
High efficiency over the whole load range
Lowest count of external components
Accurate and adjustable switching frequency
Integrated digital voltage loop compensation
Fast output dynamic response during load jump
External synchronization
ICE3PCS03G
PG-DSO-8
Low peak current limitation
Features
Description
•
•
•
Continuous current operation mode PFC
The ICE3PCS03G is a 8-pins wide input range controller
IC for active power factor correction converters. It is de-
signed for converters in boost topology, and requires few
external components. Its power supply is recommended
to be provided by an external auxiliary supply which will
switch on and off the IC.
Wide input range of Vcc up to 25V
Enhanced dynamic response without input
current distortion
•
•
Accurate brown-out protection threshold
External current loop compensation for greater
user flexibility
•
•
Open loop protection
Maximum duty cycle of 95% (typical)
DBYP
DB
LBoos t
RBVS
RGATE
1
Line
Filter
CB
90 ~ 270 Vac
CE
RGS
RBVS
2
RSH UN T
RBVS
3
DBRO1
DBRO2
RCS
RBRO1
ISENSE
GATE
VSENSE
RBRO2
BOP
RBRO3
CBRO
GND
FREQ
ICOMP VCC
CVCC
RFREQ
CICOMP
VCC
Type
Package
ICE3PCS03G
PG-DSO-8
Version 2.0
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CCM-PFC
ICE3PCS03G
1
1.1
1.2
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . . 8
Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input Voltage Brownout Protection(BOP) . . . . . . . . . . . . . . . . . . . . . . . . 11
Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
First Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.6.3
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.9
3.10
4
4.1
4.2
4.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PFC Brownout Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
5
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS03G
Pin Configuration and Functionality
1
1.1
Pin Configuration and Functionality
ratings. Therefore a series resistor (RCS) of around 50
Pin Configuration
is recommended in order to limit this current into the IC
GND (IC Ground)
Pin Symbol
Function
The ground potential of the IC.
1
2
3
4
5
6
7
8
ISENSE
GND
Current Sense Input
IC Ground
ICOMP (Current Loop Compensation)
Low pass filter and compensation of the current control
loop. The capacitor which is connected at this pin
integrates the output current of OTA6 and averages the
current sense signal.
ICOMP
FREQ
BOP
Current Loop Compensation
Switching Frequency Setting
Brownout Protection
VSENSE Bulk Voltage Sense
FREQ (Frequency Setting)
VCC
IC Supply Voltage
Gate Drive
This pin allows the setting of the operating switching
frequency by connecting a resistor to ground. The
frequency range is from 21kHz to 250kHz.
GATE
BOP (Brownout Protection)
BOP monitors the AC input voltage for Brownout
Protection.
Package PG-DSO-8
VSENSE
VSENSE is connected via a resistive divider to the bulk
voltage. The voltage of VSENSE relative to GND
represents the output voltage. The bulk voltage is
monitored for voltage regulation, over voltage
protection and open loop protection.
ISENSE
GATE
VCC
GND
ICOMP
FREQ
VCC
P-DSO-8
VSENSE
BOP
VCC provides the power supply of the ground related
to IC section.
GATE
GATE is the output for driving the PFC MOSFET.Its
gate drive voltage is clamped at 15V (typically).
Figure 1 Pin Configuration (top view)
1.2
Pin Functionality
ISENSE (Current Sense Input)
The ISENSE Pin senses the voltage drop at the
external sense resistor (RSHUNT). This is the input signal
for the average current regulation in the current loop. It
is also fed to the peak current limitation block.
During power up time, high inrush currents cause high
negative voltage drop at RSHUNT, driving currents out of
pin 1 which could be beyond the absolute maximum
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CCM-PFC
ICE3PCS03G
Block Diagram
2
Block Diagram
A functional block diagram is given in Figure 2. Note that the figure only shows the brief functional block and does
not represent the implementation of the IC.
Figure 2 Block Diagram
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5 May 2010
CCM-PFC
ICE3PCS03G
Block Diagram
Table 1
Bill of Material
Component
Parameters
GBU8J
Rectifier Bridge
CE
100nF/X2/275V
750uH
LBoost
QB
IPP60R199CP
MUR360
IDT04S60C
220µF/450V
1N4007
3.9M
DBYP
DB
CB
DBRO1...2
RBRO1...2
RBRO3
CBRO
130k
3F
Rshunt
Cisense
RCS
60m
1nF
50
RGATE
RFREQ
CICOMP
RBVS1...2
RBVS3
3.3
67k
4.7nF/25V
1.5M
18.85k
Version 2.0
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CCM-PFC
ICE3PCS03G
Functional Description
3
Functional
Description
VBULK
100%
95%
20%
3.1
General
VCC
The ICE3PCS03G is a 8-pins control IC for power
factor correction converters. It is suitable for wide range
line input applications from 85 to 265 VAC with overall
efficiency above 90%. The IC supports converters in
boost topology and it operates in continuous
conduction mode (CCM) with average current control.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM) resulting in a higher harmonics but still meeting
the Class D requirement of IEC 1000-3-2.
The outer voltage loop controls the output bulk voltage,
integrated digitally within the IC. Depending on the load
condition, internal PI compensation output is converted
to an appropriate DC voltage which controls the
amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device.
26V
12V
IVCC
<6.4mA
with 1nF external cap. at gate drive pin
3.5mA
1.4mA
Bulk voltage rises to 95% rated value
within 200ms
Standby mode
(VVSENSE < 0.5V)
Normal
operation
UVLO
Figure 3 State of Operation respect to VCC
3.3
Start-up
During power up when the Vout is less than 95% of the
rated level, internal voltage loop output increases from
initial voltage under the soft-start control. This results in
a controlled linear increase of the input current from 0A
thus reducing the stress in the external components.
Once Vout has reached 95% of the rated level, the soft-
start control is released to achieve good regulation and
dynamic response.
3.4
Frequency Setting and External
Synchronization
3.2
Power Supply
The IC can provide external switching frequency
setting by an external resistor RFREQ and the online
synchronization by external pulse signal at FREQ pin.
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
12.0V and both voltages at pin 6 (VSENSE) >0.5V and
pin 5 (BOP) >1.25V, the IC begins operating its gate
drive and performs its startup as shown in Figure 3.
If VCC drops below 11V, the IC is off. The IC will then
be consuming typically 1.4mA, whereas consuming
6.4mA during normal operation
3.4.1
Frequency Setting
The switching frequency of the PFC converter can be
set with an external resistor RFREQ at FREQ pin as
shown Figure 2. The pin voltage at VFREQ is typical 1V.
The corresponding capacitor for the oscillator is
integrated in the device and the RFREQ/frequency is
given in Figure 4. The recommended operating
frequency range is from 21kHz to 250kHz. As an
example, a RFREQ of 67k at pin FREQ will set a
switching frequency FSW of 65kHz typically.
The IC can be turned off and forced into standby mode
by pulling down the voltage at pin 6 (VSENSE) below
0.5V.
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS03G
Functional Description
3.5
Voltage Loop
Frequency vs Resistance
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage VOUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from VOUT. The pin VSENSE is the input of
sigma-delta ADC which has an internal reference of
2.5V and sampling rate of 3.55kHz (typical). The
voltage loop compensation is integrated digitally for
better dynamic response and saving design effort.
Figure 6 shows the important blocks of this voltage
loop.
260
240
220
200
180
160
140
120
100
80
Resistance
/kohm
Frequency
/kHz
Resistance
/kohm
Frequency
/kHz
15
17
20
30
40
50
60
70
80
90
278
249
211
141
106
86
110
120
130
140
150
169
191
200
210
221
40
36
34
31.5
29.5
26.2
25
74
62
23
55
21.2
20.2
49
60
100
43
232
19.2
40
20
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250
Resistance/kohm
LBoost
DB
RBVS1
Figure 4
3.4.2
Frequency Versus RFREQ
External Synchronization
QB
Rectified
Input Voltage
RGATE
RBVS2
CB
The switching frequency can be synchronized to the
external pulse signal after 6 external pulses delay once
the voltage at the FREQ pin is higher than 2.5V. The
synchronization means two points. Firstly, the PFC
switching frequency is tracking the external pulse
signal frequency. Secondly, the falling edge of the PFC
signal is triggered by the rising edge of the external
pulse signal. Figure 5 shows the blocks of frequency
setting and synchronization. The external RSYN
combined with RFREQ and the external diode DSYN can
ensure pin voltage to be kept between 1.0V (clamped
externally) and 5V (maximum pin voltage). If the
external pulse signal has disappeared longer than
108s (typical) the switching frequency will be
synchronized to internal clock set by the external
RBVS3
Gate Driver
Current Loop
+
PWM Generation
GATE
VIN
Sigma-
delta
ADC
Nonlinear
Gain
Notch
Filter
PI Filter
Av(IIN
)
2.5V
VSENSE
t
500 ns
OLP
OVP
C2a
C1a
C1b
0.5V
2.5V
2.7V
OVP
Q
R
resistor RFREQ
.
Q
S
Syn. clock
IOSC
1.0V
Figure 6
3.5.1
Voltage Loop
Notch Filter
DSYN
OTA7
In the PFC converter, an averaged current through the
output diode of rectified sine waveform charges the
output capacitor and results in a ripple voltage at the
output capacitor with a frequency two times of the line
frequency. In this digital PFC, a notch filter is used to
remove the ripple of the sensed output voltage while
keeping the rest of the signal almost uninfluenced. In
this way, an accurate and fast output voltage regulation
without influence of the output voltage ripple is
achieved.
RSYN
C9
SYN
R
FREQ
FREQ
2.5V/1.25V
3.5.2
Voltage Loop Compensation
Figure 5
Frequency Setting and
Synchronization
The Proportion-Integration (PI) compensation of the
voltage loop is integrated digitally inside the IC. The
digital data out of the PI compensator is converted to
analog voltage for current loop control.
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CCM-PFC
ICE3PCS03G
Functional Description
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
LBoost
DB
output voltage of integrated PI compensator. This block
has been designed to reduce the voltage loop
dependency on the input voltage in order to support the
wide input voltage range (85VAC-265VAC). Figure 7
gives the relative output power transfer curve versus
the digital word from the integrated PI compensator.
The output power at the input voltage of 85VAC and
maximum digital word of 256 from PI compensator is
set as the normative power and the power curves at
different input voltage present the relative power to the
normative one.
QB
Rectified
Input Voltage
RGATE
CB
Rshunt
GATE
RCS
Current Loop
voltage
proportional to
averaged
Gate
Driver
Inductor current
ISENSE
ICOMP
Current Loop
Compensation
PWM
power at 85V
power at 265V
Comparator
Q
R
S
10.00000
1.00000
0.10000
0.01000
0.00100
0.00010
0.00001
C10
OTA6
5.0mS
PWM Logic
CICOMP
+/-50uA (linear range)
S2
5V
Input From
Voltage Loop
Nonlinear
Gain
Fault
Figure 8
3.6.2
Complete System Current Loop
Current Loop Compensation
0
18
37
55
73
91 110 128 146 165 183 201 219 238 256
The compensation of the current loop is implemented
at the ICOMP pin. This is OTA6 output and a capacitor
CICOMP has to be installed at this node to ground (see
Figure 8). Under normal mode of the operation, this pin
gives a voltage which is proportional to the averaged
inductor current. This pin is internally shorted to 5V in
the event of standby mode.
PI digital output
Figure 7
Power Transfer Curve
3.6
Average Current Control
The choke current is sensed through the voltage
across the shunt resistor and averaged by the ICOMP
pin capacitor so that the IC can control the choke
current to track the instant variation of the input voltage.
3.6.3
Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous mode (CCM) to achieve the power factor
correction. Assuming the voltage loop is working and
output voltage is kept constant, the off duty cycle DOFF
for a CCM PFC system is given as:
3.6.1
Complete Current Loop
The complete system current loop is shown in Figure 8.
It consists of the current loop block which averages the
voltage at ISENSE pin resulted from the inductor
current flowing across Rshunt. The averaged waveform
is compared with an internal ramp in the ramp
generator and PWM block. Once the ramp crosses the
average waveform, the comparator C10 turns on the
driver stage through the PWM logic block. The
Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
DOFF=VIN/VOUT
From the above equation, DOFF is proportional to VIN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle DOFF, and thus to the input voltage
VIN. Figure 9 shows the scheme to achieve the
objective.
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CCM-PFC
ICE3PCS03G
Functional Description
immediately and maintained in off state for the current
PWM cycle. The signal TOFFMIN resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Ramp Profile
Ave(Iin) at ICOMP
Current
limit Latch
Toff_min
600ns
R
S
Q
Q
High = turn on Gate
Peak current limit
Gate
Drive
PWM on
Latch
t
R
Q
Current loop
PWM on signal
Figure 9
Average Current Control in CCM
S
Q
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 3
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of TOFFMIN (600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
TOFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
Figure 11
PWM LOGIC
3.8
System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
and the off duty cycle DOFF
.
Figure 10 shows the timing diagrams of the TOFFMIN and
the gate waveforms.
3.8.1
Input Voltage Brownout Protection(BOP)
Brownout occurs when the input voltage VIN falls below
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the VCC has not
entered into the VCCUVLO level yet. For a system without
BOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
T
off_min 600 ns
Clock
PWM Cycle
(1 )
VC,ref
ICE3PCS03G provides a new BOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network shown in Figure 12. This network provides a
filtered value of VIN which turns the IC on when the
voltage at pin 5 (BOP) is more than 1.25V. The IC
enters into the fault mode when BOP goes below 1.0V.
The hysteresis prevents the system to oscillate
between normal and fault mode. Note also that the
peak of VIN needs to be at least 20% of the rated VOUT
in order to overcome OLP and powerup system.
Vramp
Ramp
Released
GATE
t
(1)
Vc,ref is a function of VICOMP
Figure 10
Ramp and PWM waveforms
3.7
PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse TOFFMIN, are
designed to meet a maximum duty cycle DMAX of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
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CCM-PFC
ICE3PCS03G
Functional Description
VSENSE pin with respect to a reference voltage of
2.7V. A VSENSE voltage higher than 2.7V will
immediately turn off the gate, thereby preventing
damage to bus capacitor. After bulk voltage falls below
the rated value, gate drive resumes switching again.
Line
Filter
90 ~ 270 Vac
DBRO2
DBRO1
3.9
Output Gate Driver
RBRO1
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 14) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 15V.
1.25V
C8b
C8a
Brownout
Latch
RBRO2
BOP
CBRO
Brownout
R
Q
S
Q
RBRO3
1V
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the gate
drive is internally pull low to maintain the off state.
Figure 12
3.8.2
Input Brownout Protection
Peak Current Limit (PCL)
VCC
Reg (17V)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 1 (ISENSE)
reaches -0.4V. This voltage is amplified by a factor of -
2.5 and connected to comparator with a reference
voltage of 1.0V as shown in Figure 13. A deglitcher with
200ns after the comparator improves noise immunity to
the activation of this protection.
Gate Driver
PWM Logic
HIGH to
turn on
LV
External
MOS
Z1
GATE
Full-wave
rectifier
* LV: Level Shift
ISENSE
RCS
G=-2.5
Figure 14 Gate Driver
200ns
AO2
PCL
Rshunt
C5
Iin
1V
SGND
Figure 13 Peak Current Limit (PCL)
3.8.3 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.5V, or
equivalently VOUT falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage VIN for
normal operation. It is implemented using comparator
C2a with a threshold of 0.5V as shown in the IC block
diagram in Figure 6.
3.8.4
First Over-Voltage Protection (OVP)
Whenever VOUT exceeds the rated value by 8%, the
over-voltage protection OVP1 is active as shown in
Figure 6. This is implemented by sensing the voltage at
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CCM-PFC
ICE3PCS03G
Functional Description
3.10
Protection Function
Description of Fault
Fault-Type Min. Duration Consequence
of Effect
Voltage at Pin ISENSE <
-400mV
PCL
200 ns
20 s
1 s
Gate Driver is turned off immediately during
current switching cycle
Voltage at Pin BOP < 1V
BOP
Gate Driver is turned off. Soft-restart after BOP
voltage > 1.25V
Voltage at Pin VSENSE < 0.5V OLP
Power down. Soft-restart after VSENSE voltage
> 0.5V
Voltage at Pin VSENSE >
108% of rated level
OVP1
12s
Gate Driver is turned off until VSENSE voltage <
2.5V.
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CCM-PFC
ICE3PCS03G
Electrical Characteristics
4
Electrical Characteristics
All voltages are measured with respect to ground (pin 2). The voltage levels are valid if other ratings are not
violated.
4.1
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the
integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is
discharged before assembling the application circuit.
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
-0.3
-0.3
Max.
26
VCC Supply Voltage
GATE Voltage
VVCC
V
VGATE
17
V
Clamped at 15V if
driven internally.
1)
ISENSE Voltage
ISENSE Current
VSENSE Voltage
VSENSE Current
ICOMP Voltage
VISENSE
IISENSE
VVSENSE
IVSENSE
VICOMP
VFREQ
VBOP
-20
-1
5.3
1
V
mA
V
-0.3
-1
5.3
1
mA
V
-0.3
-0.3
-0.3
-1
5.3
5.3
9.5
35
FREQ Voltage
V
2)
BOP Voltage
V
BOP Current
IBOP
A
°C
°C
Junction Temperature
Storage Temperature
Thermal Resistance
Soldering Temperature
TJ
-40
-55
150
150
185
260
2
TA,STO
RTHJA
TSLD
K/W Junction to Air
°C Wave Soldering3)
kV Human Body Model4)
ESD Capability
VESD
1)
Absolute ISENSE current should not be exceeded
Absolute BOP current should not be exceeded
According to JESD22A111
2)
3)
4)
According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5k series resistor)
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CCM-PFC
ICE3PCS03G
Electrical Characteristics
4.2
Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
VVCC,OFF
-25
Max.
25
VCC Supply Voltage @ 25°C
Junction Temperature
VVCC
TJ
V
TJ=25°C
125
250
°C
PFC switching frequency
FPFC
21
kHz
4.3
Characteristics
Note: The electrical Characteristics involve the spread of values given within the specified supply voltage and
junction temperature range TJ from -25 °C to 125 °C. Typical values represent the median values, which
are related to 25 °C. If not otherwise stated, a supply voltage of VVCC = 18V, a typical switching frequency
of ffreq=65kHz are assumed and the IC operates in active mode. Furthermore, all voltages are referring to
GND if not otherwise mentioned.
4.3.1
Supply Section
Parameter
Symbol
Limit Values
Unit Note/Test Condition
Min.
Typ.
Max.
VCC Turn-On Threshold
VCCon
11.5
12
12.9
11.9
1.45
V
V
V
VCC Turn-Off Threshold/
Under Voltage Lock Out
VCCUVLO
VCChy
10.5
11.0
1
VCC Turn-On/Off Hysteresis
0.7
Start Up Current
Before VCCon
ICCstart1
ICCstart2
ICCHG
-
-
380
1.4
6.4
3.5
680 A
VCCon-1.2V
Start Up Current
Before VCCon
2.4
8.5
4.7
mA VCCon-0.2V
mA CL= 1nF
Operating Current with active GATE
-
Operating Current during Standby
ICCStdby
-
mA VVSENSE= 0.4V
V
ICOMP= 4V
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CCM-PFC
ICE3PCS03G
Electrical Characteristics
4.3.2
Variable Frequency Section
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
67.5 kHz R5 = 67k
Switching Frequency (Typical)
Switching Frequency (Min.)
Switching Frequency (Max.)
Voltage at FREQ pin
FSWnom
FSWmin
FSWmax
VFREQ
Dmax
62.5
65
-
-
21
250
1
-
kHz R5 = 212k
kHz R5 = 17k
V
-
-
-
Max. Duty Cycle
93
95
98.5
%
f
SW=fSWnom
(RFREQ=67k)
4.3.3
PWM Section
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
Min. Duty Cycle
Min. Off Time
DMIN
0
%
VVSENSE= 2.5V
ICOMP= 4.3V
V
TOFFMIN
310
600
920
ns
VVSENSE= 2.5V
ISENSE= 0V
(R5 = 67k)
V
4.3.4
External Synchronization
Parameter
Symbol
Values
Typ.
2.5
Unit Note / Test Condition
Min.
Max.
150
Detection threshold of external clock
Synchronization range
Vthr_EXT
V
fEXT_range
50
kHz
Synchronization frequency ratio
fEXT:fPFC
1:1
propagation delay from rising edge of
external clock to falling edge of PFC
gate drive
TEXT2GATE
500
ns
%
fEXT=65kHz
Allowable external duty on time
TD_on
10
70
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CCM-PFC
ICE3PCS03G
Electrical Characteristics
4.3.5
PFC Brownout Protection Section
Parameter
Symbol
Values
Typ.
1
Unit Note / Test Condition
Min.
Max.
Input Brownout Protection High to Low
Threshold
VBOP_H2L
VBOP_L2H
0.98
1.02
V
V
Input Brownout Protection Low to High
Threshold
1.2
1.25
1.3
0.5
Blanking time for BOP turn_on
TBOPon
IBOP
20
-
s
Input Brownout Protection BOP Bias
Current
-0.5
A
VBOP=1.25V
4.3.6
System Protection Section
Parameter
Symbol
Values
Typ.
2.7
Unit Note / Test Condition
Min.
Max.
Over Voltage Protection (OVP) Low to
High
VOVP1_L2H
VOVP1_H2L
VOVP1_HYS
TOVP1
2.65
2.45
150
2.77
2.55
270
V
V
108%VBULKRated
Over Voltage Protection (OVP) High to
Low
2.5
Over Voltage Protection (OVP )
Hysteresis
200
mV
Blanking time for OVP
12
s
Peak Current Limitation (PCL) ISENSE VPCL
Threshold
-365
-400
-435 mV
ns
Blanking time for PCL turn_on
TPCLon
200
4.3.7 Current Loop Section
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
Max
.
OTA6 Transconductance Gain
OTA6 Output Linear Range1)
GmOTA6
IOTA6
3.5
5.0
± 50
5.0
6.35 mS At Temp = 25°C
A
ICOMP Voltage during OLP
VICOMPF
4.8
5.2
V
VVSENSE= 0.4V
1)
The parameter is not subject to production test - verified by design/characterization
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CCM-PFC
ICE3PCS03G
Electrical Characteristics
4.3.8
Voltage Loop Section
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
Max
.
Trimmed Reference Voltage
VVSREF
2.47
0.45
2.5
0.5
2.53
0.55
V
V
±1.2%
Open Loop Protection (OLP) VSENSE VVS_OLP
Threshold
VSENSE Input Bias Current
IVSENSE
-1
-
1
A VVSENSE= 2.5V
4.3.9 Driver Section
Parameter
Symbol
Values
Typ.
-
Unit Note / Test Condition
Min.
Max.
GATE Low Voltage
VGATEL
-
1.2
V
VCC =10V
IGATE = 5 mA
-
0.4
-
-
1.4
-
V
V
V
V
I
GATE = 0 A
-
IGATE = 20 mA
GATE = -20 mA
-0.2
-
0.8
15
I
GATE High Voltage
VGATEH
-
VCC = 25V
CL = 1nF
-
12.4
-
-
-
V
V
V
CC = 15V
CL = 1nF
8.0
VCC = VVCCoff + 0.2V
CL = 1nF
4.3.10
Gate Drive Section
Parameter
Symbol
Values
Typ.
30
Unit Note / Test Condition
Min.
Max.
GATE Rise Time
GATE Fall Time
tr
tf
-
-
ns VGate = 20% - 80%
VGATEH CL = 1nF
-
25
-
ns VGate = 80% - 20%
VGATEH CL = 1nF
Version 2.0
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CCM-PFC
ICE3PCS03G
Outline Dimension
5
Outline Dimension
PG-DSO-8 Outline Dimension
±0.08
0.33
x 45˚
1)
4-0.2
1.27
C
0.1
±0.25
0.64
+0.1
-0.05
0.41
M
0.2 A C x8
±0.2
6
8
1
5
Index
Marking
4
A
1)
5-0.2
Index Marking (Chamfer)
1) Does not include plastic or metal protrusion of 0.15 max. per side
Notes:
1. You can find all of our packages, sorts of packing and others in our Infineon
Internet Page “Products”: http://www.infineon.com/products.
2. Dimensions in mm.
Version 2.0
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5 May 2010
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere Anstrengungen gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Quality takes on an allencompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Dazu gehört eine bestimmte
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener
Sichtweise auch über den eigenen
Arbeitsplatz hinaus – und uns ständig
zu verbessern.
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit den entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.
Geben Sie uns die Chance, hohe
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Wir werden Sie überzeugen.
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Published by Infineon Technologies AG
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