ICE3PCS01G [INFINEON]
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM); 单机功率因数校正（ PFC ）控制器在连续导通模式（ CCM ）
| 型号： | ICE3PCS01G |
| 厂家： | 
Infineon |
| 描述： | Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) |
| 文件： | 总24页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Version 2.0, 5 May 2010
CCM-PFC
ICE3PCS01G
Standalone Power Factor
Correction (PFC) Controller in
Continuous Conduction Mode
(CCM)
Power Management & Supply
CCM-PFC
Revision History:
Datasheet
Edition 2010-05-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 05/05/10.
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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question, please contact the nearest Infineon Technologies Office.
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
CCM-PFC
ICE3PCS01G
Standalone Power Factor Correction
(PFC) Controller in Continuous
Conduction Mode (CCM)
Product Highlights
•
•
•
•
•
•
•
•
High efficiency over the whole load range
Lowest count of external components
Accurate and adjustable switching frequency
Bulk voltage good signal for inrush relay control or PWM IC enabling
Integrated digital voltage loop compensation
Fast output dynamic response during load jump
External synchronization
ICE3PCS01G
PG-DSO-14
Extra low peak current limitation
Features
Description
•
•
•
Continuous current operation mode PFC
Wide input range of Vcc up to 25V
The ICE3PCS01G is a 14-pins wide input range controller
IC for active power factor correction converters. It is de-
Programmable boost follower step level according signed for converters in boost topology, and requires few
to input line and output power conditions
external components. Its power supply is recommended to
•
Enhanced dynamic response without input current be provided by an external auxiliary supply which will
distortion
switch on and off the IC.
•
•
Accurate brown-out protection threshold
External current loop compensation for greater
user flexibility
•
•
•
•
•
Open loop protection
Second over bulk voltage protection
PFC enable function
Separate signal and power ground pins
Maximum duty cycle of 95% (typical)
DBYP
RNTC
DB
LBoost
VCC
RBVS 4
RGATE
RBVS 1
Line
CB
90 ~ 270 Vac
Filter
CE
RGS
RBVS 5
RBVS 2
RSHUNT
RBVS 6
RBVS 3
DBRO1
DBRO2
RCS
Qrel
RRel
RBRO1
VB_OK ISENSE
GATE
PGND
VSENSE
OVP
PWM
Feedback
RBRO2
BOP
RBOFO 1
BOFO
RBRO3
CBRO
VREF
SGND
VBTHL_EN FREQ ICOMP VCC
RBOFO 2
RVB 1
VCC
RVB 2
RFREQ
C
IC OMP
CVCC
Type
Package
ICE3PCS01G
PG-DSO-14
Version 2.0
3
5 May 2010
CCM-PFC
ICE3PCS01G
1
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . 10
Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Voltage Brownout Protection(BOP) . . . . . . . . . . . . . . . . . . . . . . . . 13
Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
First Over-Voltage Protection (OVP1) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Second Over Voltage Protection (OVP2) . . . . . . . . . . . . . . . . . . . . . . . . 14
Bulk Voltage Monitor and Enable Function . . . . . . . . . . . . . . . . . . . . . . 14
Boost Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.6.3
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.9
3.10
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PFC Brownout Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Boost Follower Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
4.3.9
Bulk Voltage Good Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.10
4.3.11
4.3.12
4.3.13
5
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Version 2.0
5
5 May 2010
CCM-PFC
ICE3PCS01G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration
1.2
Pin Functionality
BOFO (Boost Follower setting)
An external DC voltage to this pin indicating the PWM
output power which can be set to enter the Boost
follower low step.
Pin Symbol
Function
1
BOFO
ISENSE
SGND
Boost Follower Setting
Current Sense Input
2
ISENSE (Current Sense Input)
The ISENSE Pin senses the voltage drop at the
external sense resistor (RSHUNT). This is the input signal
for the average current regulation in the current loop. It
is also fed to the peak current limitation block.
3
Signal Ground
4
ICOMP
FREQ
Current Loop Compensation
Switching Frequency Setting
Bulk Voltage OK signal
5
During power up time, high inrush currents cause high
negative voltage drop at RSHUNT, driving currents out of
pin 2 which could be beyond the absolute maximum
ratings. Therefore a series resistor (RCS) of around 50Ω
is recommended in order to limit this current into the IC.
6
VB_OK
7
VBTHL_EN PFC Enable Function
8
VREF
BOP
OVP
Voltage Reference
9
Brownout Protection
Over Voltage Protection
SGND (Signal Ground)
The ground potential of the IC.
10
11
12
13
14
VSENSE Bulk Voltage Sense
VCC
GATE
PGND
IC Supply Voltage
Gate Drive
ICOMP (Current Loop Compensation)
Low pass filter and compensation of the current control
loop. The capacitor which is connected at this pin
integrates the output current of OTA6 and averages the
current sense signal.
Power Ground
FREQ (Frequency Setting)
This pin allows the setting of the operating switching
frequency by connecting a resistor to ground. The
frequency range is from 21kHz to 250kHz.
Package PG-DSO-14
VB_OK (Bulk Voltage OK signal)
BOFO
ISENSE
SGND
PGND
GATE
VCC
This pin is pulled up to 5V internally once the bulk
voltage is higher than 95% rated voltage and pulled
down to ground once VSENSE pin is lower than preset
VBTHL_EN threshold. This signal can enable the PWM
IC or control the inrush relay.
ICOMP
FREQ
VSENSE
OVP
P-DSO-14
VBTHL_EN
An external voltage reference can be applied to
VBTHL_EN to set the turn-off threshold of VB_OK
signal. The IC can be shut down by pulling the pin lower
than 0.5V
VB_OK
BOP
VBTHL_EN
VREF
VREF (Voltage Reference)
This pin is the 5V regulator output with a 5mA sourcing
Figure 1 Pin Configuration (top view)
current (minimum).
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
Pin Configuration and Functionality
BOP (Brownout Protection)
BOP monitors the AC input voltage for Brownout
Protection and line range selection
OVP
A resistive voltage divider from bulk voltage to SGND
can set the over voltage protection threshold. This
additional OVP is able to ensure system safety
operation.
VSENSE
VSENSE is connected via a resistive divider to the bulk
voltage. The voltage of VSENSE relative to SGND
represents the output voltage. The bulk voltage is
monitored for voltage regulation, over voltage
protection and open loop protection.
VCC
VCC provides the power supply of the ground related
to IC section.
GATE
GATE is the output for driving the PFC MOSFET.Its
gate drive voltage is clamped at 15V (typically).
PGND (Power Ground)
Gate switching ground.
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
Block Diagram
2
Block Diagram
A functional block diagram is given in Figure 2. Note that the figure only shows the brief functional block and does
not represent the implementation of the IC.
Figure 2 Block Diagram
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
Block Diagram
Table 1
Bill Of Material
Component
Rectifier Bridge
CE
Parameters
GBU8J
100nF/X2/275V
750uH
LBoost
QB
DBYP
DB
CB
DBRO1...2
RBRO1...2
RBRO3
CBRO
IPP60R199CP
MUR360
IDT04S60C
220µF/450V
1N4007
3.9MΩ
130kΩ
3µF
Rshunt
Cisense
RCS
30mΩ
1nF
50Ω
RGATE
RFREQ
CICOMP
RBVS1...2
RBVS3
RBVS4...5
RBVS6
RVB1
3.3Ω
67kΩ
4.7nF/25V
1.5MΩ
18.85kΩ
2MΩ
23kΩ
330kΩ
RVB2
200kΩ
CVREF
RBOFO1...2
100nF/25V
200kΩ
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
Functional Description
3
Functional
Description
VBULK
100%
95%
20%
3.1
General
VCC
26V
The ICE3PCS01G is a 14-pins control IC for power
factor correction converters. It is suitable for wide range
line input applications from 85 to 265 VAC with overall
efficiency above 90%. The IC supports converters in
boost topology and it operates in continuous
conduction mode (CCM) with average current control.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM) resulting in a higher harmonics but still meeting
the Class D requirement of IEC 1000-3-2.
12V
IVCC
<6.7mA
with 1nF external cap. at gate drive pin
3.5mA
5 mA
1.4mA
VREF
5V
VB_OK
5V
VREF rises to 5V with
100nF external cap.
within 200us
OVP
Bulk voltage rises to 95% rated value
within 200ms
Standby mode
Normal
UVLO
configuration
within 50us
(VVSENSE < 0.5V or VVBTHL < 0.5V)
operation
The outer voltage loop controls the output bulk voltage,
integrated digitally within the IC. Depending on the load
condition, internal PI compensation output is converted
to an appropriate DC voltage which controls the
amplitude of the average input current.
Figure 3 State of Operation respect to VCC
3.3
Start-up
During power up when the Vout is less than 95% of the
rated level, internal voltage loop output increases from
initial voltage under the soft-start control. This results in
a controlled linear increase of the input current from 0A
thus reducing the stress in the external components.
Once Vout has reached 95% of the rated level, the soft-
start control is released to achieve good regulation and
dynamic response and VB_OK pin outputs 5V
indicating PFC stage in normal operation.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device.
3.2
Power Supply
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
12.0V and both voltages at pin 11 (VSENSE) >0.5V
and pin 9 (BOP) >1.25V, the IC begins operating its
gate drive and performs its startup as shown in Figure
3.
3.4
Frequency Setting and External
Synchronization
If VCC drops below 11V, the IC is off. The IC will then
be consuming typically 1.4mA, whereas consuming
6.7mA during normal operation
The IC can provide external switching frequency
setting by an external resistor RFREQ and the online
synchronization by external pulse signal at FREQ pin.
The IC can be turned off and forced into standby mode
by pulling down the voltage at pin 11 (VSENSE) below
0.5V or the voltage at pin 7 (VBTHL_EN) below 0.5V.
3.4.1
Frequency Setting
The switching frequency of the PFC converter can be
set with an external resistor RFREQ at FREQ pin as
shown Figure 2. The pin voltage at VFREQ is typical 1V.
The corresponding capacitor for the oscillator is
integrated in the device and the RFREQ/frequency is
given in Figure 4. The recommended operating
frequency range is from 21kHz to 250kHz. As an
example, a RFREQ of 67kΩ at pin FREQ will set a
switching frequency FSW of 65kHz typically.
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
Functional Description
3.5
Voltage Loop
Frequency vs Resistance
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage VOUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from VOUT. The pin VSENSE is the input of
sigma-delta ADC which has an internal reference of
2.5V and sampling rate of 3.55kHz (typical). The
voltage loop compensation is integrated digitally for
better dynamic response and saving design effort.
Figure 6 shows the important blocks of this voltage
loop.
260
240
220
200
180
160
140
120
100
80
Resistance
/kohm
Frequency
/kHz
Resistance
/kohm
Frequency
/kHz
40
36
15
17
20
30
40
50
60
70
80
90
278
249
211
141
106
86
74
62
55
49
110
120
130
140
150
169
191
200
210
221
34
31.5
29.5
26.2
25
23
21.2
20.2
60
100
43
232
19.2
40
20
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250
Resistance/kohm
LBoost
DB
RBVS1
Figure 4
3.4.2
Frequency Versus RFREQ
External Synchronization
QB
Rectified
RGATE
RBVS2
Input Voltage
CB
The switching frequency can be synchronized to the
external pulse signal after 6 external pulses delay once
the voltage at the FREQ pin is higher than 2.5V. The
synchronization means two points. Firstly, the PFC
switching frequency is tracking the external pulse
signal frequency. Secondly, the falling edge of the PFC
signal is triggered by the rising edge of the external
pulse signal. Figure 5 shows the blocks of frequency
setting and synchronization. The external RSYN
combined with RFREQ and the external diode DSYN can
ensure pin voltage to be kept between 1.0V (clamped
externally) and 5V (maximum pin voltage). If the
external pulse signal has disappeared longer than
108µs (typical) the switching frequency will be
synchronized to internal clock set by the external
RBVS3
Gate Driver
Current Loop
+
PWM Generation
GATE
VIN
Sigma-
delta
ADC
Nonlinear
Gain
Notch
Filter
PI Filter
Av(IIN
)
2.5V
VSENSE
t
500 ns
OLP
OVP
C2a
C1a
C1b
0.5V
2.5V
2.7V
OVP
Q
R
resistor RFREQ
.
Q
S
Syn. clock
IOSC
1. 0V
Figure 6
3.5.1
Voltage Loop
Notch Filter
DSYN
OTA7
In the PFC converter, an averaged current through the
output diode of rectified sine waveform charges the
output capacitor and results in a ripple voltage at the
output capacitor with a frequency two times of the line
frequency. In this digital PFC, a notch filter is used to
remove the ripple of the sensed output voltage while
keeping the rest of the signal almost uninfluenced. In
this way, an accurate and fast output voltage regulation
without influence of the output voltage ripple is
achieved.
RSYN
C9
SYN
R
FREQ
FREQ
2.5V/1.25V
Figure 5
Frequency Setting and
Synchronization
3.5.2
Voltage Loop Compensation
The Proportion-Integration (PI) compensation of the
voltage loop is integrated digitally inside the IC. The
digital data out of the PI compensator is converted to
analog voltage for current loop control.
Version 2.0
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5 May 2010
CCM-PFC
ICE3PCS01G
Functional Description
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
LBoost
DB
output voltage of integrated PI compensator. This block
has been designed to reduce the voltage loop
dependency on the input voltage in order to support the
wide input voltage range (85VAC-265VAC). Figure 7
gives the relative output power transfer curve versus
the digital word from the integrated PI compensator.
The output power at the input voltage of 85VAC and
maximum digital word of 256 from PI compensator is
set as the normative power and the power curves at
different input voltage present the relative power to the
normative one.
QB
Rectified
RGATE
Input Voltage
CB
Rshunt
GATE
RCS
Current Loop
voltage
proportional to
averaged
Gate
Inductor current
Driver
ISENSE
ICOMP
Current Loop
Compensation
PWM
power at 85V
power at 265V
Comparator
Q
R
S
10.00000
1.00000
0.10000
0.01000
0.00100
0.00010
0.00001
C10
OTA6
5.0mS
PWM Logic
CICOMP
+/-50uA (linear range)
S2
5V
Input From
Nonlinear
Gain
Voltage Loop
Fault
Figure 8
3.6.2
Complete System Current Loop
Current Loop Compensation
0
18
37
55
73
91 110 128 146 165 183 201 219 238 256
The compensation of the current loop is implemented
at the ICOMP pin. This is OTA6 output and a capacitor
CICOMP has to be installed at this node to ground (see
Figure 8). Under normal mode of the operation, this pin
gives a voltage which is proportional to the averaged
inductor current. This pin is internally shorted to 5V in
the event of standby mode.
PI digital output
Figure 7
Power Transfer Curve
3.6
Average Current Control
The choke current is sensed through the voltage
across the shunt resistor and averaged by the ICOMP
pin capacitor so that the IC can control the choke
current to track the instant variation of the input voltage.
3.6.3
Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous mode (CCM) to achieve the power factor
correction. Assuming the loop voltage is working and
output voltage is kept constant, the off duty cycle DOFF
for a CCM PFC system is given as:
3.6.1
Complete Current Loop
The complete system current loop is shown in Figure 8.
It consists of the current loop block which averages the
voltage at ISENSE pin resulted from the inductor
current flowing across Rshunt. The averaged waveform
is compared with an internal ramp in the ramp
generator and PWM block. Once the ramp crosses the
average waveform, the comparator C10 turns on the
driver stage through the PWM logic block. The
Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
DOFF=VIN/VOUT
From the above equation, DOFF is proportional to VIN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle DOFF, and thus to the input voltage
VIN. Figure 9 shows the scheme to achieve the
objective.
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Functional Description
immediately and maintained in off state for the current
PWM cycle. The signal TOFFMIN resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Ramp Profile
Ave(Iin) at ICOMP
Current
Toff_min
limit Latch
600ns
R
S
Q
Q
High = turn on Gate
Peak current limit
Gate
Drive
t
PWM on
Latch
R
Q
Current loop
PWM on signal
Figure 9
Average Current Control in CCM
S
Q
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 4
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of TOFFMIN (600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
TOFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
Figure 11
PWM LOGIC
3.8
System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
and the off duty cycle DOFF
.
Figure 10 shows the timing diagrams of the TOFFMIN and
3.8.1
Input Voltage Brownout Protection(BOP)
the gate waveforms.
Brownout occurs when the input voltage VIN falls below
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the VCC has not
entered into the VCCUVLO level yet. For a system without
BOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
T
off_min 600 ns
Clock
PWM Cycle
(1 )
VC,ref
ICE3PCS01G provides a new BOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network shown in Figure 12. This network provides a
filtered value of VIN which turns the IC on when the
voltage at pin 9 (BOP) is more than 1.25V. The IC
enters into the fault mode when BOP goes below 1.0V.
The hysteresis prevents the system to oscillate
between normal and fault mode. Note also that the
peak of VIN needs to be at least 20% of the rated VOUT
in order to overcome OLP and powerup system.
Vramp
Ramp
Released
GATE
t
(1)
Vc,ref is a function of VICOMP
Figure 10
Ramp and PWM waveforms
3.7
PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse TOFFMIN, are
designed to meet a maximum duty cycle DMAX of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
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Functional Description
VSENSE pin with respect to a reference voltage of
2.7V. A VSENSE voltage higher than 2.7V will
immediately turn off the gate, thereby preventing
damage to bus capacitor. After bulk voltage falls below
the rated value, gate drive resumes switching again.
Line
Filter
90 ~ 270 Vac
DBRO2
DBRO1
3.8.5
Second Over Voltage Protection (OVP2)
The second OVP is provided in case that the first one
fails due to the aging or incorrect resistors connected to
the VSENSE pin. This is implemented by sensing the
voltage at pin OVP with respect to a reference voltage
of 2.5V. When voltage at OVP pin is higher than 2.5V,
the IC will immediately turn off the gate, thereby
preventing damage to bus capacitor.
RBRO1
1.25V
C8b
C8a
Brownout
Latch
RBRO2
BOP
CBRO
Brownout
R
Q
S
Q
RBRO3
1V
When the bulk voltage drops out of the hysteresis the
IC can be latched further or begin auto soft-start. These
two protection modes are distinguished through
detecting the external equivalent resistance connecting
to VBTHL_EN pin after Vcc is higher than UVLO
threshold as shown in Figure 3. If the equivalent
resistance is higher than 100kΩ the IC selects latch
mode for second OVP, otherwise auto soft-start mode.
In normal operation the trigger level of second OVP
should be designed higher than the first. However in
the condition of mains transient overshoot the bulk
voltage may be pulled up to the peak value of mains
that is higher than the threshold of OVP1 and OVP2. In
this case the OVP1 and OVP2 are triggered in the
same time the IC will shut down the gate drive until bulk
voltage falls out of the two protection hysteresis, then
resume the gate drive again.
Figure 12
3.8.2
Input Brownout Protection
Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 2 (ISENSE)
reaches -0.2V. This voltage is amplified by a factor of -
5 and connected to comparator with a reference
voltage of 1.0V as shown in Figure 13. A deglitcher with
200ns after the comparator improves noise immunity to
the activation of this protection.
Full-wave
rectifier
ISENSE
RCS
3.8.6
Bulk Voltage Monitor and Enable
Function
G=-5
200ns
AO2
PCL
The IC monitors the bulk voltage through VSENSE pin
and output a TTL signal to enable PWM IC or control
inrush relay. During soft-start, once the bulk voltage is
higher than 95% rated value, pin VB_OK outputs a high
level. The threshold to trigger the low level is decided
by the pin VBTHL_EN voltage which can be adjustable
externally.
Rshunt
Iin
C5
1V
SGND
When pin VBTHL_EN is pulled down externally lower
than 0.5V, IC will enters into standby mode and most of
the function blocks are turned off. When the disable
signal is released the IC recovers by soft-start.
Figure 13 Peak Current Limit (PCL)
3.8.3 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.5V, or
equivalently VOUT falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage VIN for
normal operation. It is implemented using comparator
C2a with a threshold of 0.5V as shown in the IC block
diagram in Figure 6.
3.8.7
Boost Follower
The IC provides adjustable lower bulk voltage in case
of low line input and light output power. The low line
condition is determined when pin BOP voltage is less
than 2.3V. Pin BOFO is connected to PWM feedback
voltage through a voltage divider, representing the
output power. The light load condition is determined
when pin BOFO voltage is less than 0.5V. Once these
two conditions are met in the same time, a 20µA
current source is flowing out of pin VSENSE so that the
bulk voltage should be reduced to a lower level in order
3.8.4
First Over-Voltage Protection (OVP1)
Whenever VOUT exceeds the rated value by 8%, the
over-voltage protection OVP1 is active as shown in
Figure 6. This is implemented by sensing the voltage at
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ICE3PCS01G
Functional Description
to keep the VSENSE voltage same as the internal
reference 2.5V as shown in Figure 14.
VCC
Reg (17V)
Gate Driver
DBRO2
VDD
BOP
PWM Logic
HIGH to
turn on
90 ~ 270 Vac
RBR O1
RBRO2
VBulk
20uA
Blanking time
L2H 34us
H2L 1us
DBR O1
C7
C6
RBRO
3
2.3/
CBRO
LV
Z1
2. 5V
RBVS1
External
MOS
VSENSE
0.5V
RBVS 2
Blanking time
H2L 4ms
BOFO
Rpullup
RBOFO1
L2H 32ms
VCC
RBVS 3
RBOFO2
Opto.
RBOFO3
GATE
GND
* LV: Level Shift
Figure 14
Boost Follower
Figure 15 Gate Driver
The reduced bulk voltage can be designed by upper
side resistance of voltage divider from pin VSENSE.
Thus the low side resistance is designed by the voltage
divider ratio from the reference 2.5V to the rated bulk
voltage. A internal 300kΩ resistor will be paralleled with
external low side resistor of BOFO pin to provide the
adjustable hysteresis for PWM feedback voltage when
boost follower is activated.
The boost follower feature will be disabled internally
during PFC soft-start in order to prevent bulk voltage
oscillation due to the unstable PWM feedback voltage.
This feature can also be disabled externally by pulling
up pin BOFO higher than 0.5V continuously.
3.9
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 15) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 13 (GATE) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the gate
drive is internally pull low to maintain the off state.
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ICE3PCS01G
Functional Description
3.10
Protection Function
Description of Fault
Fault-Type Min. Duration Consequence
of Effect
Voltage at Pin ISENSE <
-200mV
PCL
200 ns
20 µs
1 µs
Gate Driver is turned off immediately during
current switching cycle
Voltage at Pin BOP < 1V
BOP
Gate Driver is turned off. Soft-restart after BOP
voltage > 1.25V
Voltage at Pin VSENSE < 0.5V OLP
Power down. Soft-restart after VSENSE voltage
> 0.5V
Voltage at Pin VSENSE < 0.8V OLP
when boost follower is active
1 µs
Disable boost follower function.
Voltage at Pin VSENSE >
108% of rated level
OVP1
12 µs
12 µs
Gate Driver is turned off until VSENSE voltage <
2.5V.
Voltage at Pin OVP > 2.5V and OVP1 and
Voltage at Pin VSENSE >
108% of rated level
Gate Driver is turned off until bulk voltage drops
out of both OVP hysteresis
OVP2
Voltage at Pin OVP > 2.5V
OVP2(latch 12 µs
mode)
Latched fault mode. Soft-restart after VCC UVLO
Voltage at Pin OVP > 2.5V
OVP2
(auto-
restart
mode)
12 µs
Gate Driver is turned off. Soft-restart after OVP
voltage < 2.3V
Voltage at Pin VBTHL_EN <
0.5V after VCC > 7V
OVP2mode 18 µs
detection
IC enters soft-restart mode after OVP2
released.
Voltage at Pin VBTHL_EN >
0.5V after VCC > 7V
OVP2mode 18 µs
detection
IC enters latch mode after OVP2 released.
Voltage at Pin VBTHL_EN <
0.5V when Vref outputs 5V
Disable
function
9 µs
Power down. Soft-restart after disable signal is
released.
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ICE3PCS01G
Electrical Characteristics
4
Electrical Characteristics
All voltages are measured with respect to ground (pin 3). The voltage levels are valid if other ratings are not
violated.
4.1
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the
integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 12 (VCC) is
discharged before assembling the application circuit.
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
-0.3
-0.3
Max.
26
VCC Supply Voltage
GATE Voltage
VVCC
V
VGATE
17
V
Clamped at 15V if
driven internally.
1)
ISENSE Voltage
ISENSE Current
VSENSE Voltage
VSENSE Current
ICOMP Voltage
FREQ Voltage
VISENSE
IISENSE
VVSENSE
IVSENSE
VICOMP
VFREQ
VVREF
VBOP
-20
-1
5.3
1
V
mA
V
-0.3
-1
5.3
1
mA
V
-0.3
-0.3
-0.3
-0.3
-1
5.3
5.3
VVREF_0A
9.5
35
V
VREF Voltage
V
2)
BOP Voltage
V
BOP Current
IBOP
µA
V
VB_OK Voltage
VBTHL/EN Voltage
BOFO Voltage
VVB_OK
VVBTHL
VBOFO
VOVP
-0.3
-0.3
-0.3
-0.3
-40
-55
5.3
5.3
5.3
5.3
150
150
140
260
2
V
V
OVP Voltage
V
Junction Temperature
Storage Temperature
Thermal Resistance
Soldering Temperature
TJ
°C
°C
TA,STO
RTHJA
TSLD
K/W Junction to Air
°C Wave Soldering3)
kV Human Body Model4)
ESD Capability
VESD
1)
Absolute ISENSE current should not be exceeded
Absolute BOP current should not be exceeded
According to JESD22A111
2)
3)
4)
According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5kΩ series resistor)
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Electrical Characteristics
4.2
Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
VVCC,OFF
-25
Max.
25
VCC Supply Voltage @ 25°C
Junction Temperature
VVCC
TJ
V
TJ=25°C
125
250
°C
PFC switching frequency
FPFC
21
kHz
4.3
Characteristics
Note: The electrical Characteristics involve the spread of values given within the specified supply voltage and
junction temperature range TJ from -25 °C to 125 °C. Typical values represent the median values, which
are related to 25 °C. If not otherwise stated, a supply voltage of VVCC = 18V, a typical switching frequency
of ffreq=65kHz are assumed and the IC operates in active mode. Furthermore, all voltages are referring to
GND if not otherwise mentioned.
4.3.1
Supply Section
Parameter
Symbol
Limit Values
Unit Note/Test Condition
Min.
Typ.
Max.
VCC Turn-On Threshold
VCCon
11.5
12
12.9
11.9
1.45
V
V
V
VCC Turn-Off Threshold/
Under Voltage Lock Out
VCCUVLO
VCChy
10.5
11.0
1
VCC Turn-On/Off Hysteresis
0.7
Start Up Current
Before VCCon
ICCstart1
ICCstart2
ICCHG
-
-
380
1.4
6.7
3.5
700 µA
VCCon-1.2V
Start Up Current
Before VCCon
2.4
9
mA VCCon-0.2V
mA CL= 1nF
Operating Current with active GATE
-
Operating Current during Standby
ICCStdby
-
4.7
mA VVSENSE= 0.4V
V
ICOMP= 4V
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Electrical Characteristics
4.3.2
Variable Frequency Section
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
Switching Frequency (Typical)
Switching Frequency (Min.)
Switching Frequency (Max.)
Voltage at FREQ pin
FSWnom
FSWmin
FSWmax
VFREQ
Dmax
62.5
65
67.5 kHz R5 = 67kΩ
-
-
21
250
1
-
kHz R5 = 212kΩ
kHz R5 = 17kΩ
V
-
-
-
Max. Duty Cycle
93
95
98.5
%
f
SW=fSWnom
(RFRE=67kΩ)
4.3.3
PWM Section
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
Min. Duty Cycle
Min. Off Time
DMIN
0
%
VVSENSE= 2.5V
ICOMP= 4.3V
V
TOFFMIN
310
600
920
ns
VVSENSE= 2.5V
ISENSE= 0V
(R5 = 67kΩ)
V
4.3.4
External Synchronization
Parameter
Symbol
Values
Typ.
2.5
Unit Note / Test Condition
Min.
Max.
150
Detection threshold of external clock
Synchronization range
Vthr_EXT
V
fEXT_range
50
kHz
Synchronization frequency ratio
f
EXT:fPFC
1:1
propagation delay from rising edge of
external clock to falling edge of PFC
gate drive
TEXT2GATE
500
ns
%
fEXT=65kHz
Allowable external duty on time
TD_on
10
70
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Electrical Characteristics
4.3.5
PFC Brownout Protection Section
Parameter
Symbol
Values
Typ.
1
Unit Note / Test Condition
Min.
Max.
Input Brownout Protection High to Low
Threshold
VBOP_H2L
VBOP_L2H
0.98
1.02
V
V
Input Brownout Protection Low to High
Threshold
1.2
1.25
1.3
0.5
Blanking time for BOP turn_on
TBOPon
IBOP
20
-
µs
Input Brownout Protection BOP Bias
Current
-0.5
µA
VBOP=1.25V
4.3.6
System Protection Section
Parameter
Symbol
Values
Typ.
2.7
Unit Note / Test Condition
Min.
Max.
Over Voltage Protection (OVP1) Low to VOVP1_L2H
High
2.65
2.45
150
2.77
2.55
270
V
V
108%VBULKRated
Over Voltage Protection (OVP1) High to VOVP1_H2L
Low
2.5
Over Voltage Protection (OVP1)
Hysteresis
VOVP1_HYS
200
mV
Blanking time for OVP1
TOVP1
12
µs
Over Voltage Protection (OVP2) Low to VOVP2_L2H
High
2.45
2.25
2.5
2.55
2.35
V
Over Voltage Protection (OVP2) High to IOVP2_H2L
Low
2.3
V
Blanking time for OVP2
TOVP2
12
0.5
5
µs
OVP2 mode detection threshold
VOVP2_mode
IOVP2_mode
V
comparator at VBTHL pin
Current source for OVP2 mode
detection1)
4
6
µA current source at VBTHL
pin
Peak Current Limitation (PCL) ISENSE VPCL
Threshold
-180
-200
-220 mV
Blanking time for PCL turn_on
TPCLon
200
ns
1)
The parameter is not subject to production test - verified by design/characterization
4.3.7
Internal Voltage Reference
Parameter
Symbol
Values
Typ.
5
Unit Note / Test Condition
Min.
Max.
5.1
50
Output Reference Voltage
Load Regulation
VVREF_0A
4.9
V
IVREF=0mA
∆VVREF_5mA
∆VVREF_VCC
mV IVREF=-5mA1)
Line Regulation
25
mV ∆VCC=3V
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Electrical Characteristics
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
Max.
Maximum Source Current
Temperature Stability
IVREF
-6
mA
%
∆VVREF_temp
VVREF_total
1.0
Total Variation
4.85
5.2
Line, Load, Temperature
1)
Maximum pulling current depends on the maximum operating junction temperature
4.3.8
Boost Follower Section
Parameter
Symbol
Values
Typ.
0.5
300
32
Unit Note / Test Condition
Min.
0.47
240
Max.
0.53
360
BOFO threshold
VBOFO
V
kΩ
ms
ms
V
BOFO hysteresis resistor
Blanking time for BOFO on
Blanking time for BOFO off
High line detection threshold
Low line detection threshold
Blanking time for line detection
Current source for low step
RBOFO_hys
TBOFO_L2H
TBOFO_H2L
VLD_H
4
2.46
2.25
2.5
2.3
32
2.56
2.35
VLD_L
V
TLD
µs
µA
IBOFO
18.7
20
21
4.3.9
Bulk Voltage Good Section
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Min.
Max.
VB_OK turn-on threshold
VB_OK turn-off threshold
Disable function threshold
Blanking time for disable function
VVBOKon
VVBOKoff
VVBTHL_EN 0.45
TVBTHL_EN
IVB_OKMax
2.25
2.375
VVBTHL_EN
0.5
2.5
V
V
sensed at pin VSENSE
set by pin VBTHL_EN
0.55
V
9
µs
mA
VB_OK max source current
-11)
1)
shared with the max source current of the VREF pin.
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Electrical Characteristics
4.3.10
Current Loop Section
Parameter
Symbol
Values
Typ.
5.0
Unit Note / Test Condition
Min.
Max.
OTA6 Transconductance Gain
OTA6 Output Linear Range1)
GmOTA6
IOTA6
3.5
6.35
mS At Temp = 25°C
± 50
5.0
µA
ICOMP Voltage during OLP
VICOMPF
4.8
5.2
V
VVSENSE= 0.4V
1)
The parameter is not subject to production test - verified by design/characterization
4.3.11
Voltage Loop Section
Parameter
Symbol
Values
Typ.
2.5
Unit Note / Test Condition
Min.
2.47
0.45
Max.
2.53
0.55
Trimmed Reference Voltage
VVSREF
V
V
±1.2%
Open Loop Protection (OLP) VSENSE VVS_OLP
Threshold
0.5
VSENSE Input Bias Current
IVSENSE
-1
-
1
µA
VVSENSE= 2.5V
4.3.12 Driver Section
Parameter
Symbol
Values
Typ.
-
Unit Note / Test Condition
Min.
Max.
GATE Low Voltage
VGATEL
-
1.2
V
VCC =10V
I
I
I
I
GATE = 5 mA
-
0.4
-
-
1.4
-
V
V
V
V
GATE = 0 A
-
GATE = 20 mA
GATE = -20 mA
-0.2
-
0.8
15
GATE High Voltage
VGATEH
-
V
CC = 25V
CL = 1nF
-
12.4
-
-
-
V
V
V
CC = 15V
CL = 1nF
8.0
V
CC = VVCCoff + 0.2V
CL = 1nF
4.3.13
Gate Drive Section
Parameter
Symbol
Values
Typ.
30
Unit Note / Test Condition
Min.
Max.
GATE Rise Time
GATE Fall Time
tr
tf
-
-
ns
ns
V
Gate = 20% - 80%
VGATEH CL = 1nF
-
25
-
V
Gate = 80% - 20%
VGATEH CL = 1nF
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ICE3PCS01G
Outline Dimension
5
Outline Dimension
PG-DSO-14 Outline Dimension
±0.08
0.33
x 45˚
1)
4 -0.2
1.27
+0.1
-0.06
C
±0.25
0.1
0.64
0.41
±0.2
M
0.2 A C 14x
6
14
1
8
7
1)
8.75 -0.2
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
Notes:
1. You can find all of our packages, sorts of packing and others in our Infineon
Internet Page “Products”: http://www.infineon.com/products.
2. Dimensions in mm.
Version 2.0
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Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere Anstrengungen gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Quality takes on an allencompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Dazu gehört eine bestimmte
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener
Sichtweise auch über den eigenen
Arbeitsplatz hinaus – und uns ständig
zu verbessern.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit den entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe
Leistung durch umfassende Qualität zu
beweisen.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.
Wir werden Sie überzeugen.
h t t p : / / w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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