ICS94235YFT [ICSI]
PROGRAMMABLE SYSTEM CLOCK CHIP FOR AMD-K7 TM PROCESSOR; 可编程系统时钟芯片， AMD- K7 TM处理器
| 型号： | ICS94235YFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PROGRAMMABLE SYSTEM CLOCK CHIP FOR AMD-K7 TM PROCESSOR |
| 文件： | 总19页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94235
Integrated
Circuit
Systems, Inc.
Recommended Application:
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RESET#
*PD#
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
CPUCLKT0
CPUCLKC0
CPUCLKT1
SDATA
SDRAM0
SDRAM1
GND
•
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
7 - PCI @ 3.3V
2 - AGP @ 3.3V
X1
X2
AVDD
**FS0/REF0
VDD
**FS1/AGP0
AGP1
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
1 - 48MHz, @3.3V
GND
1 - REF @ 3.3V, (selectable strength) through I2C
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
Features:
GND
•
•
•
•
•
Programmable ouput frequency
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
Programmable ouput rise/fall time
Programmable CPU, SDRAM, PCI and AGP skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
*MODE/PCICLK3
PCICLK4
PCICLK5
AVDD48
**FS3/48MHz
GND
VDD
SDRAM10(PCI_STOP#)*
SDRAM11
SDRAM12
SCLK
•
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
48-Pin 300mil SSOP &
240mil TSSOP package
•
Skew Specifications:
•
•
•
•
•
•
•
CPUT - CPUC: <250ps
PCI - PCI: <500ps
CPU - SDRAM: <350ps
SDRAM - SDRAM: <250ps
AGP - AGP: <250ps
AGP - PCI: <750ps
CPU - PCI: <3ns
Block Diagram
Functionality
FS3
0
0
0
FS2
0
0
0
FS1
0
0
1
FS0
0
1
CPU SDRAM PCI
66.66 66.66 33.33 66.66
66.66 100.00 33.33 66.66
100.00 66.66 33.33 66.66
AGP
PLL2
48MHz
REF0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
100.00 100.00 33.33 66.66
100.00 133.33 33.33 66.66
120.00 120.00 30.00 60.00
133.33 100.00 33.33 66.66
133.33 133.33 33.33 66.66
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKT (1:0)
CPUCLKC0
2
90.00
100.90 100.90 33.63 67.27
100.00 66.66 33.33 66.66
90.00
30.00 60.00
SDRAM
DIVDER
Stop
Stop
SDRAM (12:0)
13
6
Control
Logic
SDATA
SCLK
PCI
DIVDER
100.00 100.00 33.33 66.66
100.00 133.33 33.33 66.66
126.00 126.00 31.50 63.00
133.33 100.00 33.33 66.66
133.33 133.33 33.33 66.66
PCICLK (5:0)
PCICLK_F
AGP (1:0)
FS (3:0)
Config.
Reg.
AGP
DIVDER
PD#
PCI_STOP#
MODE
Stop
2
RESET#
1
1
1
1
Power Groups
94235 Rev
A 01/17/02
Third party brands and names are the property of their respective owners.
ICS94235
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Real time system reset signal for frequency value or watchdog timmer
timeout. This signal is active low.
1
RESET#
PD#1
OUT
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
2
IN
4
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
5
OUT
3, 11, 16, 23, 29,
34, 41, 48
8, 17, 28, 35, 40
6
GND
PWR
Ground pins
VDD
PWR
PWR
IN
Power supply pins, nominal 3.3V
AVDD
FS02,
REF0
FS12, 3
Analog power supply pin, nominal 3.3V
Frequency select pin.
3
7
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
9
AGP0
OUT
OUT
OUT
IN
AGP outputs defined as 2X PCI. These may not be stopped.
AGP outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
10
12
AGP1
PCICLK_F
FS21, 3
PCICLK
(5:4) (2:0)
PCICLK3
MODE1, 3
AVDD48
FS32, 3
20, 19, 15, 14, 13
OUT
PCI clock outputs.
OUT
IN
PCI clock output.
18
21
22
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
Analog power supply pin, nominal 3.3V
Frequency select pin.
PWR
IN
48MHz
OUT
IN
48MHz output clock
Clock input of I2C input, 5V tolerant input
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
24
27
SCLK
PCI_STOP#1
SDRAM10
IN
OUT
SDRAM clock output.
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
SDRAM
OUT
SDRAM clock outputs.
(12:11, 9:0 )
Data pin for I2C circuitry 5V tolerant
44
SDATA
I/O
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
45, 47
46
CPUCLKT (1:0)
OUT
CPUCLKC0
OUT
Third party brands and names are the property of their respective owners.
ICS94235
General Description
Mode Pin - Power Management Input Control
MODE, Pin 18
Pin 27
(Latched Input)
PCI_STOP#
0
(Input)
SDRAM10
(Output)
1
Third party brands and names are the property of their respective owners.
ICS94235
General I2C serial interface information for the ICS94235
How to Write:
How to Read:
How to Read:
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D3(H)
Address D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B8
Byte18
Byte 19
Byte 20
ACK
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
Third party brands and names are the property of their respective owners.
ICS94235
Brief I2C registers description for ICS94235
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status and
programmable ’safe’frequency’can be
configured in this register.
Watchdog Control Registers 10 Bit [6:0]
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
VCO Control Selection Bit
10 Bit [7]
0
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
VCO Frequency Control
Registers
11-12
13-14
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Third party brands and names are the property of their respective owners.
ICS94235
Serial Configuration Command Bitmap
Bit
Description
PWD
FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK AGP
Spread Precentage
Bit2 Bit7 Bit6 Bit5 Bit4
(MHz)
66.66
66.66
100.00
100.00
100.00
120.00
133.33
133.33
90.00
(MHz)
66.66
100.00
66.66
100.00
133.33
120.00
100.00
133.33
90.00
(MHz) (MHz)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
33.33
33.33
33.33
33.33
33.33
30.00
33.33
33.33
30.00
33.63
33.33
33.33
33.33
31.50
33.33
33.33
34.00
34.00
34.00
34.00
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.66
35.66
33.40
36.66
36.66
66.66
66.66
66.66
66.66
66.66
60.00
66.66
66.66
60.00
67.27
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
100.90
100.00
100.00
100.00
126.00
133.33
133.33
102.00
102.00
136.00
136.00
103.00
103.00
137.33
137.33
105.00
105.00
140.00
107.00
107.00
133.90
110.00
146.66
100.90
66.66
66.66 0 to -0.5% Down Spread
66.66 0 to -0.5% Down Spread
66.66 0 to -0.5% Down Spread
100.00
133.33
126.00
100.00
133.33
102.00
136.00
102.00
136.00
103.00
137.33
103.00
137.33
105.00
140.00
140.00
107.00
142.66
133.90
110.00
146.66
63.00
+/- 0.25% Center Spread
66.66 0 to -0.5% Down Spread
66.66 0 to -0.5% Down Spread
Bit 2,
Bit 7:4
00000
Note1
67.99
67.99
67.99
67.99
68.66
68.66
68.66
68.66
69.99
69.99
69.99
71.33
71.33
66.95
73.33
73.33
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
0
0
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Third party brands and names are the property of their respective owners.
ICS94235
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
MODE#
BIT PIN# PWD
DESCRIPTION
-
X
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
X
1
1
1
1
FS3#
20
19
18
15
14
13
12
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
10
9
AGP1
AGP0
48MHz
22
43
SDRAM0
REF0 - 1X or 2X
default = 1=1X
CPUCLKT0, CPUCLKC0
Bit 2
7
1
Bit 1 47, 46
1
1
Bit 0
45
CPUCLKT1
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
PWD
DESCRIPTION
FS0#
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
X
X
X
1
-
0
1
1
1
1
1
1
1
Reserved
Reserved
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
-
FS1#
-
-
FS2#
39
38
37
36
33
32
31
30
27
26
25
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
1
1
1
1
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
42
SDRAM1
Third party brands and names are the property of their respective owners.
ICS94235
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to how many
290ms the watchdog timer will wait
before it goes to alarm mode and
reset the frequency to the safe
setting. Default at power up is
16X 290ms = 4.64 seconds.
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Third party brands and names are the property of their respective owners.
ICS94235
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
1
0
0
CPUCLKT/C0 Skew Control
CPUCLKT1
PCICLK (5:0, F) Skew Control
SDRAM0 Skew Control
SDRAM (12:1) Skew Control
AGP (1:0) Skew Control
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
CPUCLKT/C0 Slew Rate Control
SDRAM0 Skew Control
CPUCLKT1 Slew Rate Control
PCICLK_F Slew Rate Control
PCICLK (5:0) Slew Rate Control
SDRAM (12:1) Skew Control
AGP (1:0) Slew Rate Control
48MHz Slew Rate Control
Third party brands and names are the property of their respective owners.
ICS94235
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Third party brands and names are the property of their respective owners.
ICS94235
Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Ouput Parameters.
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2
VDD+0.3
V
Input Low Voltage
Input High Current
VIL
IIH
VSS-0.3
0.8
5
V
VIN = VDD
uA
Input Low Current
Input Low Current
IIL1
IIL2
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
uA
uA
-200
Operating
IDD3.3OP66
IDD3.3OP100
CL = 0 pF; Select @ 66MHz
CL = 0 pF; Select @ 66MHz
Supply Current
180
mA
IDD3.3OP133
CL = 0 pF; Select @ 133MHz
VDD = 3.3 V;
Power Down
PD
Fi
600
16
uA
Input frequency
12
27
14.318
MHz
Input Capacitance1
Clk Stabilization1
Skew1
CIN
Logic Inputs
X1 & X2 pins
5
pF
pF
CINX
45
TSTAB
From VDD = 3.3 V to 1% target Freq.
VT = 50%
3
ms
tAGP-PCI
tCPU-SDRAM
tCPU-PCI
300
200
2.67
750
350
3
ps
ns
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
ICS94235
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX
UNITS
Output Impedance
ZO
VO = VX
Ohms
Output High Voltage
VOH2B
Termination to Vpull-up(external)
1.2
0.4
V
Output Low Voltage
Output Low Current
Rise Time1
VOL2B
IOL2B
tr2B
Termination to Vpull-up(external)
VOL = 0.3V
V
mA
ns
ns
18
VOL = 0.3V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
Fall Time1
tf2B
0.913
Vpullup(external)
0.6
Vpullup(external)
0.6
Differential Voltage-AC1
Differential Voltage-DC1
VDIF
VDIF
0.4
0.2
V
V
Note 2
Note 2
Differential Crossover Voltage1
Duty Cycle1
VX
550
45
1100
55
mV
%
Note 3
dt2B
VT = 50%
53
Skew1
tsk2B
VT = 50%
250
ps
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
tjcyc-cyc2B
tjabs2B
VT = VX
201
250
250
ps
ps
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the TRUE
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max = (Vpullup(external)/2)+150mV.
Third party brands and names are the property of their respective owners.
ICS94235
Electrical Characteristics - PCICLK
TA = 0 - 70º C VDD = 3.3V +/-5%; C = 30pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
V
2.6
IOL = 9.4 mA
0.4
-16
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
19
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5V
1.63
1.63
51.9
170
2
2
Fall Time1
tf1
ns
Duty Cycle1
dt1
55
500
%
Skew1
Tsk1
VT = 1.5V
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
V
2.6
12
45
IOL = 9.4 mA
0.4
-12
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
tr1
VOL = 0.4 V, VOH =2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.63
1.63
49.7
170
2
2
Fall Time1
tf1
ns
Duty Cycle1
dt1
55
500
%
Skew1(window)
T
sk1
VT = 50%
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
ICS94235
Electrical Characteristics - 48MHz, REF0
TA = 0 - 70º C; VDD = 3.3V +/-5%, VDDL = 2.5 V +/-5%; CL = 20pF (otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
IOH = -16 mA
MIN
TYP
MAX
UNITS
V
2.4
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.23
1.21
53
2
2
Fall Time1
tf5
ns
Duty Cycle1
dt5
45
-1
55
0.5
1
%
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
595
ns
VT = 1.5 V
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM (12:0)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH3
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
Output High Voltage
Output Low Voltage
2
V
V
VOL3
IOL = 11 mA
0.4
-12
Output High Current
Output Low Current
Rise Time1
IOH3
IOL3
Tr3
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
12
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
0.88
0.8
2.2
2.2
55
Fall Time1
Tf3
ns
Duty Cycle1
Dt3
45
51.2
205
%
Skew1(window)
Tsk1
VT = 50%
250
ps
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
ICS94235
Shared Pin Operation -
Input/Output Pins
Via to
VDD
Programming
Header
2K
Via to Gnd
Device
Pad
8.2K
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
ICS94235
PD# Timing Diagram
Third party brands and names are the property of their respective owners.
ICS94235
PCI_STOP# Timing Diagram
Third party brands and names are the property of their respective owners.
ICS94235
c
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
L
A
A1
b
2.413
0.203
0.203
0.127
2.794
0.406
0.343
0.254
.095
.008
.008
.005
.110
.016
E1
E
INDEX
AREA
.0135
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
1
2
E1
e
h x 45°
0.635 BASIC
0.025 BASIC
D
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
A
0°
8°
0°
8°
A1
- C -
VARIATIONS
D mm.
D (inch)
SEATING
PLANE
N
b
MIN
MAX
MIN
.620
MAX
.630
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS94235yFT
ICS XXXX y F - T
Third party brands and names are the property of their respective owners.
ICS94235
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
aaa
-
0.10
-
.004
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.488
MAX
48
12.40
.496
7/6/00 Rev B
12.60
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS94235yGT
ICS XXXX y G - T
Third party brands and names are the property of their respective owners.
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