ICS94235YGLFT [IDT]
Processor Specific Clock Generator, 146.66MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48;
| 型号： | ICS94235YGLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 146.66MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94235
Integrated
Circuit
Systems, Inc.
Programmable System Clock Chip forAMD - K7 processor
Recommended Application:
ALI 1647 style chipset
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RESET#
*PD#
GND
X1
X2
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
Output Features:
CPUCLKT0
CPUCLKC0
CPUCLKT1
SDATA
SDRAM0
SDRAM1
GND
•
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
7 - PCI @ 3.3V
2 - AGP @ 3.3V
**FS0/REF0
VDD
**FS1/AGP0
AGP1
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
1 - 48MHz, @3.3V
GND
1 - REF @ 3.3V, (selectable strength) through I2C
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
Features:
GND
•
•
•
•
•
Programmable ouput frequency
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
Programmable ouput rise/fall time
Programmable CPU, SDRAM, PCI and AGP skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
*MODE/PCICLK3
PCICLK4
PCICLK5
AVDD48
**FS3/48MHz
GND
VDD
SDRAM10(PCI_STOP#)*
SDRAM11
SDRAM12
SCLK
•
•
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
48-Pin 300mil SSOP &
240mil TSSOP package
Skew Specifications:
•
•
•
•
•
•
•
CPUT - CPUC: <250ps
PCI - PCI: <500ps
CPU - SDRAM: <350ps
SDRAM - SDRAM: <250ps
AGP - AGP: <250ps
AGP - PCI: <750ps
Notes:
REF0 could be 1X or 2X strength controlled by I2Cꢀ
* Internal Pull-up Resistor of 120K to VDD
** Internal pull-down of 120K to GNDꢀ
CPU - PCI: <3ns
Block Diagram
Functionality
FS3
0
0
0
FS2
0
0
0
FS1
0
0
1
FS0
0
1
CPU SDRAM PCI
66.66 66.66 33.33 66.66
66.66 100.00 33.33 66.66
100.00 66.66 33.33 66.66
AGP
PLL2
48MHz
REF0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
100.00 100.00 33.33 66.66
100.00 133.33 33.33 66.66
120.00 120.00 30.00 60.00
133.33 100.00 33.33 66.66
133.33 133.33 33.33 66.66
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKT (1:0)
CPUCLKC0
2
90.00
100.90 100.90 33.63 67.27
100.00 66.66 33.33 66.66
90.00
30.00 60.00
SDRAM
DIVDER
Stop
Stop
SDRAM (12:0)
13
6
Control
Logic
SDATA
SCLK
PCI
DIVDER
100.00 100.00 33.33 66.66
100.00 133.33 33.33 66.66
126.00 126.00 31.50 63.00
133.33 100.00 33.33 66.66
133.33 133.33 33.33 66.66
PCICLK (5:0)
PCICLK_F
AGP (1:0)
FS (3:0)
Config.
Reg.
AGP
DIVDER
PD#
PCI_STOP#
MODE
Stop
2
RESET#
1
1
1
1
Power Groups
AVDD = Xtal, Core PLL
AVDD48 = 48MHz, Fixed PLL
94235 Rev
A 01/17/02
Third party brands and names are the property of their respective owners.
ICS94235
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Real time system reset signal for frequency value or watchdog timmer
timeout. This signal is active low.
1
RESET#
PD#1
OUT
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
2
IN
4
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
5
OUT
3, 11, 16, 23, 29,
34, 41, 48
8, 17, 28, 35, 40
6
GND
PWR
Ground pins
VDD
PWR
PWR
IN
Power supply pins, nominal 3.3V
AVDD
Analog power supply pin, nominal 3.3V
Frequency select pin.
3
FS02,
7
REF0
FS12, 3
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
9
AGP0
OUT
OUT
OUT
IN
AGP outputs defined as 2X PCI. These may not be stopped.
AGP outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
10
12
AGP1
PCICLK_F
FS21, 3
PCICLK
(5:4) (2:0)
PCICLK3
MODE1, 3
AVDD48
FS32, 3
20, 19, 15, 14, 13
OUT
PCI clock outputs.
OUT
IN
PCI clock output.
18
21
22
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
Analog power supply pin, nominal 3.3V
Frequency select pin.
PWR
IN
48MHz
OUT
IN
48MHz output clock
Clock input of I2C input, 5V tolerant input
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
24
27
SCLK
PCI_STOP#1
SDRAM10
IN
OUT
SDRAM clock output.
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
SDRAM
(12:11, 9:0 )
OUT
SDRAM clock outputs.
Data pin for I2C circuitry 5V tolerant
44
SDATA
I/O
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
45, 47
46
CPUCLKT (1:0)
OUT
CPUCLKC0
OUT
Notes:
1: Internal Pull-up Resistor of 120K to 3ꢀ3V on indicated inputs
2: Internal pull-down resistor of 120K to GNDꢀ
3: Bidirectional input/output pins, input logic levels are latched at internal power-on-resetꢀ Use 10Kohm resistor
to program logic Hi to VDD or GND for logic lowꢀ
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of developmentꢀ
Characteristic data and other specifications are subject to change
without noticeꢀ
2
ICS94235
General Description
The ICS94235 is a main clock synthesizer chip for AMD-K7 based systems with ALI 1647 style chipsetꢀ This provides all
clocks required for such a systemꢀ
The ICS94235 belongs to ICS new generation of programmable system clock generatorsꢀ It employs serial programming I2C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocksꢀ
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clockingꢀ
Mode Pin - Power Management Input Control
MODE, Pin 18
Pin 27
(Latched Input)
PCI_STOP#
0
(Input)
SDRAM10
(Output)
1
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of developmentꢀ
Characteristic data and other specifications are subject to change
without noticeꢀ
3
ICS94235
General I2C serial interface information for the ICS94235
How to Write:
How to Read:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8)ꢀ
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3(H)
Address D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 7
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B8
Byte18
Byte 19
Byte 20
ACK
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
*See notes on the following pageꢀ
Third party brands and names are the property of their respective owners.
4
ICS94235
Brief I2C registers description for ICS94235
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status and
programmable ’safe’frequency’can be
configured in this register.
Watchdog Control Registers 10 Bit [6:0]
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
VCO Control Selection Bit
10 Bit [7]
0
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
VCO Frequency Control
Registers
11-12
13-14
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for
verificationꢀ Readback will support standard SMBUS controller protocolꢀ The number of bytes to readback is
defined by writing to byte 8ꢀ
2ꢀ
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a setꢀ If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiverꢀ
3ꢀ
4ꢀ
5ꢀ
6ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
7ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
Third party brands and names are the property of their respective owners.
5
ICS94235
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK AGP
Spread Precentage
Bit2 Bit7 Bit6 Bit5 Bit4
(MHz)
66.66
(MHz)
66.66
(MHz) (MHz)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
33.33
33.33
33.33
33.33
33.33
30.00
33.33
33.33
30.00
33.63
33.33
33.33
33.33
31.50
33.33
33.33
34.00
34.00
34.00
34.00
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.66
35.66
33.40
36.66
36.66
66.66
66.66
66.66
66.66
66.66
60.00
66.66
66.66
60.00
67.27
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
66.66
100.00
66.66
100.00
100.00
100.00
120.00
133.33
133.33
90.00
100.00
133.33
120.00
100.00
133.33
90.00
100.90
100.00
100.00
100.00
126.00
133.33
133.33
102.00
102.00
136.00
136.00
103.00
103.00
137.33
137.33
105.00
105.00
140.00
107.00
107.00
133.90
110.00
146.66
100.90
66.66
66.66 0 to -0.5% Down Spread
66.66 0 to -0.5% Down Spread
66.66 0 to -0.5% Down Spread
100.00
133.33
126.00
100.00
133.33
102.00
136.00
102.00
136.00
103.00
137.33
103.00
137.33
105.00
140.00
140.00
107.00
142.66
133.90
110.00
146.66
63.00
+/- 0.25% Center Spread
66.66 0 to -0.5% Down Spread
66.66 0 to -0.5% Down Spread
Bit 2,
Bit 7:4
00000
Note1
67.99
67.99
67.99
67.99
68.66
68.66
68.66
68.66
69.99
69.99
69.99
71.33
71.33
66.95
73.33
73.33
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
0
0
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3ꢀ
The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shownꢀ
Third party brands and names are the property of their respective owners.
6
ICS94235
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
MODE#
BIT PIN# PWD
DESCRIPTION
-
X
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
X
1
1
1
1
FS3#
20
19
18
15
14
13
12
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
10
9
AGP1
AGP0
22
43
48MHz
SDRAM0
REF0 - 1X or 2X
default = 1=1X
CPUCLKT0, CPUCLKC0
Bit 2
7
1
Bit 1 47, 46
Bit 0 45
1
1
CPUCLKT1
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
X
X
X
1
FS0#
FS1#
FS2#
-
0
1
1
1
1
1
1
1
Reserved
Reserved
-
-
-
39
38
37
36
33
32
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
31
30
27
26
25
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
1
1
1
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDRAM1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
-
-
-
-
-
42
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
2ꢀ Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditionsꢀ
Third party brands and names are the property of their respective owners.
7
ICS94235
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to how many
290ms the watchdog timer will wait
before it goes to alarm mode and
reset the frequency to the safe
setting. Default at power up is
16X 290ms = 4.64 seconds.
Note: FS values in bit (0:4) will correspond to Byte 0 FS
valuesꢀ Default safe frequency is same as 00000 entry in
byte0ꢀ
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte 12
bit (7:0) & Byte 11 bit (7) ) + 8 is equal to the VCO divider
valueꢀ For example if VCO divider value of 36 is desired,
user need to program 36 - 8 = 28, namely, 0, 00011100 into
byte 12 bit & byte 11 bit 7ꢀ
Note: The decimal representation of these 7 bits
(Byte 11 (6:0)) + 2 is equal to the REF divider value ꢀ
Notes:
1ꢀ PWD = Power on Default
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8
ICS94235
Byte 13: Spread Spectrum Control Register
Byte 14: Spread Spectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrumꢀ
Incorrect spread percentage may cause system failureꢀ
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrumꢀ
Incorrect spread percentage may cause system failureꢀ
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
1
0
0
CPUCLKT/C0 Skew Control
PCICLK (5:0, F) Skew Control
CPUCLKT1
SDRAM0 Skew Control
SDRAM (12:1) Skew Control
AGP (1:0) Skew Control
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
CPUCLKT/C0 Slew Rate Control
SDRAM0 Skew Control
CPUCLKT1 Slew Rate Control
PCICLK_F Slew Rate Control
PCICLK (5:0) Slew Rate Control
SDRAM (12:1) Skew Control
AGP (1:0) Slew Rate Control
48MHz Slew Rate Control
Notes:
1ꢀ PWD = Power on Default
2ꢀ The power on default for byte 13-20 depends on the harware (latch inputs FS(4:0)) or I2C (Byte 0 bit (1:7)) settingꢀ Be sure
to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first passꢀ
3ꢀ If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up valueꢀ
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9
ICS94235
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not
affect device performance or functinalityꢀ
VCOProgrammingConstrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
UsefulFormula
VCOFrequency=14ꢀ31818xVCO/REFdividervalue
Phase Detector Stabiliy = 14ꢀ038 x (VCO divider value)-0ꢀ5
ToprogramtheVCOfrequencyforover-clocking*
0ꢀ Before trying to program our clock manually, consider using ICS provided software utilities for easy programmingꢀ
1ꢀ Select the frequency you want to over-clock from with the desire gear ratio (iꢀeꢀ CPU:SDRAM:3V66:PCI ratio) by writing to
byte 0, or using initial hardware power up frequencyꢀ
2ꢀWrite 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20)ꢀ
3ꢀ Read back byte 11-20 and copy values in these registersꢀ
4ꢀ Re-initialize the write sequenceꢀ
5ꢀ Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider valuesꢀ
6ꢀ Write to byte 13 to 20 with the values you copy from step 3ꢀ This maintains the output spread, skew and slew rateꢀ
7ꢀ The above procedure is only needed when changing the VCO for the 1st passꢀ If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to rebootꢀ
Note:
1ꢀ User needs to ensure step 3 & 7 is carried outꢀ Systems with wrong spread percentage and/or group to group skew relation
programmed into bytes 13-16 could be unstableꢀ Step 3 & 7 assure the correct spread and skew relationshipꢀ
2ꢀ If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctlyꢀ
3ꢀ Follow min and max VCO frequency range providedꢀ Internal PLLcould be unstable if VCO frequency is too fast or too slowꢀ
Use 14ꢀ31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz)ꢀ
4ꢀ ICS recommends users, to utilize the software utility provided by ICSApplication Engineering to program theVCO frequencyꢀ
5ꢀ Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desiredꢀ
See Application note for software supportꢀ
Third party brands and names are the property of their respective owners.
10
ICS94235
Absolute Maximum Ratings
Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 5ꢀ5V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
Electrical Characteristics - Input/Supply/Common Ouput Parameters.
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2
VDD+0.3
V
Input Low Voltage
Input High Current
VIL
IIH
VSS-0.3
0.8
5
V
VIN = VDD
uA
Input Low Current
Input Low Current
IIL1
IIL2
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
uA
uA
-200
Operating
IDD3.3OP66
IDD3.3OP100
CL = 0 pF; Select @ 66MHz
CL = 0 pF; Select @ 66MHz
Supply Current
180
mA
IDD3.3OP133
CL = 0 pF; Select @ 133MHz
VDD = 3.3 V;
Power Down
PD
Fi
600
16
uA
Input frequency
12
27
14.318
MHz
Input Capacitance1
Clk Stabilization1
Skew1
CIN
Logic Inputs
X1 & X2 pins
5
pF
pF
CINX
45
TSTAB
From VDD = 3.3 V to 1% target Freq.
VT = 50%
3
ms
tA GP-PCI
tCPU-SDRAM
tCPU-PCI
300
200
2.67
750
350
3
ps
ns
1Guaranteed by design, not 100% tested in production.
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11
ICS94235
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated).
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX
UNITS
Output Impedance
ZO
VO = VX
Ohms
Output High Voltage
VOH2B
Termination to Vpull-up(external)
1.2
0.4
V
Output Low Voltage
Output Low Current
Rise Time1
VOL2B
IOL2B
tr2B
Termination to Vpull-up(external)
VOL = 0.3V
V
18
mA
ns
ns
VOL = 0.3V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
Fall Time1
tf2B
0.913
Vpullup(external)
0.6
Vpullup(external)
0.6
Differential Voltage-AC1
Differential Voltage-DC1
VDIF
VDIF
0.4
0.2
V
V
Note 2
Note 2
Differential Crossover Voltage1
Duty Cycle1
VX
550
45
1100
55
mV
%
Note 3
dt2B
VT = 50%
53
Skew1
tsk2B
VT = 50%
250
ps
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
tjcyc-cyc2B
tjabs2B
VT = VX
201
250
250
ps
ps
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the TRUE
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max = (Vpullup(external)/2)+150mV.
Third party brands and names are the property of their respective owners.
12
ICS94235
Electrical Characteristics - PCICLK
TA = 0 - 70º C VDD = 3.3V +/-5%; C = 30pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
V
2.6
IOL = 9.4 mA
0.4
-16
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
19
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5V
1.63
1.63
51.9
170
2
2
Fall Time1
tf1
ns
Duty Cycle1
dt1
55
500
%
Skew1
Tsk1
VT = 1.5V
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
V
2.6
12
45
IOL = 9.4 mA
0.4
-12
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
tr1
VOL = 0.4 V, VOH =2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.63
1.63
49.7
170
2
2
Fall Time1
tf1
ns
Duty Cycle1
dt1
55
500
%
Skew1(window)
Tsk1
VT = 50%
ps
1Guaranteed by design, not 100% tested in production.
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13
ICS94235
Electrical Characteristics - 48MHz, REF0
TA = 0 - 70º C; VDD = 3.3V +/-5%, VDDL = 2.5 V +/-5%; CL = 20pF (otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
IOH = -16 mA
MIN
TYP
MAX
UNITS
V
2.4
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.23
1.21
53
2
2
Fall Time1
tf5
ns
Duty Cycle1
dt5
45
-1
55
0.5
1
%
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
595
ns
VT = 1.5 V
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM (12:0)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH3
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
Output High Voltage
Output Low Voltage
2
V
V
VOL3
IOL = 11 mA
0.4
-12
Output High Current
Output Low Current
Rise Time1
IOH3
IOL3
Tr3
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
12
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
0.88
0.8
2.2
2.2
55
Fall Time1
Tf3
ns
Duty Cycle1
Dt3
45
51.2
205
%
Skew1(window)
Tsk1
VT = 50%
250
ps
1Guarenteed by design, not 100% tested in production.
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14
ICS94235
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) serve as dual
signal functions to the deviceꢀ During initial power-up, they
act as input pinsꢀ The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latchꢀ At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output functionꢀ In
this mode the pins produce the specified buffered clocks to
external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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15
ICS94235
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the partꢀ PD# is
an asynchronous active low inputꢀ This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizerꢀ
Internal clocks are not running after the device is put in power downꢀ When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystalꢀ The power up latency needs to be less than 3 mSꢀ The power down
latency should be as short as possible but conforming to the sequence requirements shown belowꢀ CPU_STOP# is considered
to be a don't care during the power down operationsꢀ The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possibleꢀ Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to completeꢀ
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS94235 device)ꢀ
2ꢀ As shown, the outputs Stop Low on the next falling edge after PD# goes lowꢀ
3ꢀ PD# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized inside this partꢀ
4ꢀ The shaded sections on the VCO and the Crystal signals indicate an active clockꢀ
5ꢀ Diagrams shown with respect to 133MHzꢀ Similar operation when CPU is 100MHzꢀ
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16
ICS94235
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94235ꢀ It is used to turn off the PCICLK clocks for low power operationꢀ
PCI_STOP# is synchronized by the ICS94235 internallyꢀ The minimum that the PCICLK clocks are enabled (PCI_STOP# high
pulse) is at least 10 PCICLK clocksꢀ PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteedꢀ
PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clockꢀ
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS94235 deviceꢀ)
2ꢀ PCI_STOP# is an asynchronous input, and metastable conditions may existꢀ This signal is required to be synchronized
inside the ICS94235ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
4ꢀ CPU_STOP# is shown in a high (true) stateꢀ
Third party brands and names are the property of their respective owners.
17
ICS94235
c
SYMBOL
In Millimeters
In Inches
N
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
2.413
0.203
0.203
0.127
E1
E
INDEX
AREA
c
SEE VARIATIONS
SEE VARIATIONS
D
E
E1
e
10.033
7.391
10.668
7.595
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
A
0°
8°
0°
8°
A1
- C -
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
MAX
MIN
.620
MAX
.630
.10 (.004) C
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
300 mil SSOP
Ordering Information
ICS94235yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
18
ICS94235
c
SYMBOL
In Millimeters
In Inches
N
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
E1
E
INDEX
AREA
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
1
22
E
D
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
A
A2
0°
-
8°
0°
-
8°
α
A1
aaa
0.10
.004
- C -
e
SEATING
PLANE
VARIATIONS
b
D mm.
D (inch)
N
aaa
C
MIN
MAX
MIN
.488
MAX
48
12.40
12.60
.496
7/6/00 Rev B
6ꢀ10 mmꢀ Body, 0ꢀ50 mmꢀ pitch TSSOP
(0ꢀ020 mil)
MO-153 JEDEC
Doc.# 10-0039
(240 mil)
Ordering Information
ICS94235yGT
Example:
ICS XXXX y G - T
Designation for tape and reel packaging
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
19
相关型号：
ICS94252YF-T-LF
Processor Specific Clock Generator, 133.33MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48
IDT
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