ICS94241 [ICSI]
Programmable TCH⑩ for Differential PIII⑩ Processor; 可编程TCH ™差分PIII ™处理器
| 型号： | ICS94241 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable TCH⑩ for Differential PIII⑩ Processor |
| 文件： | 总16页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94241
Integrated
Circuit
Systems, Inc.
ProgrammableTCH™forDifferentialPIII™Processor
Recommended Application:
Pin Configuration
VIA PL133-T style chipset with Intel differential PIII
processor
Output Features:
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
GNDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VTT_PWRGD#
REF0
REF1/FS2
GNDCPU
CPUCLK_CS
CPUCLK0
VDDLCPU
RESET#
**1
X2
•
•
2 - CPUs @2.5V
13 - SDRAM @ 3.3V
VDDPCI
FS4/PCICLK0
FS3/PCICLK1
GNDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDPCI
BUFFER_IN
GNDSDR
SDRAM12
SDRAM11
VDDSDR
SDRAM10
SDRAM9
GND48
*
*
•
•
•
•
7 - PCI @3.3V,
1 - 48MHz, @3.3V
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
SDRAM0
GNDSDR
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
GNDSDR
SDRAM5
SDRAM6
VDDSDR
SDRAM7
SDRAM8
AVDD48
Features:
•
•
•
•
•
•
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable output to output skew
Programmable spread spectrum for EMI control
Real time system reset output
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
**
**
SDATA
SCLK
48MHz/FS0
24MHz/FS1
•
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Key Specifications:
** Internal Pull-down resistor of 120K to GND
1. This output has 1.5 to 2X drive strength
•
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: <500ps
PCI – PCI: <500ps
CPU-SDRAM: <500ps
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Block Diagram
Functionality
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPUCLK PCICLK
Spread Percentage
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
66.67
66.67
68.67
71.34
33.33
+/- 0.25 Center Spread
33.33 0 to -0.5% Down Spread
34.33
35.66
± 0.25 Center Spread
+/- 0.25 Center Spread
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
100.00
100.00
103.00
107.00
33.33
+/- 0.25 Center Spread
33.33 0 to -0.5% Down Spread
34.33
35.67
+/- 0.25 Center Spread
+/- 0.25 Center Spread
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
200.00
200.00
206.00
214.00
133.33
133.33
137.33
142.67
33.33
+/- 0.25 Center Spread
33.33 0 to -0.5% Down Spread
34.33
35.67
33.33
+/- 0.25 Center Spread
+/- 0.25 Center Spread
+/- 0.25 Center Spread
33.33 0 to -0.5% Down Spread
34.33
35.67
+/- 0.25 Center Spread
+/- 0.25 Center Spread
For additional margin testing frequencies refer to pg 5
frequency table.
0453C—10/26/04
ICS94241
General Description
The ICS94241 is a single chip timing control hub for desktop designs using VIA PL133-T style chipset with Intel
differential PIII processor. It provides all necessary clock signals for such a system.
The ICS94241 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub).
ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock
device. This part incorporates ICS's newest clock technology which more robust features and functionality.
Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by
configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output
skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's
Watchdog Timer technology in having a frequency reset feature to provide a safe setting under unstable system
conditions.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 5, 14, 19, 30, 36
VDD
PWR Power supply, nominal 3.3V
PWR Ground
2, 8, 16, 22, 33, 39, 45 GND
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load cap
(36pF)
3
4
X1
IN
X2
OUT
FS41,3
IN
OUT
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
6
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
PCICLK0
FS31,3
Frequency select pin. Latched Input. Internal Pull-down to GND
7
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
PCICLK1
OUT
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew
(CPU early)
13, 12, 11, 10, 9
PCICLK (6:2)
BUFFER IN
OUT
IN
15
Input to Fanout Buffers for SDRAM outputs.
17, 18, 20, 21, 28, 29,
31, 32, 34, 34, 35, 37, SDRAM (12:0)
38, 40
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset)
OUT
23
24
SDATA
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Frequency select pin. Latched Input.
24MHz output clock
SCLK
FS12,3
IN
25
26
24MHz
48MHz
FS02,3
OUT
OUT
IN
48MHz output clock
Frequency select pin. Latched Input
27
41
AVDD48
PWR Analog power for 48MHz outputs
Real time system reset signal for frequency ratio change or
OUT
RESET
watchdog timmer timeout. This signal is active low.
42
43
44
VDDLCPU
CPUCLK0
CPUCLK_CS
FS22,3
PWR Supply for CPU clocks 2.5V nominal
OUT
OUT
IN
CPU clock outputs
CPU clock output for chipset host clock
Frequency select pin. Latched Input
14.318 MHz reference clock.
46
47
REF1
OUT
REF0
OUT 14.318 Mhz reference clock.
This 3.3V LVTTL input is a level sensitive strobe used to determine
48
VTT_PWRGD#
IN
when FS inputs are valid and are ready to be sampled
(active low)
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Internal Pull-down to GND on indicated inputs
3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0453C—10/26/04
2
ICS94241
General I2C serial interface information for the ICS94241
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D2(H)
Address D3(H)
ACK
ACK
Dummy Command Code
Byte Count
ACK
ACK
Dummy Byte Count
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
Byte 7
Byte 18
Byte 19
Byte 20
ACK
ACK
ACK
If 12H has been written to B6
ACK
Byte18
Byte 19
Byte 20
If 13H has been written to B6
ACK
If 14H has been written to B6
ACK
Stop Bit
Stop Bit
*See notes on the following page.
0453C—10/26/04
3
ICS94241
Brief I2C registers description for ICS94241
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality &
Frequency Select
Register
See individual
byte
description
0
See individual
byte
description
Active / inactive output control
registers/latch inputs read back.
Output Control Registers
1-6
7
Byte 7 bit (7:4) is ICS vendor id -
001. Other bits in this register
designate device revision ID of this
See individual
byte
description
Vendor ID & Revision ID
Registers
part.
Writing to this register will configure
Byte Count
Read Back Register
byte count and how many byte will
be read back. Do not write 00H to
8
9
08H
10H
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog Timer
Count Register
Watchdog enable, watchdog status
10 Bit [6:0] and programmable 'safe' frequency'
can be configured in this register.
Watchdog Control
Registers
000,0000
This bit select whether the output
VCO Control Selection
Bit
frequency is control by
10 Bit [7]
0
hardware/byte 0 configurations or
byte 11&12 programming.
These registers control the dividers
Depended on
hardware/byte
0 configuration
VCO Frequency Control
Registers
ratio into the phase detector and
11-12
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
Spread Spectrum
Control Registers
These registers control the spread
percentage amount.
13-14
Increment or decrement the group
skew amount as compared to the
initial skew.
Group Skews Control
Registers
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the
output rise and fall time.
description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
7.
0453C—10/26/04
4
ICS94241
Byte 0: Functionality and frequency select register (Default=0)
Description
Bit
PWD
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPUCLK PCICLK
Spread Percentage
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
66.67
68.67
71.34
73.34
33.33 Center Spread +/- 0.25%
33.33 Down Spread 0 to - 0.5%
34.33 Center Spread +/- 0.25%
35.66 Center Spread +/- 0.25%
36.66 Center Spread +/- 0.25%
38.33 Center Spread +/- 0.25%
30.00 Center Spread +/- 0.25%
33.33 Center Spread +/- 0.25%
33.33 Center Spread +/- 0.25%
33.33 Down Spread 0 to - 0.5%
34.33 Center Spread +/- 0.25%
35.67 Center Spread +/- 0.25%
36.67 Center Spread +/- 0.25%
38.33 Center Spread +/- 0.25%
33.63 Center Spread +/- 0.25%
30.00 Center Spread +/- 0.25%
33.33 Center Spread +/- 0.25%
33.33 Down Spread 0 to - 0.5%
34.33 Center Spread +/- 0.25%
35.67 Center Spread +/- 0.25%
36.67 Center Spread +/- 0.25%
38.33 Center Spread +/- 0.25%
33.63 Center Spread +/- 0.25%
30.00 Center Spread +/- 0.25%
33.33 Center Spread +/- 0.25%
33.33 Down Spread 0 to - 0.5%
34.33 Center Spread +/- 0.25%
35.67 Center Spread +/- 0.25%
36.67 Center Spread +/- 0.25%
38.33 Center Spread +/- 0.25%
33.48 Center Spread +/- 0.25%
30.00 Center Spread +/- 0.25%
76.67
150.00
166.67
100.00
100.00
103.00
107.00
110.00
115.00
100.90
90.00
200.00
200.00
206.00
214.00
220.00
230.00
201.80
180.00
133.33
133.33
137.33
142.67
146.67
153.33
133.90
120.00
Bit
2, (7:4)
Note 1
Bit 3
Bit 1
Bit 0
0=Frequency selected by hardware; 1=Frequency selected by Bit2, (7:4)
0=Spread off; 1=Spread Spectrum Enable
0=Running; 1=Tristate
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0453C—10/26/04
5
ICS94241
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
1
1
1
1
1
1
1
Latched FS2#
(Reserved)
(Reserved)
(Reserved)
SDRAM0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
(Reserved)
PCICLK0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
6
-
13
12
11
10
9
-
40
-
(Reserved)
CPUCLK0
CPUCLK_CS
43
44
7
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIN#
PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
(Reserved)
-
-
1
X
1
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
(Reserved)
Latched FS0#
48MHz
1
(Reserved)
26
25
-
1
(Reserved)
1
24 MHz
X
X
X
1
Latched FS1#
Latched FS4#
Latched FS3#
(Reserved)
1
(Reserved)
17, 18,
20, 21
28, 29,
31, 32
34, 35,
37, 38
Bit 2
Bit 1
Bit 0
1
1
1
SDRAM (12:9)
SDRAM (8:5)
SDRAM (4:1)
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
REF1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
-
X
X
X
X
X
X
-
-
-
46
47
REF0
Note: This is an unused register writing to this register
will not affect device performance or functinality.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0453C—10/26/04
6
ICS94241
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
0
0
0=Hw/B0 freq / 1=B11&12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, FS4
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 16X 290ms = 4.6
seconds.
Note: FS values in bit (4:0) will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
0453C—10/26/04
7
ICS94241
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
0
0
1
1
0
SDRAM (12:1) Skew Control
PCICLK0 Skew Control
CPUCLK_CS Skew Control
CPUCLK0 Skew Control
SDRAM0 Skew Control
PCICLK (6:1) Skew Control
Byte 17:Output Rise/FallTime Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
PCICLK (6:1) Slew Rate Control
CPUCLK_CS Slew Rate Control
PCICLK0 Slew Rate Control
48MHz Slew Rate Control
24MHz Slew Rate Control
CPUCLK0 Slew Rate Control
SDRAM0 Slew Rate Control
SDRAM (12:1) Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
0453C—10/26/04
8
ICS94241
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these
are unused registers writing to these registers
will not affect device performance or
functionality.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program theVCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2.Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7.The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmedintobytes13-16couldbeunstable. Step3&7assurethecorrectspreadandskewrelationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3.Follow min and maxVCO frequency range provided. Internal PLL could be unstable ifVCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4.ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program theVCO
frequency.
5.Spread percent needs to be calculated based onVCO frequency, spread modulation frequency and spread amount
desired. See Application note for software support.
0453C—10/26/04
9
ICS94241
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIH
VIL
VSS - 0.3
V
IIH
VIN = VDD
5
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with no pull-up resistors
CL = 0 pF; Select @ 66MHz
CL = 0 pF; Select @ 100MHz
VDD = 3.3 V
-5
IIL2
-200
IDD3.3OP66
IDD3.3OP100
Fi
90
90
180
mA
Supply Current
Input frequency
Input Capacitance1
12
27
16
5
MHz
pF
CIN
CINX
TSTAB
Logic Inputs
X1 & X2 pins
45
3
pF
From VDD = 3.3 V to 1% target Freq.
Clk Stabilization1
ms
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
IDD2.5OP66
IDD2.5OP100
tCPU-PCI
CONDITIONS
MIN
TYP
10
MAX
72
UNITS
mA
Operating
Supply Current
Skew1
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
VT = 1.5 V; VTL = 1.25 V
15
100
4
1.5
ns
1Guaranteed by design, not 100% tested in production.
0453C—10/26/04
10
ICS94241
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
CONDITIONS
IOH = -12.0mA
MIN
TYP
MAX
UNITS
V
2
VOL2B
IOH2B
IOL2B
IOL = 12 mA
0.4
-19
V
VOH = 1.7 V
mA
mA
ns
VOL = 0.7 V
19
45
1
tr2B
VOL = 0.5V, VOH = 2.0 V
VOH = 2.0V, VOL = 0.5 V
VT = 1.25 V
0.95
0.95
49
1.3
1.3
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
%
1
Skew
tsk2B
VT = 1.25 V
145
225
175
250
ps
1
tjcyc-cyc2B
VT = 1.25 V
Jitter, Cycle-to-cycle
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
SYMBOL
CONDITIONS
IOH = -11 mA
MIN
TYP
MAX
UNITS
V
VOH1
VOL1
IOH1
IOL1
tr1
2.4
IOL = 9.4 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
25
45
VOL = 0.4 V,VOH = 2.4 V
VOH = 2.4 V,VOL = 0.4 V
VT = 1.5 V
1.6
1.9
52
2
tf1
2
ns
dt1
55
%
tsk1
VT = 1.5 V
50
500
250
ps
1
tjcyc-cyc2B
VT= 1.5 V
Jitter, Cycle-to-cycle
240
ps
1Guaranteed by design, not 100% tested in production.
0453C—10/26/04
11
ICS94241
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
IOH = -28mA
MIN
TYP
MAX
UNITS
V
2.4
VOL3
IOH3
IOL3
Tr31
Tf31
Dt31
Tsk1
Tprop
IOL = 23 mA
0.4
-54
V
VOH = 2.0 V
mA
mA
ns
VOH = 0.8 V
41
45
VOL = 0.4V, VOH = 2.4 V
VOH = 2.4V, VOL= 0.4 V
VT= 1.5 V
0.85
0.85
50
2
2
Fall Time
ns
Duty Cycle
55
500
5
%
Skew1
VT= 1.5 V
VT= 1.5 V
200
ps
Propagation Delay
ns
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
SYMBOL
VOH5
CONDITIONS
IOH = -16 mA
MIN
TYP
MAX
UNITS
V
2.4
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
VOL5
IOH5
IOL5
tr5
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
16
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.5
53
4
4
Fall Time1
tf5
ns
Duty Cycle1
dt5
55
500
%
1
tjcyc-cyc2B
VT = 1.5 V
Jiter, Cycle-to-cycle (24, 48MHz)
250
ps
1Guaranteed by design, not 100% tested in production.
0453C—10/26/04
12
ICS94241
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0453C—10/26/04
13
ICS94241
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
0453C—10/26/04
14
ICS94241
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS94241yFLF-T
Example:
ICS XXXX y F LF-T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0453C—10/26/04
15
ICS94241
Revision History
Rev.
Issue Date Description
Page #
C
10/26/2004 Added Lead Free Ordering Information
15
0453C—10/26/04
16
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