ICS94252YFLF-T [IDT]
146.66MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 0.300 INCH, MO-118, SSOP-48;
| 型号： | ICS94252YFLF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 146.66MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 0.300 INCH, MO-118, SSOP-48 光电二极管 |
| 文件： | 总19页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94252
Integrated
Circuit
Systems, Inc.
Programmable System Clock Chip for PIII™ Processor
Recommended Application:
ALI 1651 style chipset
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
IOAPIC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
CPUCLK0
CPUCLK1
VDDL
•
•
•
•
•
•
2 - CPU clocks @ 2.5V
13 - SDRAM @ 3.3V
7 - PCI @3.3V
2 - AGP @ 3.3V
1 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V
1 - REF @3.3V, (selectable strength) through I2C
X1
X2
SDATA
VDD
**FS0/REF0
VDD
**FS1/AGP0
AGP1
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
GND
1*FS2/PCICLK_F
PCICLK0
PCICLK1
RESET#/PCICLK2
GND
•
Features:
GND
•
•
•
•
•
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, PCI and AGP skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread
percentage
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
*MODE/PCICLK3
PCICLK4
*(PD#)PCICLK5
VDD
VDD
**FS3/48MHz
GND
SDRAM10(PCI_STOP#)*
SDRAM11(CPU_STOP#)*
SDRAM12(PD#)*
SCLK
•
•
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
48-Pin 300mil SSOP
Notes:
REF0 can be 1X or 2X strength controlled by I2C.
Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
1. This input has 2X drive strength
Skew Specifications:
*
•
•
•
•
•
•
•
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
AGP - AGP: <500ps
PCI - AGP: <350ps
CPU - SDRAM:<350ps
CPU - PCI: <2.5ns
Block Diagram
Functionality
FS3
FS2
FS1
0
FS0
0
CPU SDRAM
66.66 66.66
PLL2
48MHz
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
66.66 100.00
100.00 66.66
100.00 100.00
100.00 133.33
133.33 66.66
133.33 100.00
133.33 133.33
X1
X2
XTAL
OSC
REF0
IOAPIC
PLL1
Spread
CPU
DIVDER
Stop
CPUCLK (1:0)
2
Spectrum
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.66
66.66
SDRAM
DIVDER
66.66 100.00
100.00 66.66
100.00 100.00
100.00 133.33
133.33 66.66
133.33 100.00
133.33 133.33
SDRAM (12:0)
Control
Logic
SDATA
SCLK
13
6
PCI
DIVDER
Stop
FS (3:0)
PCICLK (5:0)
PCICLK_F
AGP (1:0)
Config.
Reg.
PD#
PCI_STOP#
CPU_STOP#
MODE
AGP
DIVDER
2
RESET#
Note:
PCICLK = 33.33MHz
AGP = 66.66MHz
0456A—12/12/02
ICS94252
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
OUT
IN
DESCRIPTION
Power supply pins, nominal 2.5V
1,45
VDDL
IOAPIC
X1
2
4
2.5V clock outputs
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
5
X2
OUT
3, 11, 16, 23,
29, 34, 41, 48
6, 8, 17, 21, 28,
35, 40
GND
PWR
PWR
Ground pins
VDD
Power supply pins, nominal 3.3V
FS02, 3
REF0
FS12, 3
IN
OUT
IN
Frequency select pin.
7
14.318 MHz reference clock.
Frequency select pin.
9
AGP outputs defined as 2X PCI frequency. These may not be
stopped.
AGP outputs defined as 2X PCI frequency. These may not be
stopped.
AGP0
OUT
OUT
10
12
AGP1
PCICLK_F
FS21, 3
OUT
IN
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
PCICLK2
OUT
PCI clock output
Real time system reset signal for frequency value or watchdog
timmer timeout. This signal is active low. Output is selectable via I2C
15
RESET#
OUT
Byte 5 bit7
PCICLK
(4, 1, 0)
PCICLK3
MODE1, 3
19, 14, 13
18
OUT
PCI clock outputs.
PCI clock output.
OUT
IN
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms. This pin will be activiated when
PCI clock output.
PD#1
IN
20
PCICLK5
OUT
IN
FS32, 3
48MHz
SCLK
Frequency select pin.
48MHz output clock
Clock input of I2C input, 5V tolerant input
22
24
OUT
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms. This pin will be activiated when
SDRAM clock output.
PD#1
IN
25
26
SDRAM12
OUT
IN
This asynchronous input halts CPU, SDRAM, and AGP clocks at
logic "0" level when driven low, the stop selection can be
programmed through I2C.
CPU_STOP#1
SDRAM11
OUT
IN
SDRAM clock output.
Stops all PCICLKsbesides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM clock output.
PCI_STOP#1
SDRAM10
27
OUT
30, 31, 32, 33,
36, 37, 38, 39, SDRAM ( 9:0 )
42, 43
OUT
SDRAM clock outputs.
Data input for I2C serial input, 5V tolerant input
2.5V CPU clocks
44
SDATA
IN
46, 47
CPUCLK (1:0)
OUT
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
3: Internal Pull-down resistor of 120K to GND on indicated inputs.
0456A—12/12/02
2
ICS94252
General Description
The ICS94252 is a main clock synthesizer chip for PIII based systems with ALI 1651 style chipset. This provides all
clocks required for such a system.
The ICS94252 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 18
(Latched Input)
Pin 20
Pin 25
Pin 26
Pin 27
PCICLK5
(Output)
PD#
(Input)
CPU_STOP#
(Input)
PCI_STOP#
(Input)
0
PD#
(Input)
SDRAM12
(Output)
SDRAM11
(Output)
SDRAM10
(Output)
1
0456A—12/12/02
3
ICS94252
General I2C serial interface information for the ICS94252
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3(H)
Address D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 7
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B8
ACK
Byte18
Byte 19
Byte 20
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
*See notes on the following page.
0456A—12/12/02
4
ICS94252
Brief I2C registers description for ICS94252
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality &
Frequency Select
Register
See individual
byte
description
0
See individual
byte
description
Active / inactive output control
registers/latch inputs read back.
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Vendor ID & Revision ID
Registers
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00H to
this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status
10 Bit [6:0] and programmable 'safe' frequency'
can be configured in this register.
Watchdog Control
Registers
000,0000
This bit select whether the output
VCO Control Selection
Bit
frequency is control by
hardware/byte 0 configurations or
10 Bit [7]
0
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
These registers control the spread
percentage amount.
13-14
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
See individual
byte
Group Skews Control
Registers
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the
output rise and fall time.
description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
7.
0456A—12/12/02
5
ICS94252
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK AGP
Spread Precentage
Bit2 Bit7 Bit6 Bit5 Bit4
(MHz)
66.66
(MHz)
66.66
(MHz) (MHz)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
66.66
100.00
66.66
100.00
133.33
66.66
100.00
133.33
66.66
100.00
66.66
100.00
133.33
66.66
100.00
133.33
69.99
105.00
69.99
105.00
140.00
69.99
105.00
140.00
73.33
110.00
73.33
110.00
146.66
73.33
110.00
146.66
100.00
100.00
100.00
133.33
133.33
133.33
66.66
66.66
100.00
100.00
100.00
133.33
133.33
133.33
69.99
Bit 2,
Bit 7:4
00000
Note1
69.99
105.00
105.00
105.00
140.00
140.00
140.00
73.33
73.33
110.00
110.00
110.00
146.66
146.66
146.66
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
0
0
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
0456A—12/12/02
6
ICS94252
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
MODE#
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIN# PWD
DESCRIPTION
-
X
1
1
1
1
1
1
1
-
10
9
X
1
1
1
1
FS3#
20
19
18
15
14
13
12
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
AGP1
AGP0
48MHz
IOAPIC
22
2
REF0 - 1X or 2X
default = 1=1X
Bit 2
7
1
Bit 1
Bit 0
46
47
1
1
CPUCLK1
CPUCLK0
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM0
X
X
X
1
FS0#
FS1#
FS2#
43
42
39
38
37
36
33
32
1
1
1
1
1
1
1
1
-
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
-
31
30
27
26
25
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
1
1
1
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
1 = PCICLK2, 0 = RESET#
(Reserved)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
15
-
1
1
1
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
-
(Reserved)
-
(Reserved)
-
(Reserved)
-
(Reserved)
Bit (1:0) = 00 CPU_STOP will
stop CPU clocks
Bit 1
-
-
0
0
Bit (1:0) = 01 CPU_STOP will
stop CPU, SDRAM, AGP clocks
Bit (1:0) = 10 CPU_STOP will
stop CPU, SDRAM clocks
Bit (1:0) = 11 CPU_STOP will
stop CPU, AGP clocks
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Bit 0
0456A—12/12/02
7
ICS94252
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to how many
290ms the watchdog timer will wait
before it goes to alarm mode and
reset the frequency to the safe
setting. Default at power up is
16X 290ms = 4.64 seconds.
Note: FS values in bit (0:4) will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
Note: The decimal representation of these 9 bits (Byte
12 bit (7:0) & Byte 11 bit (7) ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits
(Byte 11 (6:0)) + 2 is equal to the REF divider
value .
Notes:
1. PWD = Power on Default
0456A—12/12/02
8
ICS94252
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
1
0
0
CPUCLK0 Skew Control
PCICLK (5:0, F) Skew Control
CPUCLK1 Skew Control
SDRAM0 Skew Control
SDRAM (12:1) Skew Control
AGP (1:0) Skew Control
Byte 17:Output Rise/FallTime Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
CPUCLK0 Slew Rate Control
SDRAM0 Skew Control
CPUCLK1 Slew Rate Control
PCICLK_F Slew Rate Control
PCICLK (5:0) Slew Rate Control
SDRAM (12:1) Skew Control
AGP (1:0) Slew Rate Control
48MHz Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS(4:0)) or I2C (Byte 0 bit (1:7)) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
0456A—12/12/02
9
ICS94252
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these
are unused registers writing to these registers
will not affect device performance or
functinality.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program theVCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2.Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7.The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmedintobytes13-16couldbeunstable. Step3&7assurethecorrectspreadandskewrelationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3.Follow min and maxVCO frequency range provided. Internal PLL could be unstable ifVCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4.ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program theVCO
frequency.
5.Spread percent needs to be calculated based onVCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
0456A—12/12/02
10
ICS94252
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-10%, VDDL = 2.5 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
2
VSS - 0.3
-5
V
V
VIL
IIH
VIN = VDD
5
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
mA
mA
IIL2
-200
CL = 30, CPU=66 MHz, SDRAM=66 MHz
235
313
510
250
325
550
CL = 30, CPU=66,100,133 MHz,SDRAM=66,
100 MHz
Operating Supply
Current
IDD3.3OP
CL = 30, CPU=100 MHz, SDRAM= 133 MHz
CPU=133 MHz, SDRAM=133 MHz
CL =30, CPU=66-133 MHz, SDRAM=100 MHz
CL = 30 pF; Input address to VDD or GND
VDD = 3.3 V
513
23
525
70
IDD2.5OP
IDD3.3PD
Fi
Powerdown Current
Input Frequency
mA
MHz
pF
230
600
14.32
CIN
Logic Inputs
5
6
Input Capacitance1
Clk Stabilization1
COUT
CINX
Output pin capacitance
pF
X1 & X2 pins
27
45
3
pF
TSTAB
From VDD = 3.3 V to 1% target frequency
ms
1Guaranteed by design, not 100% tested in production.
0456A—12/12/02
11
ICS94252
Electrical Characteristics - CPU
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
tr2B
CONDITIONS
IOH = -12.0 mA
MIN
2
TYP
2.3
MAX UNITS
V
IOL = 12 mA
0.4
-27
V
VOH = 1.7 V
-48
mA
mA
ns
VOL = 0.7 V
27
0.4
0.4
45
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.8
0.8
1.6
1.6
55
Fall Time1
Duty Cycle1
tf2B
ns
dt2B
48.2
109
246
%
Skew1
tsk2B
VT = 1.25 V
175
250
ps
VT = 1.25 V, CPU 66, SDRAM 100
CPU 100, SDRAM 100
CPU 133, SDRAM 100
CPU 133, SDRAM 133
220
240
210
250
250
250
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP, PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.3
TYP
MAX UNITS
Output High Voltage
Output Low Voltage
IOH = -1mA
IOL = 1 mA
>2
0.55
-33
V
V
VOL1
0.19
V
V
V
OH@MIN = 1 V
IOH1
IOL1
Output High Current
mA
mA
OH@MAX = 3.135V
OL@MIN = 1.95 V
-33
30
68
24
Output Low Current
Rise Time1
VOL@MAX =0.4V
38
2
tr1
tf1
0.5
0.5
45
ns
ns
%
VOL = 0.4 V, VOH = 2.4 V
1.75
Fall Time1
VOL = 2.4 V, VOH = 0.4 V
VT = 1.5 V
1.79
51
2
Duty Cycle1
dt1
tsk1
tjcyc-cyc1
55
Skew1
VT = 1.5 V
VT = 1.5 V
212
160
500
500
ps
ps
Jitter, cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
0456A—12/12/02
12
ICS94252
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH3
VOL3
IOH3
IOL3
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
MAX UNITS
V
IOL = 23 mA
0.4
-46
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8V
54
0.4
0.4
45
tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.73
0.81
50.2
1.6
1.6
55
Fall Time1
Duty Cycle1
tf3
ns
dt3
%
tsk1
tsk1
tsk1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
Sdram 0:12
Sdram 0:9
233
137
250
250
250
ps
ps
ps
Skew
Sdram 10:12
91
VT = 1.5 V, CPU 66, SDRAM 100
CPU 100, SDRAM 100
245
Jitter, cycle-to-cycle1
tjcyc-cyc3
239
223
230
250ps
CPU 133, SDRAM 100
CPU 133, SDRAM 133
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH4B
VOL4B
IOH4B
IOL4B
tr4B
CONDITIONS
MIN
TYP
MAX UNITS
V
IOH = -12 mA
IOL =12mA
2
2.25
0.4
-21
V
mA
mA
ns
VOH = 1.7 V
-48
VOL= 0.7
V
19
0.4
0.4
45
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.91
0.88
54.2
318
1.6
1.6
55
Fall Time1
tf4B
ns
Duty Cycle1
dt4B
%
Jitter, Cycle-to-cycle1
tjcyc-cyc4B VT = 1.25 V
500
ps
1Guaranteed by design, not 100% tested in production.
0456A—12/12/02
13
ICS94252
Electrical Characteristics - 48MHz, REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.4
TYP
2.75
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.4 V
0.4
-23
V
mA
mA
ns
ns
%
-40.5
IOL5
29
45
45
tr5
VOL = 0.4 V, VOH = 2.4 V, 48MHz
VOH = 2.4 V, VOL = 0.4 V , 48MHz
VT = 1.5 V, 48MHz
1.81
1.79
54
2
2
Fall Time1
Duty Cycle1
Rise Time1
Fall Time1
Duty Cycle1
tf5
dt5
55
2
tr5
VOL = 0.4 V, VOH = 2.4 V, REF
1.1
ns
ns
%
tf5
VOH = 2.4 V, VOL = 0.4 V, REF
VT = 1.5 V, REF
1.3
2
dt5
54.5
183
479
55
500
500
Jitter, cycle-to-cycle1
Jitter, cycle-to-cycle1
tjcyc-cyc5
tjcyc-cyc5
VT = 1.5 V, 48MHz
VT = 1.5 V, REF
ps
ps
1Guaranteed by design, not 100% tested in production.
0456A—12/12/02
14
ICS94252
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0456A—12/12/02
15
ICS94252
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94252. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94252 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PCICLK
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94252 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94252.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
0456A—12/12/02
16
ICS94252
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations.The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94252 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0456A—12/12/02
17
ICS94252
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94252. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLK
PCI_STOP# (High)
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94252.
3. All other clocks continue to run undisturbed.
0456A—12/12/02
18
ICS94252
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
hh x 45°
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
A1
D (inch)
N
- CC --
MIN
MAX
MIN
.620
MAX
.630
48
15.75
16.00
e
SEATING
PLANE
b
Reference Doc.: JEDEC Publication 95, MO-118
.10 (.004)
C
10-0034
Ordering Information
ICS94252yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0456A—12/12/02
19
相关型号：
ICS94258YG-XX-T-LF
Processor Specific Clock Generator, 133.33MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, TSSOP-48
IDT
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