ICS94236F-T [IDT]
Clock Generator, PDSO48;
| 型号： | ICS94236F-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO48 光电二极管 |
| 文件： | 总17页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94236
Integrated
Circuit
Systems, Inc.
Programmable System Clock Chip forAMD - K7™ processor
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
REF0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1/FS2**
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDCPU
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
•
•
•
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
13 - SDRAM @ 3.3V
GND
X1
X2
VDDPCI
•
•
•
•
6 - PCI @3.3V,
1FS4/PCICLK_F
**FS3/PCICLK0
GND
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
Features:
•
•
•
•
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCI_F and PCICLK skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
SDATA
SCLK
48MHz/FS0*
24/48MHz/FS1**
•
•
•
48-Pin 300mil SSOP
Internal Pull-up Resistor of 120K to VDD.
Internal Pull-down Resistor of 120K to GND.
Internal Pull-down Resistor of 60K to GND.
*
**
1
Block Diagram
Functionality
CPU
(MHz)
95.00
PCICLK
(MHz)
31.67
33.33
34.00
35.00
36.67
37.67
38.33
40.00
33.33
33.75
34.25
34.75
35.25
35.75
36.25
37.50
FS3
FS2
FS1
FS0
PLL2
48MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24_48MHz
/ 2
100.00
102.00
105.00
110.00
113.00
115.00
120.00
133.33
135.00
137.00
139.00
141.00
143.00
145.00
150.00
X1
X2
XTAL
OSC
REF (1:0)
CPUCLK
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKC0
CPUCLKT0
SEL24_48#
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
Control
Logic
SDATA
SCLK
FS (4:0)
PD#
Config.
Reg.
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
BUFFER IN
* 16 additional frequency selectables via FS4, refer to page5
for frequency table.
0451A—01/10/03
ICS94236
General Description
The ICS94236 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The ICS94236 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
2
REF0
GND
X1
OUT
3,9,16,22,
33,39,45, 47
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
4
IN
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
5
X2
OUT
6,14
VDDPCI
PCICLK_F
PWR Supply for PCICLK_F and PCICLK, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
OUT
7
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
FS4 2
IN
FS3 2
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
8
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK(2:4)
BUFFER IN
OUT PCI clock output
IN
Logic input to select 24 or 48MHz for pin 25 output
10
OUT PCI clock output.
OUT PCI clock outputs.
11, 12, 13
15
IN
Input to Fanout Buffers for SDRAM outputs.
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
SDRAM (11:0)
OUT
19,30,36
23
VDDSDR
SDATA
PWR Supply for SDRAM nominal 3.3V.
IN
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24
SCLK
24_48MHz
FS1 2
OUT 24MHz/48MHz clock output
IN Frequency select pin. Latched Input.
OUT 48MHz output clock
25
26
48MHz
FS0 2
IN
Frequency select pin. Latched Input
27
40
41
42
VDD48
SDRAM_OUT
PD#1, 2
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
OUT Reference clock for SDRAM zero delay buffer
IN
Powers down chip, active low
VDDCPU
PWR Supply for CPU clock 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
43
CPUCLKT0
CPUCLKC0
OUT
44
46
OUT
CPUCLK
REF1
FS22
OUT 3.3V CPU clock output powered by VDDCPU
OUT 14.318 MHz reference clock.
48
IN
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0451A—01/10/03
2
ICS94236
General I2C serial interface information for the ICS94236
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3(H)
Address D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 7
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B8
Byte18
Byte 19
Byte 20
ACK
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
*See notes on the following page.
0451A—01/10/03
3
ICS94236
Brief I2C registers description for ICS94236
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status and
Watchdog Control Registers 10 Bit [6:0] programmable 'safe' frequency' can be
configured in this register.
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
VCO Control Selection Bit 10 Bit [7]
0
configurations or byte 11&12
programming.
These registers control the dividers ratio
VCO Frequency Control
Registers
Depended on
hardware/byte 0
configuration
11-12
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
13-14
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
7.
0451A—01/10/03
4
ICS94236
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
PWD
Description
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK PCICLK
Spread %
FS4 FS3 FS2 FS1 FS0
MHz
MHz
31.67
33.33
34.00
35.00
36.67
37.67
38.33
40.00
33.33
33.75
34.25
34.75
35.25
35.75
36.25
37.50
33.63
33.33
34.33
35.67
39.00
30.00
30.75
31.25
33.33
33.48
36.75
37.75
38.25
38.75
40.00
50.00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
95.00
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0 to - 0.7% spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0 to - 0.7% spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
0.45% Center Spread
100.00
102.00
105.00
110.00
113.00
115.00
120.00
133.33
135.00
137.00
139.00
141.00
143.00
145.00
150.00
100.90
100.00
103.00
107.00
117.00
120.00
123.00
125.00
133.33
133.90
147.00
151.00
153.00
155.00
160.00
200.00
Bit
(2,7:4)
Note 1
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable
0- Running
1- Tristate all outputs
Bit 3
Bit 1
Bit 0
0
1
0
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0451A—01/10/03
5
ICS94236
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
-
46
-
X
1
FS2#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
1
FS0#
CPUCLK
7
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
1
(Reserved)
FS3#
-
-
X
1
13
12
11
10
8
40
-
SDRAM_OUT
(SEL24_48#)#
X
CPUCLK0 enable (both
differential pair. "True" and
Complimentary")
Bit 1
43,44
-
1
1
Bit 0
(Reserved)*
Note:
* It is recommended to drive this bit to 0.
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
SDRAM 7
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
29
31
32
34
35
37
38
1
1
1
1
1
1
1
1
-
1
1
1
1
1
1
1
1
SDRAM 6
SDRAM 5
SDRAM 4
SDRAM 3
SDRAM 2
SDRAM 1
SDRAM 0
-
(Reserved)
48MHz
26
25
17
18
20
21
24_48MHz
SDRAM 11
SDRAM 10
SDRAM 9
SDRAM 8
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
(Reserved)
(Reserved)
Mode
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
-
1
-
X
X
1
-
FS1#
-
(Reserved)
REF1
48
2
1
1
REF0
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0451A—01/10/03
6
ICS94236
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 290ms.
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
0451A—01/10/03
7
ICS94236
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
PCI_F Skew Control
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCICLK [0:4] Skew Control
Byte 17:Output Rise/FallTime Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
X
0
1
0
CPUCLKT0
CPUCLKC0
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
1
0
1
0
PCI [0:4]: Slew Rate Control
PCI_F Slew Rate Control
48MHz: Slew Rate Control
24MHz: Slew Rate Control
CPUCLK
SDRAM_OUT: Slew Rate Control
SDRAM [0:11] Slew Rate Control
1
0
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
0451A—01/10/03
8
ICS94236
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these
are unused registers writing to these registers
will not affect device performance or
functinality.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program theVCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2.Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7.The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmedintobytes13-16couldbeunstable. Step3&7assurethecorrectspreadandskewrelationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3.Follow min and maxVCO frequency range provided. Internal PLL could be unstable ifVCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4.ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program theVCO
frequency.
5.Spread percent needs to be calculated based onVCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
0451A—01/10/03
9
ICS94236
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
2
VSS - 0.3
TYP
MAX
DD + 0.3
0.8
UNITS
VIH
VIL
IIH
V
V
V
A
VIN = VDD
VIN=0 V; Inputs with no pull-up
resistors
5
IIL1
IIL2
Input Low Current
Input Low Current
-5
uA
uA
VIN=0 V; Inputs with pull-up resistors
-200
IDD3.3OP66
IDD3.3OP100
IDD3.3OP133
PD
CL=0 pF; Select@ 66MHz
CL=0 pF; Select@ 100MHz
CL=0 pF; Select@ 133MHz
Operating
87
91
Supply Current
180
mA
104
3.25
14.318
Power Down
Input frequency
Input Capacitance1
5
16
5
mA
MHz
pF
VDD = 3.3 V;
Fi
CIN
12
27
1
Logic Inputs
X1 & X2 pins
From VDD= 3.3 V to 1% target Freq.
CINX
45
3
pF
Clk Stabilization1
Skew1
TSTAB
ms
ns
tCPU-PCI
VT = 50% to 1.5V
2.8
4
1 Guaranteed by design, not 100% tested in production.
0451A—01/10/03
10
ICS94236
Electrical Characteristics - REF(0:1)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
IOH = -12 mA
MIN
2.4
TYP
MAX
UNITS
V
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5V
1.2
1.5
4
4
Fall Time1
tf5
ns
Duty Cycle1
dt5
54.1
1007
55
%
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5V
1100
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time1
SYMBOL
Z0
CONDITIONS
VO = VX
MIN
1
TYP
MAX
UNITS
VOH2B
VOL2B
IOL2B
tr2B
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
1.2
0.4
V
V
18
mA
ns
ns
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
Fall Time1
tf2B
Vpu
+0.6
Vpu
+0.6
Differential voltage-AC1
VDIF
VDIF
Note 2
Note 2
0.4
0.2
V
V
Differential voltage-DC1
VX
dt2B
Differential Crossover
Duty Cycle1
Note 3
550
45
1100
55
mV
%
VT = 50%
VT = 50%
VT = VX
51
Skew1
tsk2B
163
201
200
250
250
ps
ps
ps
Jitter, Cycle-to-cycle1
Jitter, Absolute1
tjcyc-cyc2B
tjabs2B
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltage (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level
3 - Vpullup(external)=1.5V, Min=Vpullup(External)/2-150mV, Max=Vpullup(external)/2+150mV
0451A—01/10/03
11
ICS94236
Electrical Characteristics - CPUCLK (Push-Pull)
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP2B
RDSN2B
VOH2B
VOL2B
IOH2B
CONDITIONS
VO = VDD*0.5
MIN
10
10
2
TYP
MAX
20
UNITS
Ω
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
VO = VDD*0.5
20
Ω
V
IOH = -12mA
IOL = 12mA
VOH = 1.7 V
0.4
-19
V
mA
mA
ns
IOL2B
VOL = 0.7 V
19
0.4
0.4
45
Rise Time1
Fall Time1
Duty Cycle1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25V
1.2
1.1
1.6
1.6
55
ns
tf2B
dt2B
46.9
142
177
%
tsk2B
VT = 1.25V
Skew Window
Jitter, Cycle-to-cycle1
375
250
ps
tjcyc-cyc2B
VT = 1.25V
ps
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F, PCICLK(0:4)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
IOH = -11 mA
MIN
2.6
TYP
MAX
UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOL = 9.4 mA
0.4
-16
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
19
45
Rise Time1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5V
1.8
2
2.3
2.3
55
Fall Time1
tf5
ns
Duty Cycle1
dt5
51.7
108
223
%
1
Skew1 (window)
Jitter, Cycle-to-cycle1
VT = 1.5V
500
500
ps
Tsk
tjcyc-cyc2B
VT = 1.5V
ps
1Guaranteed by design, not 100% tested in production.
0451A—01/10/03
12
ICS94236
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP3B
VOH3
VOL3
IOH3
CONDITIONS
VO = VDD*0.5
MIN
10
TYP
MAX
24
UNITS
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18mA
IOL = 9.4mA
VOH = 2.0 V
2.4
V
0.4
-46
V
mA
mA
ns
IOL3
VOL = 0.8 V
19
45
Rise Time1
tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5V
0.8
0.8
1.6
1.6
55
Fall Time1
tf3
ns
Duty Cycle1
dt3
48.5
192
290
173
%
Skew Window(0:11)
Skew Window(0:12)
Jitter, Cycle-to-cycle1
tsk3
VT = 1.5V
250
500
250
pS
pS
pS
tsk3
VT = 1.5V
tjcyc-cyc3
VT = 1.5V
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz,48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
IOH = -16 mA
MIN
2.4
TYP
MAX
UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOL = 9 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5V
1.1
1.28
52
4
4
tf5
ns
dt5
55
0.5
500
%
Jitter, One Sigma1
Jitter, Cycle to cycle
VT = 1.5V
tj1s5
tjcyc_cyc2B
ns
VT = 1.5V
177
ps
1Guaranteed by design, not 100% tested in production.
0451A—01/10/03
13
ICS94236
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS94236
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0451A—01/10/03
14
ICS94236
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
CPU_STOP# is considered to be a don't care during the power down operations. The REF and 48MHz clocks are
expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94236 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0451A—01/10/03
15
ICS94236
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94236. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94236.
3. All other clocks continue to run undisturbed.
0451A—01/10/03
16
ICS94236
c
N
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
2.413
0.203
0.203
0.127
E1
E
INDEX
AREA
c
SEE VARIATIONS
SEEVARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
1
22
E1
e
α
hh xx 45°
D
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEEVARIATIONS
N
A
0°
8°
0°
8°
α
A1
- C -
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
MAX
MIN
MAX
.630
.10 (.004) C
16.002
48
15.748
.620
JEDECMO-118
6/1/00
DOC# 10-0034
REVB
Ordering Information
ICS94236yF-T
Example:
ICS XXXX y F -T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0451A—01/10/03
17
相关型号：
ICS94252YF-T-LF
Processor Specific Clock Generator, 133.33MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48
IDT
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