ICS843002AKI-41 [ICSI]
700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR; 700MHz的， FEMTOCLOCKS -TM VCXO BASED SONET / SDH抖动衰减器
| 型号： | ICS843002AKI-41 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 文件： | 总21页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
GENERAL DESCRIPTION
FEATURES
The ICS843002I-41 is a member of the • (2) Differential LVPECL outputs
ICS
HiperClockS™ family of high performance clock
solutions from ICS.The ICS843002I-41 is a PLL
based synchronous clock generator that is
optimized for SONET/SDH line card applications
• Selectable CLKx, nCLKx differential input pairs
HiPerClockS™
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series.The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the 2nd
PLL stage (typically 19.44MHz). The second PLL stage
provides additional frequency multiplication (x32), and it
maintains low output jitter by using a low phase noise
FemtoClock™ VCO. PLL multiplication ratios are selected
from internal lookup tables using device input selection pins.
The device performance and the PLL multiplication ratios are
optimized to support non-FEC (non-Forward Error Correction)
SONET/SDH applications with rates up to OC-48 (SONET)
• Maximum output frequency: 700MHz
• FemtoClock VCO frequency range: 560MHz - 700MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
or STM-16 (SDH).The VCXO requires the use of an external, PIN ASSIGNMENT
inexpensive pullable crystal.VCXO PLL uses external passive
loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given
line card application.
The ICS843002I-41 includes two clock input ports. Each one
can accept either a single-ended or differential input. Each
input port also includes an activity detector circuit, which
reports input clock activity through the LOR0 and LOR1 logic
output pins.The two input ports feed an input selection mux.
“Hitless switching” is accomplished through proper filter
tuning. Jitter transfer and wander characteristics are
influenced by loop filter tuning, and phase transient
performance is influenced by both loop filter tuning and
alignment error between the two reference clocks.
32 31 30 29 28 27 26 25
LF1
LF0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LOR0
LOR1
nc
ISET
VCC
VCCO_LVCMOS
VCCO_LVPECL
nQB
CLK0
nCLK0
CLK_SEL
QB
QA_SEL2
VEE
9
10 11 12 13 14 15 16
Typical ICS843002I-41 configuration in SONET/SDH Systems:
• VCXO 19.44MHz crystal
• Loop bandwidth: 50Hz - 250Hz
• Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, 622.08MHz
ICS843002I-41
32-LeadVFQFN
• Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz, Hi-Z
5mm x 5mm x 0.75mm package body
K Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843002AKI-41
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REV. A JUNE 1, 2005
1
PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
BLOCK DIAGRAM
19.44 MHz
External
Pullable
xtal
Loop
Components
ISET
ICS843002-41
LF0
LF1
Phase
Detector
VCCO_LVCMOS
Charge
Pump
and Loop
Filter
R Divider =
1, 2, 4, 8,
16 or 32
Divide
by 32
19.44 MHz
VCXO
CLK1
nCLK1
Activity
Detector
1
0
LOR1
Divide
by 32
CLK0
nCLK0
Activity
Detector
VCXO Jitter Attenuation PLL
LOR0
VCCO_PECL
622.08 MHz
QA
nQA
Cx Divider =
1,2,4,8,16,32,
HiZ or Disable
110
110
CLK_SEL
FemtoClock
PLL
111
111
x32
3
3
QA_SEL2:0
QB
nQB
Cx Divider =
1,2,4,8,16,32,
HiZ or Disable
3
R_SEL2:0
QB_SEL2:0
NOTE 1: 19.44MHzVCXO crystal shown is typical for SONET/SDH device applications.
843002AKI-41
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REV. A JUNE 1, 2005
2
PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Analog
Input/Output
Description
1, 2
LF1, LF0
Loop filter connection node pins.
Charge pump current setting pin.
3
ISET
4
5
VCC
Power
Input
Core power supply pin.
CLK0
Pulldown Non-inverting differential clock input.
Pullup/ Inverting differential clock input.
Pulldown VCC/2 bias voltage when left floating.
6
nCLK0
Input
7
8
CLK_SEL
QA_SEL2
Input
Input
Pulldown Input clock select. LVCMOS/LVTTL interface levels. See Table 3A.
Pulldown LVPECL output divider control for QA/nQA outputs. See Table 3C.
9,
10
QA_SEL1,
QA_SEL0
Input
Input
Input
Pullup
LVPECL output divider control for QA/nQA outputs. See Table 3C.
11
QB_SEL2
Pulldown LVPECL output divider control for QB/nQB outputs. See Table 3C.
12,
13
QB_SEL1,
QB_SEL0
Pullup
LVPECL output divider control for QB/nQB outputs. See Table 3C.
14
15, 16
17, 27
18, 19
20
VCCA
QA, nQA
VEE
Power
Output
Power
Output
Power
Power
Unused
Analog supply pin.
Differential clock output pair. LVPECL interface levels.
Negative supply pins.
QB, nQB
VCCO_LVPECL
VCCO_LVCMOS
nc
Differential clock output pair. LVPECL interface levels.
Output power supply pin for QA, nQA and QB, nQB.
Power supply pin for LOR0 and LOR1.
No connect.
21
22
Alarm output, loss of reference for CLK1.
LVCMOS/LVTTL interface levels.
Alarm output, loss of reference for CLK0.
LVCMOS/LVTTL interface levels.
23
24
LOR1
LOR0
Output
Output
Pullup/ Inverting differential clock input.
Pulldown VCC/2 bias voltage when left floating.
25
26
nCLK1
CLK1
Input
Input
Pulldown Non-inverting differential clock input.
28,
29,
30
R_SEL0,
R_SEL1,
R_SEL2
Input
Pulldown Input divider selection. LVCMOS/LVTTL interface. See Table 3B.
31,
32
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
50
50
RPULLDOWN Input Pulldown Resistor
843002AKI-41
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REV. A JUNE 1, 2005
3
PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 3A. INPUT REFERENCE SELECTION FUNCTION TABLE
Inputs
CLK_SEL
Input Selected
CLK0
0
1
CLK1
TABLE 3B. INPUT REFERENCE DIVIDER SELECTION FUNCTION TABLE
Inputs
R_SEL2:0
000
R Divider Value or State
÷1
001
÷2
010
÷4
011
÷8
100
÷16
÷32
101
110
bypass VCXO PLL
111
bypass VCXO and FemtoClock™ PLL's
TABLE 3C. OUTPUT DIVIDER SELECTION FUNCTION TABLE
Inputs
Qx_SEL2:0
000
Output Divider Value or State
Output Q and nQ Hi-Z
001
÷32
÷8
010
011
÷4
100
÷16
÷2
101
110
÷1
111
Output Q at LVPECL VOL, Output nQ at LVPECL VOH
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REV. A JUNE 1, 2005
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PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
-0.5V to VCCO + 0.5V
I
Outputs, VO (LVCMOS)
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
34.8°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVCMOS, VCCO_LVPECL = 3.3V 5ꢀ OR 2.5V 5ꢀ,
TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
3.135
3.135
2.375
3.3
3.3
3.3
2.5
175
10
3.465
3.465
3.465
2.625
V
V
VCCA
V
VCCO_LVCMOS,
VCCO_LVPECL
IEE
Output Supply Voltage
V
Power Supply Current
Analog Supply Current
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVCMOS = 3.3V 5ꢀ OR 2.5V 5ꢀ,
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VCC + 0.3
0.8
V
V
-0.3
CLK_SEL, QA_SEL2,
QB_SEL2, R_SEL0:R_SEL2
V
CC = VIN = 3.465V
150
5
µA
Input
High Current
IIH
QA_SEL0:1, QB_SEL0:1
VCC = VIN = 3.465V
µA
µA
V
CC = 3.465V,
IN = 0V
VCC = 3.465V,
IN = 0V
CCO_LVCMOS = 3.3V
VCCO_LVCMOS = 2.5V
CLK_SEL, QA_SEL2,
QB_SEL2, R_SEL0:R_SEL2
-5
V
Input
Low Current
IIL
QA_SEL0:1, QB_SEL0:1
LOR0, LOR1; NOTE 1
LOR0, LOR1; NOTE 1
-150
µA
V
V
2.6
1.8
V
V
Output
High Voltage
VOH
VOL
V
CCO_LVCMOS = 3.3V or
2.5V
Output
Low Voltage
0.5
V
NOTE 1: Outputs terminated with 50Ω toVCCO_LVCMOS/2 .See Parameter Measurement Information Section,
“Output LoadTest Circuit”.
843002AKI-41
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REV. A JUNE 1, 2005
5
PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVPECL = 3.3V 5ꢀ OR 2.5V 5ꢀ,
TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
150
150
µA
µA
µA
µA
VIN = VCC = 3.465V
V
IN = 0V, VCC = 3.465V
-5
IIL
Input Low Current
nCLK0, nCLK1
VIN = 0V, VCC = 3.465V
-150
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVPECL = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO_LVPECL - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fN
fT
fS
Nominal Frequency
19.44
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
TBD
TBD
70
0
CL
12
4
pF
CO
Shunt Capacitance
Pullability Ratio
pF
CO/C1
ESR
220
240
50
1
Equivalent Series Resistance
Drive Level
Ω
mW
Mode of Operation
Fundamental
843002AKI-41
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REV. A JUNE 1, 2005
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PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
19.44
700
MHz
RMS Phase Jitter, (Random);
NOTE 1
155.52MHz, Integration range:
12kHz - 20MHz
tjit(ø)
0.81
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
105
890
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVCMOS, VCCO_LVPECL = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
19.44
700
MHz
RMS Phase Jitter, (Random);
NOTE 1
155.52 MHz, Integration range:
12kHz - 20MHz
tjit(ø)
0.83
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
95
900
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843002AKI-41
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REV. A JUNE 1, 2005
7
PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TYPICAL PHASE NOISE AT 155.52MHZ
0
-10
-20
-30
-40
Filter
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.81ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Filter to raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. A JUNE 1, 2005
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PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
2V
2.8V 0.04V
2V
SCOPE
SCOPE
VCC
VCCA,
VCCO_LVPECL
,
VCC
VCCA
,
Qx
Qx
VCCO_LVPECL
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VCC
nCLK0,
nCLK1
Phase Noise Mask
VPP
VCMR
Cross Points
nCLK0,
nCLK1
Offset Frequency
f1
f2
VEE
RMS Jitter = Area Under the Masked Phase Noise Plot
DIFFERENTIAL INPUT LEVEL
PHASE JITTER
nQx
Qx
nQA, nQB
QA, QB
tPW
tPERIOD
nQy
tPW
Qy
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
80ꢀ
tF
80ꢀ
VSWING
Clock
20ꢀ
20ꢀ
Outputs
tR
OUTPUT RISE/FALL TIME
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REV. A JUNE 1, 2005
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PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
APPLICATION INFORMATION
DESCRIPTION OF THE PLL STAGES
SETTING THE VCXO PLL LOOP RESPONSE
The ICS843002I-41 is a two stage device, a VCXO PLL
followed by a low phase noise FemtoClock PLL. The VCXO
uses an external pullable crystal which can be pulled
100ppm by the VCXO PLL circuitry to phase lock it to
the input reference frequency. The FemtoClock PLL is a
wide bandwidth PLL (about 800kHz) which means it will
phase track the VCXO PLL. Most of the reference clock
jitter attenuation needs to be accomplished by VCXO PLL.
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by the
user.This includes the values of RS, CS, CP and RSET as shown
in the External VCXO PLL Components figure on this page.
TheVCXO PLL loop bandwidth is approximated by:
RS x ICP x KO
NBW (VCXO PLL) =
32
By using the bypass FemtoClock PLL mode (Table 3B),
the selected input reference clock can be passed directly
to the FemtoClock PLL which will multiply it up by 32 to a
higher frequency. A second mode, VCXO and FemtoClock
bypass, routes the selected input refrence directly to the
LVPECL output dividers.
WHERE:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps (see table on page 12)
KO = VCXO Gain in Hz/V
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by CP. It does,
however, provide a useful approximation of filter performance.
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the VCXO feedback divider value (bandwidth and damp-
ing factor), and by the external loop filter components
(bandwidth, damping factor, and 2nd frequency response).
A practical range of VCXO PLL bandwidth is from about
10Hz to about 1kHz. The setting of VCXO PLL bandwidth
and damping factor is covered later in this document. A
PC based PLL bandwidth calculator is also under devel-
opment. For assistance with loop bandwidth suggestions
or value calculation, please contact ICS applications.
To prevent jitter on the clock output due to modulation of the
VCXO PLL by the phase detector frequency, the following general
rule should be observed:
ƒ (Phase Detector)
NBW (VCXO PLL) ≤
20
ƒ(Phase Detector) = Input Frequency ÷ (R Divider x 32)
The PLL loop damping factor is determined by:
RS
2
ICP x CS x KO
32
DF (VCLK) =
x
WHERE:
CS = Value of capacitor CS in loop filter in Farads
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REV. A JUNE 1, 2005
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PRELIMINARY
ICS843002I-41
Integrated
Circuit
Systems, Inc.
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
EXTERNAL VCXO PLL COMPONENTS
CP establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of CP based on
a CS value that would be used for a damping factor of 1.This will
minimize baseband peaking and loop instability that can lead to
output jitter.
In general, the loop damping factor should be 0.7 or greater to
ensure output stability.A higher damping factor will create less
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
CP also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A CP value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and CP is too small, theVCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
32
31
LF1
LF0
1
2
3
The best way to set the value of CP is to use the filter response
software under development from ICS (please refer to the
following section). CP should be increased in value until it just
starts affecting the passband peak.
ISET
CP
RS
CS
RSET
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response (coming soon) at
www.icst.com. Contact your local sales representative if a tool
cannot be found for this product.
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
should not run underneath the device, the loop filter or crystal
components.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown be-
tween pins 32 to ground and between pins 31 to ground.These
are optional crystal load capacitors which can be used to cen-
ter tune the external pullable crystal (the crystal frequency can
only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be
maintained between components CS and CP in the loop filter:
CS
CP =
20
LOSS OF REFERENCE INDICATOR (LOR0 AND LOR1) OUTPUT PINS.
The LOR0 and LOR1 pins are controlled by the internal clock as an “edge”). The LOR output will otherwise be low. The
activity monitor circuits. The clock activity monitor circuits are activity monitor does not flag excessive reference transitions in
clocked by the VCXO PLL phase detector feedback clock. an phase detector observation interval as an error.The monitor
The LOR output is asserted high if there are three consecutive only distinguishes between transitions occurring and no transi-
feedback clock edges without any reference clock edges (in tions occurring.
both cases, either a negative or positive transition is counted
843002AKI-41
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REV. A JUNE 1, 2005
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PRELIMINARY
ICS843002I-41
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
NOTES ON SETTING CHARGE PUMP CURRENT
The recommended range for the charge pump current is 50μA
to 300μA. Below 50μA, loop filter charge leakage, due to PCB or
capacitor leakage, can become a problem.This loop filter leakage
can cause locking problems, output clock cycle slips, or low
frequency phase noise.
As can be seen in the loop bandwidth and damping factor
equations or by using the filter response software available from
ICS, increasing charge pump current (ICP) increases both
bandwidth and damping factor.
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET
17.6k
8.8k
4.4k
2.2k
Charge Pump Current (ICP)
62.5µA
125µA
250µA
500µA
1E-3
100E-6
10E-6
1k
10k
100k
RSET, Ω
FIGURE 1. CHARGE PUMP CURRENT VS. VALUE OF RSET (EXTERNAL RESISTOR) GRAPH
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PRELIMINARY
ICS843002I-41
Integrated
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843002I-41 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, andVCCO_X
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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PRELIMINARY
ICS843002I-41
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
ICS843002I-41
Integrated
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 5A to 5E show inter- For example in Figure 5A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers.If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS843002I-41
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
SINGLE ENDED CLOCK INPUT INTERFACE
When using a LVCMOS or LVTTL clock driver, the clock capacitance, this resistor acts as a low pass signal filter.
input is connected to the CLKx (CLK0 or CLK1) input pin.The The typical value for this optional series filter resistor is 100Ω.
nCLKx (nCLK0 or nCLK1) pin is left unconnected. To help This will lower both the amplitude and edge rate of the clock
reduce interference with the internal VCO circuits, an external input signal. In the case of a very short clock trace a series
resistor can be placed in series with the clock signal right termination resistor may not be needed.
near the CLKx input pin. Combined with the input pin
Optional
Series
Filter
3.3V
3.3V
Series
Termination
Resistor
CLKx
CLK
LVTTL or
LVCMOS
50kΩ
50kΩ
nCLKx
(no connection)
nCLK
Differential
Input Stage
50kΩ
External Circuitry
Internal Device Circuitry
FIGURE 6. SINGLE-ENDED CLOCK INPUT INTERFACE
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I-41.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I-41 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 175mA = 606.375mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 606.375mW + 60mW = 666.38mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming an
air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 34.8°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.666W * 34.8°C/W = 108.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN VFQFN, FORCED CONVECTION
θJA vs. Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS843002I-41
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR A 32 LEAD VFQFN
θJA vs. Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS843002I-41 is: 5536
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ICS843002I-41
Integrated
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
PACKAGE OUTLINE - K SUFFIX FOR A 32 LEAD VFQFN
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
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Integrated
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700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843002AKI-41
ICS843002AKI-41T
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
ICS43002A41
ICS43002A41
32 Lead VFQFN
32 Lead VFQFN
2500 tape & reel
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843002AKI-41
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