ICS843002BY-31T [IDT]
PLL/Frequency Synthesis Circuit;
| 型号： | ICS843002BY-31T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL/Frequency Synthesis Circuit 时钟 外围集成电路 |
| 文件： | 总28页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ VCXO BASED
FREQUENCY TRANSLATOR/JITTER ATTENUATOR
ICS843002-31
GENERAL DESCRIPTION
FEATURES
The ICS843002-31 is
a member of the
• Outputs:
ICS
HiPerClockS™
HiperClockS™ family of high performance clock
solutions from IDT. This monolithic device is a high-
performance, PLL-based synchronous clock
generator and jitter attenuation circuit. The
• Two high frequency differential LVPECL outputs
Output frequency: up to 700MHz
• One LVCMOS/LVTTL VCXO PLL output with output enable
• One Reference clock output with output enable
• One LOCK detect output
ICS843002-31 contains two clock multiplication stages that are
cascaded in series. The first stage is a VCXO-based PLL that
is optimized to provide reference clock jitter attenuation, to be
jitter tolerant, and to provide a stable reference clock for the
second multiplication stage.The second stage is the proprietary
IDT FemtoClock™circuit which is a high-frequency, sub-
picosecond clock multiplier.
• Input mux supports 3 selectable inputs: one differential input
pair and two LVCMOS/LVTTL input clocks
• 13-bit VCXO PLL feedback and reference dividers provide
wide range of frequency translation ratio options
• FemtoClock frequency multiplier supports rate of:
The VCXO PLL has an on-chip VCXO circuit that uses an
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
dividers supporting complex PLL multiplication ratios and
input reference clock rates as low as 2.3kHz. External loop
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter atten-
uation of a recovered data clock.
560MHz - 700MHz
• ‘Lock Detect’ output reports lock status of VCXO PLL
• VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below (user adjustable)
• RMS phase jitter, random at 12kHz to 20MHz:
<1ps (design target)
The FemtoClock circuit can multiply the VCXO crystal frequency
by a factor of 28 or 32 (selectable) and provide a clock output of
up to 700MHz.
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
Clock Input/Output Configuration:
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Clock Inputs - one differential pair, two singled ended
(mux selected)
• Differential input pair can support LVPECL, LVDS,
LVHSTL, SSTL, HCSL or single-ended LVCMOS
or LVTTL levels
PIN ASSIGNMENT
• Singled ended inputs can support LVCMOS or
LVTTL levels
64 63 62 61 60 59 58 57 56 55 54 53 52 5150 49
• Clock Outputs, FemtoClockS two LVPECL pairs
(selectable output dividers)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VEE
LF1
LF0
2
REF_CLK
VCLK
LOCK
VCCO_CMOS
nQB
3
• Clock Output, VCXO – one single ended output
(at VCXO crystal frequency)
ISET
VEE
4
5
NV1
• Clock Output, other – VCXO reference clock
6
NV0
ICS843002-31
64-Lead TQFP, EPAD
10mm x 10mm x 1.0mm
package body
7
QB
VCC
8
VEE
MR
Example Applications:
9
nQA
CLK0
nCLK0
OE_REF
CLK1
VCC
• SONET/SDH line card clock generator (up to 622.08MHz
for OC-48) using 8kHz frame clock as input reference
10
11
QA
Y package
Top View
VCCO_PECL
MP
• Jitter attenuation of a recovered communications clock
12
13
14
NPB0
NPB1
NPB2
VCCA
• Complex-ratio clock frequency translation between
various communication protocols, such as:
• For telecom, OC-12 to E3 rate conversion, 622.08MHz
to 34.368MHz, PLL ratio of 179/32
SEL1
SEL0
CLK2
15
16
1718 19 20 2122 23 2425 26 27 28 29 30 31 32
• For digital video, ITU-R601 to SMPTE 252M/59.94,
27MHz to 74.17582MHz, PLL ratio of 250/91
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
BLOCK DIAGRAM - NOMINAL SYSTEM CONFIGURATION
3
NPB[2:0]
3
NPA[2:0]
2
NV[1:0]
VCXO PLL Output
Divider NV[1:0]
ISET
VCLK
Charge Pump Current
00: ÷1
01: ÷12
10: ÷16
11: Disabled Drive Low
External Loop
Filter Connection
LF0 LF1
CLK0
00
17.5 - 25MHz
nCLK0
QA Output
Divider NPA[2:0]
CLK1
CLK2
01
10
000: ÷1
001: ÷2
010: ÷4
011: ÷8
100: ÷12
101: ÷14
110: ÷16
111: Disabled
Drive Low
FemtoClock™
Frequency
Multiplier
Input Divider
QA
nQA
XOIN[12:0]
÷1 to ÷8191
VCXO PLL
0: x32
1: x28
QB Output
Divider NPB[2:0]
11 Bypass
VCXO PLL
Feedback Divider
000: QA ÷1
001: QA ÷2
010: QA ÷4
011: QA ÷8
QB
nQB
SEL1
SEL0
XOFB[12:0]
÷1 to ÷8191
100: XOIN Output
101: OFB Output
110: MP Output
111: Disabled
Drive Low
13
>1
1
XOIN[12:0]
XOFB[12:0]
MP
13
REF_CLK
LOCK
OE_REF
LOCK Detect
NOTE 1: For application configuration (non-test/bypass modes).
NOTE 2: Bold lines
are primary clock paths (non-control/non-feedback lines).
Not all control lines and signal paths are shown in this simplified block diagram.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
SIMPLIFIED BLOCK DIAGRAM - CLOCK SIGNAL PATHS IN BYPASS MODE
VCXO PLL Output
Divider NV[1:0]
ISET
Charge Pump
Current
VCLK
00: ÷1
01: ÷12
10: ÷16
External Loop
Filter Connection
11: Disabled Drive Low
17.5 - 25MHz
QA Output
Divider NPA[2:0]
LF0 LF1
CLK0
1 1 Bypass
NPA[2:0]
000: ÷1
nCLK0
001: ÷2
010: ÷4
011: ÷8
100: ÷12
101: ÷14
110: ÷16
111: Disabled Drive Low
CLK1
CLK2
0 1
1 0
QA
FemtoClock™
Frequency
Multiplier
Input Divider
XOIN[12:0]
÷1 to ÷8191
nQA
VCXO PLL
000: ÷1
001: ÷2
QB
010: ÷4
nQB
011: ÷8
111: Disabled
FemtoClock™
Feedback Divider
VCXO PLL
Feedback Divider
XOFB[12:0]
MP
0: ÷32
1: ÷28
110: MP
÷1 to ÷8191
101: XOFB
100: XOIN
NPB2
NPB1
NPB0
NOTE 1: Setting SEL1:SEL0 = 11 enables bypass mode.
Only clock signals on the CLK0/nCLK0 input pair are routed
to the device in bypass mode.
NOTE 2: Bold lines
show clock bypass paths.
Not all control lines and signal paths are shown in this
simplified block diagram.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT PAGE)
Number
Name
Type
Analog
Input/Output
Description
1, 2
LF1, LF0
Loop filter connection pins.
Analog
Input/Output
3
ISET
VEE
Charge pump current setting pin.
4, 41, 48
5, 6
Power
Negative supply pins. Normally connected to ground.
VCXO PLL output divider control pins.
LVCMOS/LVTTL interface levels.
NV1, NV0
VCC
Input
Pullup
7, 13
Power
Core power supply pins.
Master Reset. When HIGH, resets all internal dividers and
8
MR
Input
Pulldown LVCMOS outputs are in high impedance.
LVCMOS / LVTTL interface levels.
9
CLK0
Input
Input
Pulldown Non-inverting differential clock input.
Pullup/ Inverting differential clock input.
Pulldown VCC/2 bias voltage when left floating.
10
nCLK0
Output enable control for reference clock output. When logic LOW,
Pulldown the reference clock output is in high impedance. When logic HIGH,
the output is enabled. LVCMOS/LVTTL interface levels.
11
OE_REF
Input
12
14, 15
16
CLK1
SEL1, SEL0
CLK2
Input
Input
Input
Pulldown Clock input. LVCMOS/LVTTL interface levels.
Pulldown Input clock select. LVCMOS/LVTTL interface levels.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
17, 18,
19, 20,
21, 22,
23, 24,
25, 26,
27, 28
VCXO PLL input divider control input.
Pulldown
XOIN12:XOIN1
XOIN0
Input
LVCMOS/LVTTL interface levels.
VCXO PLL input divider control input.
Pullup
29
Input
LVCMOS/LVTTL interface levels.
30, 31,
32
NPA2, NPA1,
NPA0
LVPECL output divider control for QA/nQA outputs.
LVCMOS/LVTTL interface levels.
Input
Power
Input
Pulldown
33
VCCA
Analog supply pin.
34, 35,
36
NPB2, NPB1,
NPB0
LVPECL output divider control for QB/nQB outputs.
Pulldown
LVCMOS/LVTTL interface levels.
FemtoClock™ circuit clock multiplication control input.
Pulldown When HIGH, selects 28. When LOW, selects 32.
LVCMOS/LVTTL interface levels.
37
MP
Input
38,
39, 40
42, 43
44
VCCO_PECL
QA, nQA
QB, nQB
VCCO_CMOS
LOCK
Power
Output
Output
Power
Output
Output
Output
Output power supply pin for LVPECL clock outputs.
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
Output power supply pin for LVCMOS outputs.
45
Lock detect output. LVCMOS/LVTTL interface levels.
VCXO PLL clock output. LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
46
VCLK
47
REF_CLK
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED FROM PREVIOUS PAGE)
Number
Name
Type
Description
49, 50,
51, 52,
53, 54,
55, 56,
57, 58,
59. 60
VCXO feedback divider control input.
LVCMOS/LVTTL interface levels.
XOFB12:XOFB1
Input
Input
Pulldown
VCXO feedback divider control input.
LVCMOS/LVTTL interface levels.
61
XOFB0
Pullup
XTAL_OUT,
XTAL_IN
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
62, 63
64
Input
VCCA_XO
Power
Analog power supply pin for VCXO.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
V
CC, VCCA, VCCA_XO, VCCO_CMOS,
VCCO_PECL = 3.465V
Power Dissipation Capacitance
(per LVCMOS output)
CPD
TBD
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
SECTION 1. FREQUENCY TRANSLATION
The ICS843002-31 is a two stage device, a VCXO PLL stage
followed by a low phase noise FemtoClock multiplier stage. The
VCXO uses a pullable crystal to lock to the reference clock and
can provide an output frequency up to 25MHz on the single-
ended VCLK output. For higher frequencies, the low phase noise
FemtoClock can multiply the VCXO PLL output clock up to
700MHz on 2 differential LVPECL output pairs (QA/nQA, QB/
nQB).
➥ Set the QB/nQB output divider control pins,
NPB[2:0] = 010 for divide by 4. This sets the QB/nQB
LVPECL output pair for 155.52MHz.
2. T1 to T3. (1.544MHz to two 44.736MHz outputs)
Since 44.736MHz is slightly higher than the maximum VCXO
output frequency, the FemtoClock circuit will have to be used.
➥ Using a pullable 22.368MHz on XTAL_IN/XTAL_OUT,
setthe VCXO PLL feedback divider pins, XOFB[12:0]
to 2796 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 22.368MHz
(1.544MHz * 2796/193 = 22.368MHz).
The VCXO PLL stage has a 13-bit input divider and a 13-bit
feedback divider to generate large integer ratios needed for
some frequency translation applications. When configuring
the device is to use pullable crystals in the 17.5MHz – 25MHz
range on the VCXO PLL stage, and ensure that the
FemtoClock PLL is kept within its range of 560MHz to 700MHz.
➥ Set the FemtoClock multiplication control pin, MP, to
28 which sets the VCO at 626.304MHz.
➥ Set the QA/nQA output divider control pins,
NPA[2:0] = 101 for divide by 14. This sets the QA/nQA
LVPECL output pair for 44.736MHz.
Below are 3 examples:
1. 8kHz to 622.08MHz and 155.52MHz
➥ Set the QB/nQB output divider control pins,
NPB[2:0] = 000 for divide by 1. This sets the QB/nQB
LVPECL output pair for 44.736MHz
This frequency translation requires use of both the VCXO PLL
and the FemtoClock circuit. The VCXO PLL can be used to
multiply up to 19.44MHz for use as a reference clock for the
FemtoClock which will do the multiplication from 19.44MHz to
622.08MHz.
3. T1 to E1. (1.544MHz to two 2.048MHz outputs)
The 2.048MHz output frequency requirement is low enough
that the FemtoClock circuit is not required. Only the VCXO stage
is used for this frequency translation.
➥ Using a 19.44MHz pullable crystal on XTAL_IN/
XTAL_OUT, set the VCXO PLL feedback divider pins,
XOFB[12:0], to 2430. This multiplies the 8kHz refer-
ence clock to 19.44MHz.
➥ Using a pullable 24.576MHz on XTAL_IN/XTAL_OUT,
setthe VCXO PLL feedback divider pins, XOFB[12:0]
to 3072 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 2.048MHz
(1.544MHz * 3072/193 = 24.576MHz).
➥ Set the FemtoClock multiplication control pin, MP, to
0 which sets the multiplication factor to 32. This sets
the FemtoClock VCO to 622.08MHz.
➥ Set the QA/nQA output divider control pins,
NPA[2:0] = 000 for divide by 1. This sets the QA/nQA
LVPECL output pair for 622.08MHz.
➥ Set the VCXO PLL Output Divider control pins,
NV[1:0] = 01 for /12. This divides the 24.576MHz VCXO
PLL frequency down to 2.048MHz.
SECTION 2. FREQUENCY CONFIGURATION
The Frequency Configuration Table Examples (see the following
pages) are intended to show the most common frequency
translation requirements. It is sorted in order of descending
input frequency. It is not intended to be an exhaustive configur-
ation table because that would be impractical with almost 3
billion possible configurations. As far as configuration is
concerned, frequencies <= 25MHz can be generated with the
VCXO PLL while frequencies > 25MHz require the use of the
downstream FemtoClock which can multiply the VCXO PLL
output up to 700MHz. Complex integer ratios are handled with
the VCXO PLL stage and the FemtoClock circuit can be
configured to multiply the VCXO PLL output by 32 or 28. The
following example will illustrate the configuration process.
this means there are 2 viable VCXO PLL crystal choices which
fall within its 17.5MHz – 15MHz range: 22.217143MHz (/28
feedback divider) or 19.44MHz (/32 feedback divider). Use of
the /28 feedback divider for the FemtoClock multiplier will give
slightly better phase noise, but in this case 22.217143/1.544
cannot be exactly achieved with the 13-bit input and feedback
VCXO PLL dividers. Using the x32 setting of the FemtoClock
allows a ratio of 19.44/1.544 = 2430/193 which is easily
achievable. So the FemtoClock would be set for x32 and a
19.44MHz crystal would be used. The VCXO PLL input divider
would be set for 193 and the VCXO PLL feedback divider would
be set for 2430. To double check the solution, perform the
following calculation: 1.544 * 2430 * 32/193 = 622.08MHz.
nd
Assume you have a 1.544MHz T1 clock which needs to be
multiplied up to 622.08MHz (OC12). Obviously, the FemtoClock
multiplier will be needed to achieve 622.08MHz. Since the
FemtoClock has a selectable multiplication factor of 28 or 32,
The 2 FemtoClock multiplier output, QB/nQB, can be set to equal
the QA/nQA output frequency or a fraction of its frequency. The
following fractional values are available: /1, /2, /4, /8.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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PRELIMINARY
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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PRELIMINARY
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
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PRELIMINARY
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PRELIMINARY
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
-0.5V to VCCO + 0.5V
I
Outputs, VO (LVCMOS)
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
22.3°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VCCA, VCCA_XO Analog Supply Voltage
VCCO_CMOS,
Output Supply Voltage
VCCO_PECL
3.135
3.3
3.465
V
IEE
Power Supply Current
Analog Supply Current
395
15
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
MP, MR, OE_REF, SEL0, SEL1,
2
VCC + 0.3
0.8
V
V
-0.3
XOIN[12:1], NPA[2:0], NPB[2:0],
CLK1, CLK2, XOFB[12:1]
V
CC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
NV0, NV1, XOIN0, XOFB0
VCC = VIN = 3.465V
VCC = 3.465V,
MP, MR, OE_REF, SEL0, SEL1,
XOIN[12:1], NPA[2:0], NPB[2:0],
CLK1, CLK2, XOFB[12:1]
-5
V
IN = 0V
VCC = 3.465V,
IN = 0V
Input
Low Current
IIL
NV0, NV1, XOIN0, XOFB0
-150
2.6
µA
V
V
Output
REF_CLK, VCLK, LOCK;
High Voltage NOTE 1
VOH
VOL
Output
REF_CLK, VCLK, LOCK;
Low Voltage NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO_CMOS/2.
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PRELIMINARY
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
CLK0
nCLK0
CLK0
150
5
µA
µA
µA
IIH Input High Current
V
-150
-5
IIL
Input Low Current
nCLK0
VIN = 0V, VCC = 3.465V
µA
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_PECL = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO_PECL - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fN
fT
fS
Nominal Frequency
19.44
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
TBD
TBD
70
0
CL
12
4
pF
CO
Shunt Capacitance
Pullability Ratio
pF
CO/C1
ESR
220
240
50
1
Equivalent Series Resistance
Drive Level
Ω
mW
Mode of Operation
Fundamental
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
35
Typical
Maximum
700
Units
MHz
MHz
MHz
MHz
ps
QA/nQA
QB/nQB
VCLK
4.375
700
fOUT
Output Frequency
1.1875
25
REF_CLK
200
Random jitter
1.3
0.75
1.5
3.5
1
OC-48 mask (12kHz - 20MHz)
19.44MHz input, into CLK0
622.08MHz output;
Deterministic jitter
ps
ps
Total jitter
NOTE 1, 2
mUI
ps
Random jitter
OC-12 mask (250kHz - 5MHz)
19.44MHz input, into CLK0
155.52MHz output;
Deterministic jitter
0.5
1.1
0.7
1
ps
ps
Total jitter
NOTE 1, 3
mUI
ps
t(J)
Timing Jitter, RMS
Random jitter
OC-48 mask (12kHz - 20MHz)
8kHz input, into CLK2
622.08MHz output;
NOTE 1, 2
Deterministic jitter
0.3
1.1
2.7
0.9
0.19
0.9
0.6
ps
ps
Total jitter
mUI
ps
Random jitter
OC-12 mask (250kHz - 5MHz)
8kHz input, into CLK2
155.52MHz output;
NOTE 1, 3
Deterministic jitter
ps
ps
Total jitter
mUI
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
20ꢀ to 80ꢀ
200
700
QA/QB @ 622.08MHz
50
50
ꢀ
VCLK, REF_CLK @ 19.44MHz
ꢀ
tLOCK
100
ms
See Parameter Measurement Information section.
NOTE 1: External crystal is 19.44MHz Eliptek ECX-5451.
NOTE 2: Loop bandwidth (-3dB) = 180Hz; Loop Damping Factor = 5.3 (see Applications Section, Example Loop Filter Component Value,
example case #4).
NOTE 3: Loop bandwidth (-3dB) = 19Hz; Loop Damping Factor = 2.8 (see Applications Section, Example Loop Filter Component Value
example case #2).
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 14
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
1.65V 5ꢀ
SCOPE
,
SCOPE
,
VCC
VCC
Qx
,
,
VCCA
VCCA
VCCA_XO,
VCCO_CMOS
LVCMOS
VCCA_XO,
VCCO_PECL
Qx
LVPECL
nQx
GND
VEE
-1.65V 5ꢀ
-1.3V 0.165V
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
nQA
QA
VDDO
VCLK
2
nQB
VDDO
REF_CLK
2
QB
tsk(o)
tsk(o)
LVPECL OUTPUT SKEW
LVCMOS OUTPUT SKEW
80ꢀ
tF
80ꢀ
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
20ꢀ
20ꢀ
Clock
Outputs
20ꢀ
Clock
Outputs
tR
LVPECL OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 15
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
Phase Noise Plot
nQA, nQB
QA, QB
tPW
Phase Noise Mask
tPERIOD
tPW
Offset Frequency
odc =
x 100ꢀ
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
VCCO_LVCMOS
2
VCLK,
REF_CLK
tPW
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 16
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
APPLICATION INFORMATION
DESCRIPTION OF THE PLL STAGES
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the -3dB
bandwidth. NBW does not take into account the effects of damp-
ing factor or the second pole imposed by CP. It does, however,
provide a useful approximation of filter performance.
The ICS843002-31 is a two stage frequency multiplication device,
a VCXO PLL followed by a low phase noise FemtoClock frequency
multiplier. The VCXO uses an external pullable crystal which can
be pulled 100ppm by the VCXO PLL circuitry to phase lock it to
the input reference frequency. The output frequency of the VCXO
PLL is equal to that of the external pullable crystal, which is in the
range of 17.5MHz to 25MHz. The loop bandwidth VCXO PLL is
typically set in the range of 10-250Hz which provides attenuation
of input reference clock jitter.Since the VCXO is a high-Q oscillator
circuit, it has low intrinsic output jitter and phase noise.The VCXO
PLL output clock is available from the VCLK pin.
To prevent jitter on VCLK due to modulation of the VCXO PLL by
the phase detector frequency, the following general rule should
be observed:
ƒ (Phase Detector)
NBW (VCXO PLL) ≤
20
The FemtoClock frequency multiplier has an effective control
bandwidth of about 800kHz which means it will track the VCXO
PLL clock output.
ƒ(Phase Detector) = Input Frequency ÷ XOIN
The PLL loop damping factor is determined by:
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the setting of the VCXO feedback divider value (XOFB) and
by the external loop filter components. A practical range of loop
bandwidth for many applications is 25Hz to 1kHz. A bandwidth
of less than 10Hz requires careful component selection and
possible metal shielding to prevent clock output wander. A damp-
ing factor of 0.7 or greater should be used to ensure loop stability.
When a passband peaking of <0.1dB is desired for SONET/SDH
loop timing application, the damping factor should be 6 or higher.
RS
2
ICP x CS x KO
DF (VCLK) =
x
XOFB Divider
WHERE:
CS = Value of capacitor CS in loop filter in Farads
optional
optional
A PC base PLL bandwidth calculator is also under development.
For assistance with loop filter bandwidth and component selec-
tion suggestions, please contact your IDT sales representative.
64
1
63
62
LFR
LF
2
3
RS
CS
ISET
SETTING THE VCXO PLL LOOP RESPONSE
CP
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by the
user. This includes the values of RS, CS, CP and RSET as shown
in the External VCXO PLL Components figure on this page.
RSET
The VCXO PLL loop bandwidth is approximated by:
RS x ICP x KO
NBW (VCXO PLL) =
32
FIGURE 1. EXTERNAL VCXO PLL COMPONENTS
WHERE:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps (see table on page 17)
KO = VCXO Gain in Hz/V (see table on page 18)
XOFB Divider = 1 to 8191
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be
maintained between components CS and CP in the loop filter:
The best way to set the value of CP is to use the filter response
software under development from ICS (please refer to the follow-
ing section). CP should be increased in value until it just starts
affecting the passband peak.
CS
CP =
20
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
CP establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of CP based on
a CS value that would be used for a damping factor of 1. This will
minimize baseband peaking and loop instability that can lead to
output jitter.
In the loop filter schematic diagram, capacitors are shown between
pins 62 to ground and between pins 63 to ground. These are
optional crystal load capacitors which can be used to center tune
the external pullable crystal (the crystal frequency can only be
lowered by adding capacitance, it cannot be raised). Note that
the addition of external load capacitors will decrease the crystal
pull range and the Kvco value.
CP also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A CP value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and CP is too small, the VCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
NOTES ON SETTING CHARGE PUMP CURRENT
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
The recommended range for the charge pump current is 50μA
to 500μA. Below 50μA, loop filter charge leakage, due to PCB
or capacitor leakage, can become a problem. This loop filter
leakage can cause locking problems, output clock cycle slips,
or low frequency phase noise.
RSET
17.6K
8.8K
4.4K
2.2K
Charge Pump Current (ICP)
62.5µA
125µA
250µA
500µA
As can be seen in the loop bandwidth and damping factor
equations or by using the filter response software available
from ICS, increasing charge pump current (ICP) increases both
bandwidth and damping factor.
1E-3
100E-6
10E-6
1k
10k
100k
RSET, Ω
FIGURE 2. CHARGE PUMP CURRENT VS. VALUE OF RSET
(EXTERNAL RESISTOR) GRAPH
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
VCXO GAIN (KO) VS. XTAL FREQUENCY
9000
8000
7000
KVCO
(Hz/V)
6000
5000
4000
16
18
20
22
24
26
XTAL Frequency (MHz)
EXAMPLE LOOP FILTER COMPONENT VALUE
Device Configuration
Loop Filter Component Selection
VCXO PLL Performance
Example
Case
Number
Input
Reference
Clock
XTAL
Frequency
(MHz)
RSET
RS
CS
CP
Loop BW
(-3dB)
(MHz)
Loop Passband
Damping Peaking
XOIN
XOFB
MP
Resistor Resistor Cap
Cap
(µF)
Divider Divider Divider
(kΩ)
(kΩ)
(µF)
Factor
(dB)
1
2
3
4
8kHz
8kHz
19.44
19.44
19.44
19.44
1
1
2430
2430
32
0
0
0
0
4.5
150
10
0.01
18
19
5.8
0.1
4.5
150
11
2.2 0.01
2.8
2.7
5.3
0.3
0.3
0.1
19.44kHz
19.44MHz
32
8
9.09
9.09
10
10
0.01
0.01
65
8
11
180
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 19
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002-31 provides
3.3V
VCC
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA, VCCA_XO, and
VCCO_X should be individually connected to the power supply
plane through vias, and bypass capacitors should be used for
each pin. To achieve optimum jitter performance, power supply
isolation is required. Figure 3 illustrates how a 10Ω resistor
along with a 10μF and a .01μF bypass capacitor should be
connected to each VCCA pin.
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK0 /nCLK0 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4D show interface
examples for the HiPerClockS CLK0/nCLK0 input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 20
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
DIFFERENTIAL CLOCK INPUT CIRCUIT
USING THE DIFFERENTIAL INTERFACE FOR SINGLE-ENDED CLOCKS
The differential interface (CLK0/nCLK0) can be used as a third
single-ended input to support an LVCMOS or LVTTL clock
driver. The clock input is connected to the CLK0 input pin,
and the nCLK0 pin is left unconnected. To help reduce interfer-
ence with the internal VCO circuits, an external resistor can be
placed in series with the clock signal near the CLK0 input pin.
Combined with the input pin capacitance, this resistor acts as
a low pass signal filter. The typical value of this optional series
filter resistor is 100Ω. This will lower both the amplitude and
edge rate of the clock input signal. In the case of a very short
clock trace a series termination register may not be needed.
Optional
Series
3.3V
3.3V
Filter
Resistor
Series
Termination
CLK0
CLK
LVTTL
or LVCMOS
Logic Output
51k
51k
nCLK0
(no connection)
nCLK
Differential
Input Stage
51k
External Circuitry
Internal Device Circuitry
FIGURE 5. SINGLE-ENDED CLOCK INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 21
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
THERMAL RELEASE PATH
The exposed metal pad provides heat transfer from the
device to the P.C. board. The exposed metal pad is ground pad
connected to ground plane through thermal via.The exposed pad
on the device to the exposed metal pad on the PCB is contacted
through solder as shown in Figure 6. For further information,
please refer to the Application Note on Surface Mount Assembly
of Amkor’s Thermally /Electrically Enhance Leadframe Base
Package, Amkor Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
FIGURE 6. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 7A and 7B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 7A. LVPECL OUTPUT TERMINATION
FIGURE 7B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 22
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 395mA = 1368.67mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
(3.465V, with all outputs switching) = 1368.67mW + 60mW = 1428.67mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.429W * 17.2°C/W = 94.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 64-PIN TQFP, E-PAD FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3°C/W
17.2°C/W
15.1°C/W
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 24
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD
JA
θ vs. 0 Air Flow (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3°C/W
17.2°C/W
15.1°C/W
TRANSISTOR COUNT
The transistor count for ICS843002-31 is: 10,095
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 25
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FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, EPAD (32 pin package depicted to define Table 9 dimension symbols)
TABLE 9. PACKAGE DIMENSIONS FOR 64 LEAD TQFP, EPAD
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ACD-HD
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
64
A
--
--
0.10
1.20
0.15
1.05
0.27
0.20
A1
0.05
0.95
0.17
0.09
A2
1.0
b
0.22
c
--
D
12.00 BASIC
10.00 BASIC
7.50 Ref.
12.00 BASIC
10.00 BASIC
7.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
θ
0.45
0.75
--
0°
7°
ccc
--
4.5
--
0.08
5.5
D3 & E3
5.0
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 26
ICS843002BY-31 REV. C JULY 13, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843002BY-31
Marking
Package
Shipping Packaging Temperature
ICS843002BY31
ICS843002BY31
ICS843002BY31L
ICS843002BY31L
64 Lead TQFP, EPAD
tray
0°C to 70°C
ICS843002BY-31T
ICS843002BY-31LF
ICS843002BY-31LFT
64 Lead TQFP, EPAD
500 tape & reel
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
64 Lead "Lead-Free" TQFP, EPAD
64 Lead "Lead-Free" TQFP, EPAD
500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 27
ICS843002BY-31 REV. C JULY 13, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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