ICS843002ALF [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS ™ CRYSTAL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS843002ALF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS843002 is a 2 output LVPECL synthesizer • Two 3.3V LVPECL outputs
ICS
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz, 18pF
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
HiPerClockS™
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002 uses ICS’ 3rd generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements.The ICS843002 is packaged in a small 20-pin
TSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter (637kHz - 10MHz): 0.72ps (typical)
• Typical phase noise at 212.5MHz
Phase noise:
Offset
Noise Power
100Hz ............... -87.7 dBc/Hz
1KHz ..............-111.6 dBc/Hz
10KHz ..............-124.3 dBc/Hz
100KHz ..............-124.3 dBc/Hz
• Full 3.3V supply mode
• Lead-Free package RoHS compliant
• -30°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
Inputs
1
20
19
18
17
16
15
14
13
12
11
nc
VCCO
VCCO
Output
Frequency
(MHz)
2
3
4
5
6
7
8
9
Q1
nQ1
VEE
VCC
nXTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
F_SEL1
Input
M Divider N Divider
Frequency F_SEL1 F_SEL0
M/N
Divider Value
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
Value
Value
(MHz)
26.5625
0
0
1
1
0
0
1
0
1
0
24
24
24
24
24
3
4
8
6
4
2
8
212.5
159.375
106.25
53.125
187.5
26.5625
26.5625
26.5625
23.4375
6
10
12
3
ICS843002
20-LeadTSSOP
6.5mm x 4.4mm x 0.92mm
BLOCK DIAGRAM
package body
G Package
Top View
Pulldown
2
F_SEL[1:0]
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
nQ0
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
Pulldown
TEST_CLK
1
0
1
0
26.5625MHz
Q1
XTAL_IN
OSC
VCO
637.5MHz
(w/26.5625MHz
Reference)
Phase
Detector
nQ1
XTAL_OUT
Pulldown
nXTAL_SEL
M = 24 (fixed)
Pulldown
MR
843002AG
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REV. B MAY 6, 2005
1
ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 7
Name
nc
Type
Unused
Description
No connect.
2, 20
3, 4
VCCO
Power
Ouput
Output supply pins.
Q0, nQ0
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
5
MR
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
6
nPLL_SEL
VCCA
Input
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8
Power
Input
Power
Input
Input
Analog supply pin.
F_SEL0,
F_SEL1
9, 11
10, 16
12, 13
14
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VCC
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
TEST_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
15
nXTAL_SEL
Input
17
VEE
Power
Output
Negative supply pins.
18, 19
nQ1, Q1
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 10ꢀ, TA = -30°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
2.97
2.97
2.97
3.3
3.3
3.3
3.63
3.63
3.63
135
100
15
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
V
V
mA
mA
mA
mA
ICC
ICCA
ICCO
31
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 10ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
2
VCC + 0.3
V
V
V
nPLL_SEL, nXTAL_SEL,
F_SEL0, F_SEL1, MR
-0.3
-0.3
0.8
Input
Low Voltage
VIL
TEST_CLK
1.0
TEST_CLK, MR,
Input
High Current
IIH
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
VCC = VIN = 3.63V
150
µA
µA
Input
Low Current
IIL
V
CC = 3.63V, VIN = 0V
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 10ꢀ, TA = -30°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
23.33
28.33
50
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 10ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] =11
Minimum Typical Maximum Units
186.67
140
226.67
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.67
20
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
212.5MHz, (637KHz - 10MHz)
159.375MHz, (637KHz - 10MHz)
106.25MHz, (637KHz - 10MHz)
53.125MHz, (637KHz - 10MHz)
20ꢀ to 80ꢀ
0.72
0.76
0.84
0.97
ps
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
46
600
54
ps
F_SEL[1:0] =00
ꢀ
F_SEL[1:0] ≠ 00
49
51
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: See Phase Noise plot.
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 53.125MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
53.125MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.97ps (typical)
Fibre Channel Jitter Filter
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.84ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 159.375MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
159.375MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.76ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 212.5MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
212.5MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.72ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
nQx
Qx
SCOPE
Qx
VCC
VCCA, VCCO
,
nQy
Qy
LVPECL
nQx
VEE
tsk(o)
-1.3V 0.33V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Phase Noise Mask
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Clock
20ꢀ
Outputs
Offset Frequency
f1
f2
tR
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
CRYSTAL INPUT INTERFACE
The ICS843002 has been characterized with 18pF parallel below were determined using a 26.5625MHz 18pF parallel
resonant crystals. The capacitor values shown in Figure 3 resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
ICS843002
Figure 3. CRYSTAL INPUt INTERFACE
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.
Figure 4A shows a schematic example of the ICS843002. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECLTermination Application Note.In this example, an 18 pF
Zo = 50 Ohm
VCC
VCCA
+
R2
10
C3
10uF
C4
0.01u
Zo = 50 Ohm
-
VCC
VCCO
C6
0.1u
R4
50
R6
50
C7
0.1u
Logic Control Input Examples
U1
R5
50
Set Logic
Input to
'1'
Set Logic
Input to
'0'
ICS843002
VCC
VCC
VCC=3.3V
RU1
1K
RU2
Not Install
VCCO=3.3V
Zo = 50 Ohm
To Logic
Input
pins
To Logic
Input
pins
+
-
RD1
RD2
1K
Zo = 50 Ohm
VCCO
Not Install
C8
0.1u
R7
50
R8
50
X1
18pF
C2
33pF
R9
50
26.5625 MHz
C9
0.1u
C1
27pF
FIGURE 4A. ICS843002 SCHEMATIC EXAMPLE
PC BOARD
L
AYOUT
E
XAMPLE
in the Table 6.There should be at least one decoupling capacitor
per power pin.The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
Figure 4B shows an example of ICS843002 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
T
ABLE 6. FOOTPRINT
T
ABLE
Reference
Size
0402
0805
0603
0603
C1, C2
C3
C4, C5, C6, C7, C8
R2
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 4B. ICS843002 PC BOARD LAYOUT EXAMPLE
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 135mA = 490mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 490mW + 60mW = 550mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θ
JA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.550W * 66.6°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843002AG
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REV. B MAY 6, 2005
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ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843002 is: 2578
843002AG
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REV. B MAY 6, 2005
13
ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843002AG
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REV. B MAY 6, 2005
14
ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843002AG
Marking
Package
Shipping Packaging
tube
Temperature
-30°C to 85°C
-30°C to 85°C
-30°C to 85°C
-30°C to 85°C
ICS843002AG
ICS843002AG
ICS843002ALF
ICS843002ALF
20 Lead TSSOP
ICS843002AGT
ICS843002AGLF
ICS843002AGLFT
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an"LF" to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ and FEMTOCLOCKS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or
warrant any ICS product for use in life support devices or critical medical instruments.
843002AG
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REV. B MAY 6, 2005
15
ICS843002
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
A
Table
Page
1
Description of Change
Date
Added 187.5MHz to the Frequency Selection Function Table.
Ordering Information Table - added Lead Free part number.
AC Characteristics Table - corrected typo, fOUT 180.67 min. to 186.67 min.
8/26/04
9/30/04
12/27/04
A
T10
T5
15
A
4
1
Features section - corrected frequency bullet to read "Supports...output
frequencies..." from "...input frequencies...".
A
B
2/7/05
5/6/05
T10
T5
15
4
Ordering Information Table - updated table.
AC Characteristics Table - deleted Propagation Delay.
843002AG
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REV. B MAY 6, 2005
16
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