ICS843002BKI-72LFT [IDT]
Clock Generator, 122.88MHz, 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32;
| 型号： | ICS843002BKI-72LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 122.88MHz, 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32 时钟 外围集成电路 晶体 |
| 文件： | 总18页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ VCXO BASED WCDMA
CLOCK GENERATOR/JITTER ATTENUATOR
ICS843002I-72
GENERAL DESCRIPTION
FEATURES
The ICS843002I-72 is
ICS
a
member of the
• Two differential LVPECL outputs
HiperClockS™ family of high performance clock
solutions from IDT. The ICS843002I-72 is a
PLL based synchronous clock generator that is
optimized for WCDMA channel card applications
• CLK input accepts the following input levels:
LVCMOS or LVTTL levels
HiPerClockS™
• Output frequency: 122.88MHz (typical)
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the second
PLL stage.The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a
low phase noise FemtoClock™VCO. The device performance
and the PLL multiplication ratios are optimized to support
WCDMA applications. The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the
PLL loop bandwidth and damping characteristics for the given
application.
• FemtoClock VCO frequency range: 490MHz - 680MHz
• RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal
(1.875MHz to 10MHz): 0.49ps (typical)
• Deterministic jitter: 30fs (typical)
• Random jitter, RMS: 2.2ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
The ICS843002I-72 can accept a single-ended input. LOCK_DT
reports the lock status of VCXO PLL loop. If the reference clock
input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
• 19.2MHz pullable crystal
• Input Reference clock frequency: 3.84MHz
• Output clock frequency: 122.88MHz
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
LF1
LF0
ISET
VCC
LOCK_DT
VEE
24
23
22
21
20
19
18
17
VCC
VCCO
VCCO
nQ1
VCC
VEE
VEE
Q1
CLK
VEE
9
10 11 12 13 14 15 16
ICS843002I-72
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
BLOCK DIAGRAM
122.88MHz
Q0
3.84MHz
FemtoClock
nQ0
Pulldown
x32
CLK
XTAL_IN
Q1
19.2MHz
Charge
Pump
Phase
Detect
5
÷
VCXO
LF
nQ1
Pullable Xtal
XTAL_OUT
Pulldown
nOE
External
Loop
Components
LF0
LF1
ISET
LOCK_DT
NOTE 1: 19.2MHz pullable crystal shown is typical for WCDMA device applications.
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Description
1, 2
LF1, LF0
Loop filter connection node pins.
Analog
Input/Output
3
ISET
VCC
Charge pump current setting pin.
Core power supply pins.
4, 5, 22, 28,
29, 30
Power
6, 7, 9, 10, 13,
17, 23, 26, 27
VEE
Power
Input
Input
Negative supply pins.
8
CLK
nOE
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, output is enabled.
Pulldown
11
LVCMOS/LVTTL interface levels. See Table 3.
12
14, 20, 21
15, 16
18, 19
24
VCCA
VCCO
Power
Power
Analog supply pin.
Output power supply pin.
Q0, nQ0
Q1, nQ1
LOCK_DT
nc
Output
Output
Output
Unused
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
Lock detect. Logic HIGH when VCXO PLL loop is locked.
No connect.
25
31,
32
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
50
kΩ
TABLE 3. INPUT REFERENCE SELECTION FUNCTION TABLE
Inputs
Outputs
Q0/nQ0, Q1/nQ1
Enabled
nOE
0
1
Hi-Z
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
37°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.3
3.3
3.3
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.13
3.135
3.465
140
V
mA
mA
ICCA
13
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC
= 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.3
3.3
2.5
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.13
2.375
2.625
140
V
mA
mA
ICCA
13
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 3.3V 5ꢀ OR 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
Input High Current CLK, nOE
VCC = VIN = 3.465V
150
µA
µA
IIL
InputLow Current
CLK, nOE
VCC = 3.465V, VIN = 0V
-5
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.4
VCCO - 0.9
VCCO - 1.5
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
122.88
MHz
RMS Phase Jitter, (Random);
NOTE 1
122.88MHz, Integration range:
1.875MHz - 10MHz
tjit(ø)
0.49
ps
tDJ
Deterministic Jitter; NOTE 2
Random Jitter, RMS; NOTE 2
Output Skew; NOTE 3, 4
Output Rise/Fall Time
30
fs
tRJ
2.2
ps
ps
ps
ꢀ
tsk(o)
tR / tF
odc
50
550
51
20ꢀ to 80ꢀ
300
49
Output Duty Cycle
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
122.88
MHz
RMS Phase Jitter, (Random);
NOTE 1
122.88MHz, Integration range:
1.875MHz - 10MHz
tjit(ø)
0.49
ps
tDJ
Deterministic Jitter; NOTE 2
Random Jitter, RMS; NOTE 2
Output Skew; NOTE 3, 4
Output Rise/Fall Time
30
fs
tRJ
2.2
ps
ps
ps
ꢀ
tsk(o)
tR / tF
odc
50
550
51
20ꢀ to 80ꢀ
300
49
Output Duty Cycle
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TYPICAL PHASE NOISE AT 122.88MHZ @ 3.3V/3.3V
122.88MHz
RMS Phase Jitter (Random)
1.875MHz to 10MHz = 0.49ps (typical)
10Gb Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
2.8V 0.04V
2V
2V
2.8V 0.04V
2V
,
SCOPE
V
SCOPE
CC
V
V
CC
V
CCO
Qx
Qx
CCO
VCCA
VCCA
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQx
Qx
Phase Noise Mask
nQy
Qy
Offset Frequency
tsk(o)
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
OUTPUT SKEW
nQ0, nQ1
80ꢀ
tF
80ꢀ
tR
Q0, Q1
VSWING
20ꢀ
tPW
tPERIOD
Clock
Outputs
20ꢀ
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS843002I-72
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
3.3V or 2.5V
VCC
.01µF
10Ω
should be individually connected to the power supply
VCCA
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVPECL OUTPUTS
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”.The number of vias (i.e. “heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
LAYOUT GUIDELINE
Figure 5 shows an example of ICS843002I-72 application
examples of LVPECL terminations are shown in this schematic.
Additional termination approaches are shown in the LVPECL
Termination Application Note.
schematic. In this example, the device is operated at V = 3.3V.
The 19.2MHz pullable crystal is used. The bypass capacitor
should be placed as close as possible to the power pins. Two
CC
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
RU2
Not Install
VCC
VCC
XTAL_OUT
C1
SP
VCC
RU1
1K
X1
To Logic
Input
pins
To Logic
Input
pins
XTAL_IN
C2
RD1
Not Install
RD2
1K
SP
R1
LOCK_DT
U1
2.7K
LD1
3.3V
2-pole loop filter for Mid Bandwidth setting
VCC
R3
133
R4
133
LF
LF
1
24
23
22
21
20
19
18
17
VCCO
LF1
LF0
LOCK_DT
VEE
2
3
4
5
6
7
8
Zo = 50 Ohm
Zo = 50 Ohm
Q1
VCC
R6
VCC
ISET
VCC
VCC
VEE
VEE
CLK
VCC
VCCO
VCC
VCC
VCCO
VCCO
nQ1
Q1
VEE
+
-
C3
100K
C5
VCCO
VEE
CLK
nQ1
0.0001uF
0.1uF
R7
8K
R8
82.5
R9
82.5
VCC=3.3V
VCCO=3.3V
ICS843002I_72
Zo = 50 Ohm
Zo = 50 Ohm
Q0
+
-
VCC
R10 10
VCCA
nQ0
VCC
C6
10u
C7
VCCO
R11
50
R12
50
0.01u
C8
0.1u
R13
50
Optional
Y-Termination
(U1:4)
(U1:5)
(U1:22)
VCC
(U1:28)
(U1:29)
(U1:30)
VCC
(U1:14)
(U1:20) (U1:21)
VCCO
VCCO
VCC
VCC
VCC
C9
0.1uF
C10
0.1uF
C11
0.1uF
C12
0.1uF
C13
0.1uF
C14
0.1uF
C15
0.1uF
C16
0.1uF
C17
0.1uF
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT
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VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
capacitance (C ). In addition, frequency, accuracy and
temperature rangLe must also be considered. Since the pulling
range of a crystal also varies with the package, it is
recommended that a metal-canned package like HC49 be used.
Generally, a metal-canned package has a larger pulling range
than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application
Note.
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C is dependent on the
L
characteristics of the VCXO.The recommended C in the Crystal
Parameter Table balances the tuning range by Lcentering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows R , C
S
S
and C values for recommended high, mid and low loop
P
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to the
Loop Filter Component Selection for VCXO Based PLLs
Application Note.
LF0
LF1
ISET
The crystal and external loop
filter components should be
kept as close as possible to the
The crystal’s load capacitance C characteristic determines its
L
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
RS RSET
device. Loop filter and crystal
CP CS
traces should be kept short and
separated from each other.
any installed tuning capacitors (C ).
TUNE
Other signal traces should be
XTAL_IN
If the crystal’s C is greater than the total external capacitance,
the VCXO will oLscillate at a higher frequency than the crystal
kept separate and not run
underneath the device, loop
filter or crystal components.
CTUNE
19.2MHz
specification. If the crystal’s C is lower than the total external
XTAL_OUT
L
CTUNE
capacitance, the VCXO will oscillate at a lower frequency than
VCXO CHARACTERISTICS TABLE
Symbol Parameter
Typical
Unit
kHz/V
pF
kVCXO
VCXO Gain
7.8
2
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
8
pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
Bandwidth
75Hz (Low)
500Hz (Mid)
1kHz (High)
Crystal Frequency (MHz)
19.2MHz
RS (kΩ)
15
CS (µF)
1.0
CP (µF)
0.01
RSET (kΩ)
8
8
4
19.2MHz
100
0.1
0.0001
0.0001
19.2MHz
100
0.1
CRYSTAL CHARACTERISTICS
Symbol Parameter
Mode of Operation
Minimum Typical
Maximum
Units
Fundamental
fN
fT
fS
Frequency
19.2
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
-40
85
CL
12
4
pF
CO
pF
CO/C1
ESR
220
240
Equivalent Series Resistance
Drive Level
20
1
Ω
mW
ppm
Aging @ 25°C
3 per year
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I-72.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I-72 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 140mA = 485.15mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
(3.465V, with all outputs switching) = 485.1mW + 60mW = 545.1mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.541W * 37°C/W = 105.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 32-PIN VFQFN, FORCED CONVECTION
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
– V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
– V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
– V
/R ] * (V
– V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO_MAX
OH_MAX
L
CCO
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V – (V – 2V))/R ] * (V
– V
) = [(2V – (V
/R ] * (V
– V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
TRANSISTOR COUNT
The transistor count for ICS843002I-72 is: 3199
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
(Ref.)
N & N
Seating Plane
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
(Ref.)
OR
E2
2
TopView
b
e
Thermal
Base
A
(Ref.)
D2
D
N &N
Odd
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package.This draw-
ing is not intended to convey the actual pin count or pin layout of
this device.The pin count and pinout are shown on the front page.
The package dimensions are in Table 11 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
Maximum
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
8
8
NE
D, E
D2, E2
L
5.0 BASIC
3.0
3.3
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
843002BKI-72LF
843002BKI-72LFT
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
ICS002BI72L
ICS002BI72L
32 lead "Lead-Free" VFQFN
32 lead "Lead-Free" VFQFN
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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