ICS843002AKI-41LF [IDT]
Clock Generator, 700MHz, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32;
| 型号： | ICS843002AKI-41LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32 时钟 外围集成电路 晶体 |
| 文件： | 总24页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700MHZ, FEMTOCLOCKTM VCXO BASED
SONET/SDH JITTER ATTENUATOR
ICS843002I-41
General Description
Features
The ICS843002I-41 is a member of the
• Two Differential LVPECL outputs
S
IC
HiperClockS™ family of high performance clock
solutions from IDT. The ICS843002I-41 is a PLL
based synchronous clock generator that is
• Selectable CLKx, nCLKx differential input pairs
HiPerClockS™
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
optimized for SONET/SDH line card applications
where jitter attenuation and frequency translation is needed. The
device contains two internal PLL stages that are cascaded in
series. The first PLL stage uses a VCXO which is optimized to
provide reference clock jitter attenuation and to be jitter tolerant,
and to provide a stable reference clock for the 2nd PLL stage
(typically 19.44MHz). The second PLL stage provides additional
frequency multiplication (x32), and it maintains low output jitter by
using a low phase noise FemtoClock™VCO. PLL multiplication
ratios are selected from internal lookup tables using device input
selection pins. The device performance and the PLL multiplication
ratios are optimized to support non-FEC (non-Forward Error
Correction) SONET/SDH applications with rates up to OC-48
(SONET) or STM-16 (SDH). The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given
line card application.
• Maximum output frequency: 700MHz
• FemtoClock VCO frequency range: 560MHz - 700MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
The ICS843002I-41 includes two clock input ports. Each one can
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
32 31 30 29 28 27 26 25
1
2
3
24
23
22
LF1
LF0
LOR0
LOR1
nc
ISET
Typical ICS843002I-41 configuration in SONET/SDH Systems:
• VCXO 19.44MHz crystal
VCC
VCCO_LVCMOS
VCCO_LVPECL
nQB
4
5
21
20
CLK0
nCLK0
CLK_SEL
QA_SEL2
6
7
8
19
18
17
QB
• Loop bandwidth: 50Hz - 250Hz
VEE
• Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
9
10 11 12 13 14 15 16
• Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz,
Hi-Z
ICS843002I-41
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Block Diagram
19.44 MHz
Pullable
xtal
External
Loop
Components
ISET
ICS843002I-41
LF0
LF1
Phase
Detector
VCCO_LVCMOS
Charge
Pump
and Loop
Filter
R Divider =
1, 2, 4, 8,
16 or 32
19.44 MHz
Divide
by 32
VCXO
CLK1
nCLK1
Activity
Detector
1
0
LOR1
Divide
by 32
CLK0
nCLK0
Activity
Detector
VCXO Jitter Attenuation PLL
LOR0
VCCO_PECL
622.08 MHz
QA
nQA
Cx Divider =
1,2,4,8,16,32,
HiZ or Disable
110
110
CLK_SEL
FemtoClock
PLL
111
111
x32
3
3
QA_SEL2:0
QB
nQB
Cx Divider =
1,2,4,8,16,32,
HiZ or Disable
3
R_SEL2:0
QB_SEL2:0
NOTE: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications.
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Table 1. Pin Descriptions
Number
Name
Type
Description
Analog
Input/Output
1, 2
LF1, LF0
Loop filter connection node pins.
Analog
Input/Output
3
ISET
Charge pump current setting pin.
4
5
VCC
Power
Input
Core power supply pin.
CLK0
Pulldown Non-inverting differential clock input.
Pullup
6
7
8
nCLK0
Input
Input
Input
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown
CLK_SEL
QA_SEL2
Pulldown Input clock select. LVCMOS/LVTTL interface levels. See Table 3A.
Output divider control for QA/nQA LVPECL outputs.
Pulldown
LVCMOS/LVTTL interface levels.See Table 3C.
9,
10
QA_SEL1,
QA_SEL0
Output divider control for QA/nQA LVPECL outputs.
Pullup
Input
Input
Input
LVCMOS/LVTTL interface levels.See Table 3C.
Output divider control for QB/nQB LVPECL outputs.
Pulldown
11
QB_SEL2
LVCMOS/LVTTL interface levels.See Table 3C.
12,
13
QB_SEL1,
QB_SEL0
Output divider control for QB/nQB LVPECL outputs.
Pullup
LVCMOS/LVTTL interface levels.See Table 3C.
14
15, 16
17, 27
18, 19
20
VCCA
QA, nQA
VEE
Power
Output
Power
Output
Power
Power
Unused
Analog supply pin.
Differential clock output pair. LVPECL interface levels.
Negative supply pins.
QB, nQB
VCCO_LVPECL
VCCO_LVCMOS
nc
Differential clock output pair. LVPECL interface levels.
Output supply pin for LVPECL outputs.
Output supply pin for LVCMOS/LVTTL outputs.
No connect.
21
22
Alarm output, loss of reference for CLK1/nCLK1.
LVCMOS/LVTTL interface levels.
23
24
LOR1
LOR0
Output
Output
Alarm output, loss of reference for CLK0/nCLK0.
LVCMOS/LVTTL interface levels.
Pullup
25
26
nCLK1
CLK1
Input
Input
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown
Pulldown Non-inverting differential clock input.
28,
29,
30
R_SEL0,
R_SEL1,
R_SEL2
Input
Input
Pulldown Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B.
31,
32
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. The XTAL_IN is the input.
XTAL_OUT is the output.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
50
50
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Function Tables
Table 3A. Input Reference Selection Function Table
Input
Function
Input Selected
CLK0/nCLK0
CLK1/nCLK1
CLK_SEL
0
1
Table 3B. Input Reference Divider Selection Function Table
Inputs
Function
R_SEL2
R_SEL1
R_SEL0
R Divider Value or State
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1
÷2
÷4
÷8
÷16
÷32
bypass VCXO PLL
bypass VCXO and FemtoClock PLLs
Table 3B. Output Divider Selection Function Table
Inputs
Function
QX_SEL2
QX_SEL1
QX_SEL0
Output Divider Value or State
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output QX/nQX (Hi-Z)
÷32
÷8
÷4
÷16
÷2
÷1
Output QX at LVPECL VOL, Output nQX at LVPECL VOH
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCCO_LVCMOS + 0.5V
Outputs, VO (LVCMOS)
Outputs, IO (LVPECL)
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
37°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5ꢀ, VCCO_LVCMOS, VCCO_LVPECL = 3.3V 5ꢀ or 2.5V 5ꢀ, VEE = 0V,
TA = -40°C to 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VCC
Units
V
Core Supply Voltage
Analog Supply Voltage
VCCA
VCC – 0.15
3.135
3.3
V
3.3
3.465
2.625
210
V
VCCO_LVCMOS,
VCCO_LVPECL
Output Supply Voltage
2.375
2.5
V
IEE
Power Supply Current
Analog Supply Current
mA
mA
ICCA
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IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5ꢀ, VCCO_LVCMOS = 3.3V 5ꢀ or 2.5V 5ꢀ, VEE = 0V,
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
0.8
Units
VIH
VIL
Input High Voltage
2
V
V
Input Low Voltage
-0.3
QA_SEL[0:1],
QB_SEL[0:1]
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
5
µA
µA
µA
µA
CLK_SEL,
QA_SEL2,
QB_SEL2,
R_SEL[0:2]
IIH
Input High Current
150
QA_SEL[0:1],
QB_SEL[0:1]
V
-150
-5
CLK_SEL,
QA_SEL2,
QB_SEL2,
R_SEL[0:2]
IIL
Input Low Current
VCC = 3.465V, VIN = 0V
V
CCO_LVCMOS = 3.465V,
IOH = 1mA
2.6
1.8
V
V
V
VOH
Output High Voltage
Output Low Voltage
LOR0, LOR1
LOR0, LOR1
VCCO_LVCMOS = 2.625V,
IOH = 1mA
VCCO_LVCMOS = 3.465V or
2.625V, IOL= -1mA
VOL
0.5
Table 4C. Differential DC Characteristics, VCC = 3.3V 5ꢀ, VCCO_LVPECL = 3.3V 5ꢀ or 2.5V 5ꢀ, VEE = 0V,
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CLK0/nCLK0,
CLK1/nCLK1
IIH Input High Current
VCC = VIN = 3.465V
150
µA
CLK0, CLK1
V
CC = 3.465V, VIN = 0V
-5
-150
µA
µA
V
IIL
Input Low Current
nCLK0, nCLK1
VCC = 3.465V, VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC – 0.85
V
NOTE 1: VIL cannot be less than -0.3V
NOTE 2: Common mode input voltage is defined as VIH.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Table 4D. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V 5ꢀ, VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO – 2.0
0.6
Typical
Maximum
VCCO – 0.9
VCCO – 1.7
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. See Parameter Measurement Information section, Output Load Test Circuit
diagram.
Table 4E. LVPECL DC Characteristics, VCC = 3.3V 5ꢀ, VCCO_LVPECL = 2.5V 5ꢀ, VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO – 2.0
0.4
Typical
Maximum
VCCO – 0.9
VCCO – 1.5
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. See Parameter Measurement Information section, Output Load
Test Circuit diagram.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V 5ꢀ, VCCO_LVCMOS = VCCO_LVPECL = 3.3V 5ꢀ or 2.5V 5ꢀ, VEE = 0V,
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
700
Units
MHz
ps
fOUT
Output Frequency
19.44
tsk(o)
Output Skew; NOTE 1, 2
150
RMS Phase Jitter (Random);
NOTE 3
155.52MHz,
Integration Range: 12kHz – 20MHz
tjit(Ø)
0.81
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
100
45
800
55
ps
ꢀ
See Parameter Measurement Information section.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise plots.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Typical Phase Noise at 155.52MHz
Filter
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.81ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
filter to raw data
Offset Frequency (Hz)
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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Parameter Measurement Information
2.8V¬ 0.04
2V
2V
2.8V¬ 0.04
2V
V
SCOPE
CC,
V
CC,
SCOPE
Qx
Qx
V
V
V
CCO_LVCMOS
CCO_LVPECL,
CCO_LVCMOS
V
CCA
V
V
CCO_LVPECLLVPECL
LVPECL
CCA
nQx
nQx
VEE
VEE
-1.3V¬ 0.165
-0.5V¬ 0.125
3.3V Core/3.3V LVPECL Output Load AC Test Circuit
3.3V Core/2.5V LVPECL Output Load AC Test Circuit
V
CC
nQx
Qx
nCLK0, nCLK1
CLK0, CLK1
VPP
VCMR
Cross Points
nQy
Qy
tsk(o)
V
EE
Differential Input Level
Output Skew
Phase Noise Plot
nQA, nQB
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Phase Noise Mask
20ꢀ
QA, QB
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Output Rise/Fall Time
RMS Phase Jitter
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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nQA, nQB
QA, QB
tPW
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
CLKx and nCLKx can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLKx to
ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Outputs
LVCMOS Control Pins
All unused LVCMOS output can be left floating. There should be no
trace attached.
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The
3.3V
ICS843002I-41 provides separate power supplies to isolate any
high switching noise from the outputs to the internal PLL. VCC,
VCCA, VCCO_LVPECL and VCCO_LVCMOS should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that
an additional 10Ω resistor along with a 10μF bypass capacitor be
connected to the VCCA pin.
VCC
.01µF
.01µF
10Ω
VCCA
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
VCC
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
HiPerClockS
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
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700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER ATTENUATOR
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
Z
o = 50Ω
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
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Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to
ground level. The R3 in Figure 6B can be eliminated and the
termination is shown in Figure 6C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
R3
50Ω
250
250
+
–
50Ω
50Ω
+
–
50Ω
2.5V LVPECL Driver
R1
50
R2
50
2.5V LVPECL Driver
R2
62.5
R4
62.5
R3
18
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 6C. 2.5V LVPECL Driver Termination Example
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Schematic Example
Figure 7 shows a schematic example of the ICS843002I-41
application schematic. In this example, the device is operated at
VCC = 3.3V. The decoupling capacitors should be located as close
as possible to the power pin. The input is driven by a 3.3V LVPECL
driver. The 2-pole filter example is used in this schematic. Please
refer to the ICS843002I-41 datasheet for additional loop filter
recommendations.
Figure 7. ICS843002I-41 Schematic Example
Loss of Reference Indicator (LOR0 and LOR1) Output Pins
The LOR0 and LOR1 pins are controlled by the internal clock
activity monitor circuits. The clock activity monitor circuits are
clocked by the VCXO PLL phase detector feedback clock. The
LOR output is asserted high if there are three consecutive
feedback clock edges without any reference clock edges (in both
cases, either a negative or positive transition is counted as an
“edge”). The LOR output will otherwise be low. In a phase detector
observation interval, the activity monitor does not flag excessive
reference transitions as an error. The monitor only distinguishes
between transitions occurring and no transitions occurring.
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VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must
be taken with the package and load capacitance (CL). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with
the package, it is recommended that a metal-canned package like
HC49 be used. Generally, a metal-canned package has a larger
pulling range than a surface mounted device (SMD). For crystal
selection information, refer to the VCXO Crystal Selection
Application Note.
reduced. The correct value of CL is dependant on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and CP values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. For other configurations, refer to the Loop Filter
Component Selection for VCXO Based PLLs Application Note.
The crystal and external loop
LF0
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
LF1
The crystal’s load capacitance CL characteristic determines it
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
ISET
RS RSET
CP CS
XTAL_IN
If the crystal CL is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal (CL) is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
underneath the device, loop
filter or crystal components.
CTUNE
19.44MHz
CTUNE
XTAL_OUT
VCXO Characteristics Table
Symbol
kVCXO
Parameter
Typical
5800
12.6
Units
Hz/V
pF
VCXO Gain
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
24.5
pF
VCXO-PLL Loop Bandwidth Selection Table
Bandwidth
10Hz (Low)
70Hz (Mid)
100Hz (High)
Crystal Frequency (MHz)
RS (kΩ)
CS (µF)
1.0
CP (µF)
0.10
RSET (kΩ)
9.5
19.44
19.44
19.44
5
10
15
1.0
0.01
4.75
1.0
0.01
4.75
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
19.44
fN
fT
fS
MHz
ppm
ppm
0C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
-40
+85
CL
12
4
pF
CO
pF
CO / C1
ESR
220
240
Equivalent Series Resistance
50
1
Ω
Drive Level
Aging @ 25 0C
mW
ppm
3 per year
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843002I-41.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I-41 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.65mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 727.65mW + 60mW = 787.65mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.788W * 37°C/W = 114.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 48 Lead TQFP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
Transistor Count
The transistor count for ICS843002I-41 is: 5536
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Package Outline and Package Dimensions
Package Outline - K Suffix for 32-Lead VFQFN
(Ref.)
Seating Plane
(N -1)x e
N & N
(Ref.)
Even
A1
IndexArea
L
A3
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
E2
OR
(Ref.)
E2
2
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package
dimensions are in Table 8 below.
Table 8. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
0.25
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
8
5.00 Basic
3.0
3.3
0.50 Basic
0.40
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
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Ordering Information
Table 9. Ordering Information
Part/Order Number
843002AKI-41
843002AKI-41T
843002AKI-41LF
843002AKI-41LFT
Marking
Package
32 Lead VFQFN
32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS43002A41
ICS43002A41
ICS002AI41L
ICS002AI41L
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
A
Table
T4B
5
Page
Description of Change
Date
1/22/09
4/7/09
6
7
LVCMOS DC Characteristics Table - added conditions to VOH and VOL
.
B
AC Characteristics Table - changed output skew from 50 to 150
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Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
6024 Silver Creek Valley Road
San Jose, CA 95138
+480-763-2056
United States
www.IDT.com/go/contactIDT
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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