2SK3157 [HITACHI]
Silicon N Channel MOS FET High Speed Power Switching; 硅N沟道MOS FET高速电源开关
| 型号： | 2SK3157 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Silicon N Channel MOS FET High Speed Power Switching |
| 文件： | 总9页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2SK3157
Silicon N Channel MOS FET
High Speed Power Switching
ADE-208-769A (Z)
2nd. Edition
Februaty 1999
Features
•
Low on-resistance
RDS = 50 mΩ typ.
•
•
High speed switching
4 V gate drive device can be driven from 5 V source
Outline
TO–220FM
D
G
1. Gate
2. Drain
3. Source
1
2
3
S
2SK3157
Absolute Maximum Ratings (Ta = 25°C)
Item
Symbol
VDSS
Ratings
Unit
V
Drain to source voltage
Gate to source voltage
Drain current
150
VGSS
ID
±20
V
20
A
Note1
Drain peak current
ID(pulse)
80
A
Body-drain diode reverse drain current IDR
20
A
Note3
Note3
Avalanche current
Avalanche energy
Channel dissipation
Channel temperature
Storage temperature
IAP
20
A
EAR
30
mJ
W
°C
°C
Pch Note2
35
Tch
150
Tstg
–55 to +150
Note: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50 Ω
Electrical Characteristics (Ta = 25°C)
Item
Symbol Min
Typ
—
Max
—
Unit
V
Test Conditions
ID = 10 mA, VGS = 0
IG = ±100 µA, VDS = 0
VGS = ±16 V, VDS = 0
VDS = 150 V, VGS = 0
ID = 1 mA, VDS = 10 V
ID = 10 A, VGS = 10 VNote4
ID = 10 A, VGS = 4 VNote4
ID = 10 A, VDS = 10 V Note4
VDS = 10 V
Drain to source breakdown voltage V(BR)DSS 150
Gate to source breakdown voltage V(BR)GSS ±20
—
—
V
Gate to source leak current
Zero gate voltege drain current
Gate to source cutoff voltage
Static drain to source on state
resistance
IGSS
—
—
1.0
—
—
13
—
—
—
—
—
—
—
—
—
—
±10
10
2.5
70
80
—
µA
µA
V
IDSS
—
VGS(off)
RDS(on)
RDS(on)
|yfs|
—
50
mΩ
mΩ
S
60
Forward transfer admittance
Input capacitance
22
Ciss
Coss
Crss
td(on)
tr
1750
600
300
18
—
pF
pF
pF
ns
ns
ns
ns
V
Output capacitance
Reverse transfer capacitance
Turn-on delay time
—
VGS = 0
—
f = 1 MHz
—
ID = 10 A, VGS = 10 V
RL = 3 Ω
Rise time
125
400
190
0.9
170
—
Turn-off delay time
td(off)
tf
—
Fall time
—
Body–drain diode forward voltage VDF
—
IF = 20 A, VGS = 0
Body–drain diode reverse
recovery time
trr
—
ns
IF = 20 A, VGS = 0
diF/ dt = 50 A/ µs
Note: 4. Pulse test
2
2SK3157
Main Characteristics
Power vs. Temperature Derating
Maximum Safe Operation Area
500
40
30
20
10
200
100
50
20
10
5
2
1
Operation in
this area is
limited by R
0.5
DS(on)
0.2
0.1
Ta = 25°C
0.05
1000
100 300
0
10 30
0.1
1
3
50
100
150
200
0.3
Drain to Source Voltage
V
(V)
DS
Case Temperature Tc (°C)
Typical Output Characteristics
10 V
20
Typical Transfer Characteristics
= 10 V
20
16
12
8
Pulse Test
3 V
5 V
4 V
V
DS
Pulse Test
16
12
8
75°C
25°C
V
GS
= 2.5 V
Tc = –25°C
4
4
2 V
8
0
0
1
2
3
4
GS
5
2
4
6
10
Gate to Source Voltage
V
(V)
Drain to Source Voltage
V
(V)
DS
3
2SK3157
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Static Drain to Source on State Resistance
vs. Drain Current
1000
2.0
1.6
1.2
0.8
0.4
Pulse Test
Pulse Test
500
200
100
50
I
= 20 A
D
V
= 4 V
GS
10 V
10 A
5 A
20
10
100
10
Drain Current
20
50
12
Gate to Source Voltage
5
0
2
4
8
16
20
1
V
(V)
I
(A)
GS
D
Forward Transfer Admittance vs.
Drain Current
Static Drain to Source on State Resistance
vs. Temperature
100
30
250
Pulse Test
Tc = –25 °C
200
150
100
50
10
75 °C
25 °C
5, 10 A
I
= 20 A
D
3
1
V
= 4 V
GS
5, 10 A
20 A
0.3
0.1
V
= 10 V
DS
Pulse Test
10 V
0
0
–40
10 50 100
5
20
2
0.1
0.5
1
0.2
40
80
120
160
Case Temperature Tc (°C)
Drain Current I
(A)
D
4
2SK3157
Body–Drain Diode Reverse
Recovery Time
Typical Capacitance vs.
Drain to Source Voltage
1000
500
10000
di / dt = 50 A / µs
V
= 0, Ta = 25 °C
GS
3000
1000
Ciss
200
100
50
300
100
Coss
Crss
30
10
20
10
V
= 0
GS
f = 1 MHz
0.1 0.3
1
3
10
30
(A)
100
0
10
20
30
40
50
Reverse Drain Current
I
DR
Drain to Source Voltage
V
(V)
DS
Dynamic Input Characteristics
= 20A
Switching Characteristics
5000
200
160
120
80
20
I
D
V
= 10 V, V
= 30 V
DD
GS
PW = 5 µs, duty < 1 %
2000
1000
500
V
GS
16
12
8
V
= 100 V
50 V
DD
t
d(off)
25 V
t
f
200
100
V
DS
t
r
50
V
= 100 V
50 V
40
4
0
DD
t
d(on)
2
20
10
25 V
0
5
I
10 20
(A)
1
50
0.5
40
80
120
160
200
0.2
0.1
Gate Charge Qg (nc)
Drain Current
D
5
2SK3157
Maximun Avalanche Energy vs.
Channel Temperature Derating
Reverse Drain Current vs.
Source to Drain Voltage
20
16
12
8
50
40
30
20
Pulse Test
I
= 20 A
AP
V
= 50 V
DD
duty < 0.1 %
Ω
Rg > 50
V
= 10 V
GS
5 V
0, –5 V
4
10
0
0
0.2
0.4
0.6
0.8
SD
1.0
(V)
25
50
75
100
125
150
Source to Drain Voltage
V
Channel Temperature Tch (°C)
Avalanche Test Circuit
Avalanche Waveform
V
DSS
1
2
2
E
=
• L • I
•
AP
AR
V
– V
DD
DSS
L
V
DS
Monitor
I
AP
V
(BR)DSS
Monitor
I
AP
Rg
V
V
DD
D. U. T
DS
I
D
Vin
15 V
50Ω
V
DD
0
6
2SK3157
Normalized Transient Thermal Impedance vs. Pulse Width
3
1
Tc = 25°C
D = 1
0.5
0.3
0.1
θ
θ
γ
θ
ch – c(t) = s (t) • ch – c
ch – c = 3.57°C/W, Tc = 25°C
PW
T
P
DM
D =
0.03
0.01
PW
T
10 µ
100 µ
1 m
10 m
100 m
1
10
Pulse Width PW (S)
Switching Time Test Circuit
Waveform
Vout
Monitor
Vin Monitor
D.U.T.
90%
R
L
10%
10%
90%
Vin
V
DD
Vin
10 V
Vout
10%
50Ω
= 30 V
90%
td(off)
td(on)
t
f
tr
7
2SK3157
Package Dimensions
Unit: mm
2.8 ± 0.2
2.5 ± 0.2
10.0 ± 0.3
7.0 ± 0.3
φ
3.2 ± 0.2
1.2 ± 0.2
1.4 ± 0.2
4.45 ± 0.3
2.7
0.7 ± 0.1
2.54 ± 0.5
2.54 ± 0.5
0.5 ± 0.1
TO–220FM
SC–67
—
Hitachi Code
EIAJ
JEDEC
8
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
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failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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