MB89P665_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12519-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89660 Series

MB89663/665/P665/W665

■ DESCRIPTION

The MB89660 series has been developed as a general-purpose version of the F²MC*-8L family consisting of

proprietary 8-bit single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as

timers, a UART, a serial interface, an 8-bit A/D converter, an input capture, an output compare, and an external

interrupt. The MB89660 series is applicable to a wide range of applications from welfare products to industrial

equipment.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Package expansion

QFP package

SDIP package

(Continued)

■ PACKAGE

64-pin Ceramic SH-DIP

64-pin Plastic QFP

64-pin Plastic SH-DIP

(DIP-64C-A06)

(FPT-64P-M06)

(DIP-64P-M01)

MB89660 Series

(Continued)

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

• Three types of timers

8-bit PWM timer

8/16-bit timer/counter

20-bit time-base timer

• Functions that permit communications with a variety of devices

UART which permits selection of synchronous/asynchronous communications

A serial interface that permits selection of the transfer direction

• 8-bit A/D converter: 8 channels

Sense mode function capable of performing compare operation in 5 µs

Activation by external input possible

• Real-time control

Input capture: 2 channels

Output compare: 2 channels

• External interrupt: 4 channels

Two channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

Hardware standby mode (Wake-up from this mode and activation by pin input only.)

2

MB89660 Series

■ PRODUCT LINEUP

Part number

MB89665

MB89W665

MB89P665

MB89663

Parameter

Classification

Mass production products

(mask ROM products)

One-time PROM product,

also used for evaluation

EPROM product

ROM size

8 K × 8 bits 16 K × 8 bits

(internal mask ROM) (internal mask ROM) (internal PROM,

16 K × 8 bits

(internal PROM,

programming with

general-purpose

programming with

general-purpose

EPROM programmer) EPROM programmer)

RAM size

256 × 8 bits

Number of instructions:

512 × 8 bits

CPU functions

136

Instruction bit length:

Instruction length:

Data bit length:

Minimum execution time:

Interrupt processing time:

8 bits

1 to 3 bytes

1,8, 16 bits

0.4 µs/10 MHz

3.6 µs/10 MHz

Ports

Output ports (CMOS):

Output ports (N-ch open-drain):

I/O ports (CMOS):

Total:

8

8 (All also serve as peripherals.)

36 (19 ports also serve as peripherals.)

52

8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs, 6.4 µs, 25.6 µs)

8-bit resolution PWM operation (conversion cycle: 102 µs, 1.6 ms, 6.6 ms)

8-bit PWM timer

8/16-bit timer/

counter

Independent 8-bit reload timer/counter operation: 2 channels

Single 16-bit event counter (cascade connection): 1 channel

One clock selectable from four transfer clocks

(one external shift clock, three internal clocks: 0.8 µs, 3.2 µs, 12.8 µs)

UART

8 bits

Full-duplex double buffer

Synchronous and asynchronous data transfer

8-bit serial I/O

8 bits

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

8-bit A/D

converter

8-bit resolution × 8 channels

A/D conversion mode (conversion time: 18 µs at 10 MHz)

Sense mode (conversion time: 5 µs at 10 MHz)

Continuous activation by an external activation or an internal timer capable

Reference voltage input

Real-time I/O

16-bit timer: operating clock cycle (0.4 µs, 0.8 µs, 1.6 µs, 3.2 µs)

overflow interrupt

Input capture: 16 bits × 2 channels (External trigger edge selectability)

Output compare: 16 bits × 2 channels

(Continued)

3

MB89660 Series

(Continued)

Part number

MB89665

MB89W665

MB89P665

MB89663

Parameter

External interrupt

4 channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge/both edges selectability

Used also for wake-up from stop/sleep mode.

(Edge detection is also permitted in stop mode.)

(Wake-up from hardware standby mode is not possible)

Standby mode

Process

Sleep mode, stop mode, and hardware standby mode

CMOS

Operating voltage*

2.2 V to 6.0 V

2.7 V to 6.0 V

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89663

Package

MB89665

MB89W665

MB89P665

DIP-64P-M01

×

DIP-64C-A06

FPT-64P-M06

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

4

MB89660 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTPROM (one-time PROM) product (also used for evaluation), verify its differences

from the product that will actually be used: Take particular care on the following points:

• On the MB89663, register bank from 16 to 32 cannot be used.

• On the MB89P665, address BFF0^Hto BFF6H comprise the option setting area, option settings can be read by

reading these addresses.

• The stack area, etc., is used.

2. Current Consumption

• When operated at low speed, the product with an OTPROM or an EPROM will consume more current than

the product with a mask ROM.

• However, the current comsumption in sleep/stop modes is the same. (For more information, see sections

“■ Electrical Characteristics” and “■ Example Characteristics.”

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

Take particular care on the following points:

• On the MB89P665, a pull-up resistor must be selected in a group of four pins for P54 to P57.

• For all products, P50 to P57 must be set to without a pull-up resistor when an A/D converter is used.

5

MB89660 Series

■ PIN ASSIGNMENT

(Top view)

1

VCC

P36/RTO1

P37/ADST

P40/SCK1

P41/SO1

P42/SI1

P43/SCK2

P44/SO2

P45/SI2

P46/PTO

P47

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

P35/RTO0

P34/RTI1

P33/RTI0

P32/TO2

P31/TO1

P30/EC

V^SS

3

4

5

6

7

8

9

P00

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

AVR

AVSS

P60/INT0

P61/INT1

P62/INT2

P63/INT3

HST

P14

P15

P16

P17

P20

P21

P22

RST

P23

MOD0

P24

MOD1

P25

X0

P26

X1

P27

V^SS

(DIP-64P-M01)

(DIP-64C-A06)

(Top view)

P45/SI2

P46/PTO

P47

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P30/EC

V^SS

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

AVR

AVSS

P60/INT0

P61/INT1

P62/INT2

P63/INT3

HST

(FPT-64P-M06)

6

MB89660 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

X0

Function

DIP^*1

30

QFP^*2

23

A

Crystal oscillator pins

31

24

X1

28

21

MOD0

MOD1

B

Operating mode selection pins

Connect directly to V^CCor VSS.

A pull-down resistor is selectable as an option for mask

ROM products.

29

22

27

26

20

19

RST

C

Reset I/O pin

This port is an N-ch open-drain output type with pull-up

resistor and a hysteresis input type. “L” is output from this

pin by an internal reset source. The internal circuit is

initialized by the input of “L”.

HST

G

D

Hardware standby input pin

Connect directly to V^CCwhen hardware standby is not

used.

56 to 49

48 to 41

40 to 33

58

49 to 42

41 to 34

33 to 26

51

P00 to P07

P10 to P17

P20 to P27

P30/EC

General-purpose I/O ports

F

E

General-purpose output ports

General-purpose I/O port

Also serves as an external clock input for an 8/16-bit

timer/counter.

This pin is a hysteresis input type and with a noise

canceller.

59

60

52

53

P31/TO1

P32/TO2

E

General-purpose high-current I/O port

Also serves as an 8/16-bit timer/counter output. This pin

is a hysteresis input type and with a noise canceller.

General-purpose I/O port

Also serves as an 8/16-bit timer/counter output. This pin

is a hysteresis input type and with a noise canceller.

61

62

54

55

P33/RTI0

P34/RTI1

General-purpose I/O ports

Also serve as the data input for the input capture. This pin

is a hysteresis input type and with a noise canceller.

63

1

56

58

P35/RTO0

P36/RTO1

General-purpose I/O ports

Also serve as the data output for the output compare. This

pin is a hysteresis input type and with a noise canceller.

2

59

P37/ADST

General-purpose heavy-current I/O port

Also serves as the external activation input for the A/D

converter. This pin is a hysteresis input type and with a

noise canceller.

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-64P-M06

(Continued)

7

MB89660 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

General-purpose I/O port

Also serves as the clock I/O for the UART. This pin is a

hysteresis input type and with a noise canceller.

DIP^*1

QFP^*2

3

60

P40/SCK1

E

4

5

6

61

62

63

P41/SO1

P42/SI1

General-purpose I/O port

Also serves as the data output for the UART. This pin is a

hysteresis input type and with a noise canceller.

General-purpose I/O port

Also serves as the data input for the UART. This pin is a

hysteresis input type and with a noise canceller.

P43/SCK2

General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O

interface. This pin is a hysteresis input type and with a

noise canceller.

7

8

64

1

P44/SO2

P45/SI2

P46/PTO

P47

E

General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O

interface. This pin is a hysteresis input type and with a

noise canceller.

General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O

interface. This pin is a hysteresis input type and with a

noise canceller.

9

2

General-purpose I/O port

Also serves as a toggle output for an 8-bit PWM timer.

This pin is a hysteresis input type and with a noise

canceller.

10

3

General-purpose I/O port

This pin is a hysteresis input type and with a noise

canceller.

11 to 18

22 to 25

4 to 11

P50/AN0 to

P57/AN7

H

E

N-ch open-drain output-only ports

Also serve as the analog input for the A/D converter.

15 to 18

P60/INT0 to

P63/INT3

General-purpose I/O ports

These pins also serve as an external interrupt input.

These pins are a hysteresis input type and with a noise

canceller.

64

57

V^CC

—

Power supply pin

32

57

25

50

VSS

Power supply (GND) pins

19

20

21

12

13

14

AVCC

AVR

AV^SS

—

A/D converter power supply pin

A/D converter reference voltage input pin

A/D converter power supply pin

Use this pin at the same voltage as VSS.

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-64P-M06

8

MB89660 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• External clock input selection versions of crystal or

ceramic oscillation type

X1

• At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

X0

Standby control signal

B

C

• CMOS input

• Built-in pull-down resistor (mask ROM products only)

• At an output pull-up resistor (P-ch) of approximately

R

50 kΩ/5.0 V

P-ch

• Hysteresis input

N-ch

D

• CMOS output

• CMOS input

• Pull-up resistor optional

R

P-ch

N-ch

E

• CMOS output

• Hysteresis input

• Pull-up resistor optional

R

P-ch

N-ch

F

• CMOS output

P-ch

N-ch

(Continued)

9

MB89660 Series

(Continued)

Type

Circuit

Remarks

G

• Hysteresis input

H

• N-ch open-drain output

• Analog input

R

• Pull-up resistor optional

P-ch

N-ch

Analog input

10

MB89660 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- or high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “ ■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D Converters

Connect to be AVCC = VCC and AVSS = AVR = VSS if the A/D converters are not in use.

4. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency(50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

5. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

11

MB89660 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P665

The MB89P665 is an OTPROM version of the MB89660 series.

1. Features

• 16-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

I/O

EPROM mode

(Corresponding addresses on the EPROM programmer)

0080H

0280H

RAM

Not available

0000H

Vacancy

(Read value FF^H)

BFF0H

BFF7H

C000H

3FF0H

Option area

Not available

Not availble

3FF7H

Vacancy

(Read value FF^H)

4000H

PROM

16 KB

EPROM

16 KB

FFFFH

7FFFH

12

MB89660 Series

3. Programming to the PROM

In EPROM mode, the MB89P665A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000^Hto 7FFFH (note that addresses C000H to FFFFH

while operating as a single chip assign to 4000H to 7FFFH in EPROM mode).

Load option data into addresses 3FF0^Hto 3FF6H of the EPROM programmer. (For information about each

corresponding option, see “8. Setting OTPROM Options.”)

(3) Program with the EPROM programmer.

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

13

MB89660 Series

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. Erasure Procedure

In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an

ultraviolet light source. A dosage of 10 W-seconds/cm²is required to completely erase an internal EPROM. This

dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity

of 12000 µW/cm²for 15 to 21 minuites. The internal EPROM should be about one inch from the source and all

filters should be removed from the UV light source prior to erasure.

It is important to note that the internal EPROM and similar devices, will erase with light sources having wave-

lengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,

nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and

exposure to them should be prevented to realize maximum system reliability. If used in such an environment,

the package windows should be covered by an opaque label or substance.

7. EPROM Programmer Socket Adapter

Package

FPT-64P-M06

DIP-64P-M01

Compatible socket adapter

ROM-64QF-28DP-8L

ROM-64SD-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

Note: Connect the adapter jumper pin to VSS when using.

14

MB89660 Series

8. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vacancy

Reset pin Power-on

Oscillation

stabilization

time

1: Crystal

0: Ceramic

output

reset

Readableand Readableand Readableand

writable

Readableand Readable and

writable

3FF0H

writable

1: Yes

0: No

1: Yes

0: No

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

1: Yes

Pull-up

1: No

1: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

3FF1H

3FF2H

3FF3H

3FF4H

3FF5H

3FF6H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P47

P46

P45

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P57 to P54 P53

Pull-up

1: No

P52

P51

P50

Vacancy

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readableand Readableand Readableand

writable

0: Yes

Vacancy

P63

P62

P61

P60

Vacancy

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable

and

writable

Readableand Readableand Readableand

writable writable writable

Note: • Set each bit to erase.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

15

MB89660 Series

■ BLOCK DIAGRAM

X0

X1

Oscillator

21-bit time-base timer

8-bit PWM timer

P47

P46/PTO

Clock controller

Reset circuit

(WDT)

P45/SI2

RST

HST

8-bit serial I/O

UART

P44/SO2

P43/SCK2

Hardware standby

CMOS I/O port

P42/SI1

P41/SO1

P40/SCK1

8

P00 to P07

P10 to P17

CMOS I/O port

P37/ADST

P36/RTO1

P35/RTO0

Output compare

16-bit timer

8

P20 to P27

P34/RTI1

P33/RTI0

Input capture

Real-time I/O

CMOS output port

P32/TO2

8/16-bit

timer/counter

P31/TO1

P30/EC

RAM

N-ch open-drain output port

F²MC-8L

CPU

8

4

P50/AN0

8-bit A/D converter

to P57/AN7

ROM

AVR

AV^CC

AVSS

4

P60/INT0

to P63/INT3

External interrupt

Other pins

VCC, VSS × 2

CMOS I/O port

MOD0, MOD1

16

MB89660 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89660 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89660 series is structured as illustrated below.

Memory Space

MB89663

I/O

MB89665

MB89W665

MB89P665

0000H

0080H

0000H

0080H

0100H

I/O

RAM

256 B

RAM

512 B

0100H

0180H

Register

0200H

0280^H

Not available

C000H

ROM*

16 KB

E000H

FFFFH

ROM

8 KB

FFFFH

*: When the MB89P665 is used for evaluation, the internal ROM cannot be used.

17

MB89660 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bits

PC

A

: Program counter

: Accumulator

FFFD^H

Undefined

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

Vacancy

PS

RP

Vacancy

H

IL1, 0

N

V

C

RP

CCR

18

MB89660 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

19

MB89660 Series

The following general-purpose registers are provided:

General-purpose registers: an 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 16 banks can be used on the MB89663 and a total of 32 banks can be used on

the MB89665/P665/W665. The bank currently in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

Register Bank Configuration

This address = 0100H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

R7

32 banks

Memory area

20

MB89660 Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

(R/W)

(W)

PDR1

DDR1

Port 1 data direction register

Port 2 data register

(R/W)

PDR2

Vacancy

(R/W)

STBC

WDTC

TBTC

Standby control register

Watchdog timer control register

Watch interrupt control register

Vacancy

(R/W)

(W)

PDR3

DDR3

PDR4

DDR4

PDR5

Port 3 data register

Port 3 data direction register

Port 4 data register

(R/W)

(W)

Port 4 data direction register

Port 5 data register

(R/W)

Vacancy

(R/W)

(W)

PDR6

DDR6

Port 6 data register

Port 6 data direction register

Vacancy

(R/W)

(W)

ADC1

ADC2

ADCD

T2CR

T1CR

T2DR

T1DR

CNTR

COMR

A/D converter control register 1

A/D converter control register 2

A/D converter data register

8/16-bit timer 2 control register

8/16-bit timer 1 control register

8/16-bit timer 2 data register

8/16-bit timer 1 data register

PWM control register

PWM compare register

Vacancy

(Continued)

21

MB89660 Series

(Continued)

Address

20H

21H

22^H

23^H

24H

25^H

26^H

27H

28^H

29H

2A^H

2BH

2CH

2D^H

2EH

2FH

30^H

31H

32^H

33H

34H

35^H

36H

37H

38^H

7C^H

7DH

7EH

7F^H

Read/write

(R/W)

(R)

Register name

SMC

Register description

UART serial mode control register

UART serial rate control register

UART serial status/data register

UART serial data register

Serial mode register

SRC

SSD

SIDR/SODR

SMR

SDR

Serial data register

EIC1

External interrupt control register 1

External interrupt control register 2

Timer control register

EIC2

TMCR

TCHR

TCLR

Timer count register (H)

Timer count register (L)

(R)

(R/W)

(R)

OPCR

CPR0H

CPR0L

CPR1H

CPR1L

ICCR

Output control register

Output compare register 0 (H)

Output compare register 0 (L)

Output compare register 1 (H)

Output compare register 1 (L)

Input capture control register

Input capture interrupt control register

Input capture register 0 (H)

Input capture register 0 (L)

Input capture register 1 (H)

Input capture register 1 (L)

Vacancy

ICIC

ICR0H

ICR0L

ICR1H

ICR1L

(R)

Vacancy

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

Note: Do not use vacancies.

22

MB89660 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

V^CC

AVCC

VSS – 0.3

VSS + 7.0

V

*

Power supply voltage

AVR must not exceed AVCC + 0.3 V

AVR

VI

V^SS– 0.3

VSS – 0.3

VSS + 7.0

VCC + 0.3

V

Input voltage

Output voltage

V^O

“L” level maximum output

current

I^OL

—

20

4

mA

“L” level average output

current

Average value (operating

current × operating rate)

I^OLAV

ΣI^OL

ΣI^OLAV

I^OH

“L” level total maximum output

current

100

40

“L” level total average output

current

Average value (operating

current × operating rate)

“H” level maximum output

current

–20

–4

“H” level average output

current

Average value (operating

current × operating rate)

I^OHAV

ΣIOH

ΣI^OHAV

“H” level total maximum output

current

–50

–20

“H” level total average output

current

Average value (operating

current × operating rate)

Power consumption

Operating temperature

Storage temperature

P^D

—

300

+85

mW

°C

TA

–40

–55

Tstg

+150

°C

* : Use AV^CCand VCC set at the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

23

MB89660 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

Normal operation assurance

range*

2.2*

6.0*

V

MB89663/665

V^CC

AVCC

Normal operation assurance

range*

MB89P665

2.7*

1.5

6.0*

6.0

V

Power supply voltage

Operating temperature

Retains the RAM state in stop

mode

AVR

T^A

0.0

AV^CC

+85

V

–40

°C

* : These values vary with the operating frequency and analog assurance range. See Figure. 1 and “5. A/D Converter

Electrical Characteristics.”

6

5

Analog accuracy assured in the

AV^CC= VCC = 3.5 to 6.0 V range

Operation assurance range

4

3

2

1

2

3

4

5

6

7

8

9

10

Main clock operating frequency (MHz)

Note: The shaded area is assured only for the MB89663/665.

Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MHz)

24

MB89660 Series

3. DC characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17

V^IH

—

0.7 V^CC

—

VCC + 0.3

V

“H” level input

voltage

RST, HST

P30 to P37,

P40 to P47,

P60 to P63

V^IHS

VIL

—

0.8 V^CC

V^SS– 0.3

—

VCC + 0.3

0.3 VCC

0.2 VCC

V

P00 to P07,

P10 to P17

“L” level input

voltage^*1

RST, HST

P30 to P37,

P40 to P47,

P60 to P63

V^ILS

Open-drain

output pin

application

voltage

V^D

P50 to P57

—

VSS – 0.3

—

VCC + 0.3

V

P00 to P07,

P10 to P17,

P20 to P27,

P30,

P32 to P36,

P40 to P47,

P60 to P63

IOH = –2.0 mA

IOH = –15 mA

2.4

—

V

V^OH1

“H” level output

voltage

V^OH2

P31, P37

P00 to P07,

P10 to P17,

P20 to P27,

P30,

P32 to P36,

P40 to P47,

P50 to P57,

P60 to P63

IOL = +1.8 mA

V^OL1

—

0.4

V

“L” level output

voltage

IOL = +12 mA

IOL = +4.0 mA

V^OL2

P31, P37

RST

—

0.4

V

VOL3

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P60 to P63

Input leakage

current (Hi-z

output leakage

current)

0.45 V

Withoutpull-up

resistor

ILI1

—

±5

µA

kΩ

< VI < VCC

RST,

Pull-up

resistance

option

R^PULU

VI = 0.0 V

25

50

100

selection pin

(Continued)

25

MB89660 Series

(Continued)

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Pull-down

Condition

Unit

Remarks

Min.

Typ.

Max.

Mask ROM

products only

R^PULD

MOD0, MOD1 VI = +5.0 mA

5

20

60

kΩ

resistance

MB89663/665

—

15

17

18

20

mA

FC = 10 MHz

t^inst*3= 0.4 µs

Normal mode

I^CC

MB89P665/

W665

FC = 10 MHz

ICCS

t^inst*3= 0.4 µs

—

6

8

mA

VCC

Sleep mode

Also

TA = +25°C

t^inst*3= 0.4 µs

Stop mode

applicable to

the hardware

standby mode.

I^CCH

—

10

µA

Power supply

current

FC = 10 MHz,

when A/D

conversion is

activated

IA

—

2.5

4.5

mA

AVCC

FC = 10 MHz,

TA = +25°C,

when A/D

conversion is

stopped

I^AH

—

5

µA

Other than

AVCC, AVSS, VCC,

and VSS

Input

capacitance

C^IN

f = 1 MHz

10

—

pF

*1: Fix MOD0 and MOD1 to V^SS.

*2: The power supply current is measured at the external clock.

*3: For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

26

MB89660 Series

4. AC Characteristics

(1) Reset Timing, Hardware Standby Timing

(V^CC= +5.0 V±10%, AVSS =VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Max.

—

RST “L” pulse width

HST “L” pulse width

tZLZH

tHLHH

16 t^XCYL

16 tXCYL

ns

—

* : t^XCYLis the oscillation cycle (1/FC) to input to the X0 pin.

tZLZH

RST

HST

0.2 VCC

tHLHH

0.2 VCC

(2) Power-on Reset

Parameter

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Values

Symbol

Condition

Unit

Remarks

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

—

50

ms

—

Due to repeated

operations

t^OFF

1

—

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tOFF

t^R

2.0 V

0.2 V

VCC

0.2 V

27

MB89660 Series

(3) Clock Timing

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

1

Typ.

—

Max.

10

Clock frequency

Clock cycle time

F^C

X0, X1

—

MHz

ns

t^XCYL

100

—

1000

Input clock pulse

width

P^WH

PWL

External clock

X0

—

20

—

ns

Input clock rising/

falling time

tCR

tCF

10

X0 and X1 Timing and Conditions

tXCYL

PWL

PWH

tCF

tCR

0.8 VCC

X0

0.2 VCC

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

When operating at FC = 10 MHz

Instruction cycle

(minimum execution

time)

t^inst

4/FC

µs

28

MB89660 Series

(5) Recommended Resonator Manufacturers

Sample Application of Piezoelectric Resonator (FAR series)

X0

X1

FAR*

C1

C2

*: Fujitsu Acoustic Resonator

C1 = C2 = 20 pF±8 pF (built-in FAR)

Initial deviation of

FAR frequency

(T^A= +25°C)

Temperature characteristic of

FAR frequency

FAR part number

(built-in capacitor type)

Frequency

(T^A= –20°C to +60°C)

FAR-C4CB-08000-M02

FAR-C4CB-10000-M02

8.00 MHz

±0.5%

10.00 MHz

Inquiry: FUJITSU LIMITED

29

MB89660 Series

Sample Application of Ceramic Resonator

X0

X1

*

C1

C2

Resonator manufacturer*

Kyocera Corporation

Resonator

Frequency

7.68 MHz

8.0 MHz

C1 (pF)

33

C2 (pF)

33

R (kΩ)

—

KBR-7.68MWS

KBR-8.0MWS

CSA8.00MTZ

33

—

Murata Mfg. Co., Ltd.

8.0 MHz

30

—

Inquiry: Kyocera Corporation

• AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters: TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

30

MB89660 Series

(6) Serial I/O Timing and UART Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

SCK1,

Condition

Unit

Remarks

Min.

Max.

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

tSHIX

2 t^inst*

—

µs

ns

µs

ns

µs

SCK2

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

SCK1, SO1

SCK2, SO2

–200

1/2 t^inst*

1 t^inst*

0

200

—

Internal

shift clock

mode

Valid SI1 → SCK1 ↑

SI1, SCK1

SI2, SCK2

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

—

SCK1,

SCK2

Serial clock “H” pulse width tSHSL

Serial clock “L” pulse width t^SLSH

—

SCK1,

SCK2

—

External

shift clock

mode

SCK1 ↓ → SO1 time

tSLOV

SCK1, SO1

SCK2, SO2

200

—

SCK2 ↓ → SO2 time

Valid SI1 → SCK1 ↑

t^IVSH

SI1, SCK1

SI2, SCK2

1/2 t^inst*

Valid SI2 → SCK2 ↑

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

tSHIX

—

SCK2 ↑ → valid SI2 hold time

* : For information on t^inst, see “(4) Instruction Cycle.”

31

MB89660 Series

Serial I/O Timing and UART Timing (Internal Shift Clock Mode)

t^SCYC

2.4 V

SCK1

SCK2

0.8 V

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

Serial I/O Timing and UART Timing (External Shift Clock Mode)

tSLSH

tSHSL

0.8 VCC

SCK1

SCK2

0.2 VCC

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

32

MB89660 Series

(7) Peripheral Input Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

Peripheral input “H” pulse

width 1

t^ILIH1

t^IHIL1

t^ILIH2

t^IHIL2

t^ILIH3

t^IHIL3

t^ILIH3

tIHIL3

—

µs

RTI0, 1

INT0 to INT3

2 t^inst*

Peripheral input “L” pulse

width 1

—

Peripheral input “H” pulse

width 2

EC

1 tinst*

32 tinst*

8 tinst*

Peripheral input “L” pulse

width 2

Peripheral input “H” pulse

width 3

A/D mode

Peripheral input “L” pulse

width 3

ADST

Peripheral input “H” pulse

width 3

Sense mode

Peripheral input “L” pulse

width 3

* : For information on t^inst, see “(4) Instruction cycle.”

tIHIL1

tILIH1

0.8 VCC

0.2 VCC

INT0 to 3

RTI0, 1

0.2 VCC

tIHIL2

tILIH2

0.8 VCC

0.2 VCC

EC

0.2 VCC

tIHIL3

tILIH3

0.8 VCC

0.2 VCC

ADST

0.2 VCC

33

MB89660 Series

(8) Noise Filter

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

P30 to P37,

P40 to P47,

P60 to P63

During port

operation

Noise filter width 1

Noise filter width 2

t^INF1

15

—

ns

During external

interrupt

t^INF2

P60 to P63

60

—

tINF 1,

2

tINF 1,

2

0.8 VCC

0.2 VCC

Input waveform

34

MB89660 Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Resolution

Symbol

Condition

Unit Remarks

Min.

—

Typ.

—

Max.

8

—

bit

Total error

—

±2.0

LSB

—

Linearity error

—

±1.0

±0.9

Differential linearity error

—

AV^SS–

AV^SS+

AVR = AV^CC

Zero transition voltage

V^OT

mV

1.5 LSB 0.5 LSB 2.5 LSB

—

Full-scale transition

voltage

AVR –

AVR +

V^FST

3.5 LSB 1.5 LSB 0.5 LSB

Interchannel disparity

—

1

LSB

A/D mode conversion time

44 t^isnt*

—

µs

—

Sense mode conversion

time

—

12 t^inst*

—

µs

—

Analog port input circuit

Analog input voltage

Reference voltage

I^AIN

—

0

—

10

µA

V

AN0 to AN7

AVR

AV^CC

0

V

AVR = 5.0 V

when A/D

conversion is

activated

I^R

—

150

—

5

µA

AVR

Reference voltage

supply current

AVR = 5.0 V

when A/D

conversion is

stopped

I^RH

* : For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter.

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

35

MB89660 Series

Digital output

1111 1111

1111 1110

Theoretical conversion value

Actual conversion value

(1 LSB × N + V^OT)

AVR

256

1 LSB =

VNT − (1 LSB × N + VOT)

Linearity error =

1 LSB

V( N + 1 ) T − VNT

Differential linearity error =

− 1

1 LSB

Linearity error

VNT − (1 LSB × N + 1 LSB)

Total error =

1 LSB

0000 0010

0000 0001

0000 0000

VOT

VNT

V( N+I )T

VFST

Analog input

(2) Precautions

• Input impedance of analog input pins

The A/D converter used for the MB89660 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low. If a higher accurancy is required, set the output impedance in this series

to 2 kΩ or less.

When the impedance cannot be kept low, the following two methods are recommended. One is to activate the

A/D converter continuously for obtaining the pseudo long sampling time by using software. The other is to

connect the external capacitor of approx. 0.1 µs to the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

.

=

C

33 pF

.

Analog input pin

Comparator

.

=

R

6 kΩ

.

If the output impedance of

the external circuit is high, it

is recommended to connect

an external capacitor of

approx. 0.1 µF.

Closes for 8 instruction cycles

after activating A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

36

MB89660 Series

■ EXAMPLES CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

P00 to P07, P10 to P17,P20 to P27, P30, P32 to

P36, P40 to P47, P50 to P57, P60 to P63

P00 to P07, P10 to P17, P20 to P27, P30, P32

to P36, P40 to P47, P60 to P63

VOL vs. IOL

VCC - VOH VS. IOH

V^DD- VOH(V)

V^OL(V)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 2.5 V

TA = +25°C

V^CC= 2.5 V

0.5

V^CC= 3.0 V

0.4

V^CC= 3.0 V

V^CC= 4.0 V

VCC = 5.0 V

V^CC= 6.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0.3

0.2

0.1

0.0

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

I^OH(mA)

(4) “H” Level Output Voltage

P31, P37

(3) “L” Level Output Voltage

P31, P37

VCC - VOH2 vs. IOH2

V^DD- VOH2(V)

VOL2 vs. IOL2

V^OL2(V)

3.0

2.0

1.0

0

TA = +25°C

VCC = 3.0 V

0.6

0.4

0.2

0

TA = +25°C

VCC = 3.0 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

VCC = 5.0 V

VCC = 6.0 V

0

–5

–10

–15

–20

I^OH2(mA)

0

–5

–10

–15

–20

I^OL2(mA)

37

MB89660 Series

(5) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(6) “H” Level Input Voltage/“L” Level

Input Voltage (Hysteresis Input)

V^IN(V)

5.0

VIN vs. VCC

TA = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V^IN(V)

5.0

VIN vs. VCC

TA = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V^IHS

VILS

0.0

0

1

2

3

4

5

6

7

VCC(V)

0.0

0

Threshold when input voltage in hysteresis

characteristics is set to “H” level

Threshold when input voltage in hysteresis

V^IHS:

V^ILS:

1

2

3

4

5

6

7

V^CC(V)

characteristics is set to “L” level

(7) Power Supply Current (External Clock)

I^CCS(mA)

I^CC(mA)

16

ICCS vs. VCC

TA = +25°C

ICC vs. VCC

5

4

3

2

1

0

TA = +25°C

14

12

10

8

FC = 10 MHz

FC = 8 MHz

FC = 4 MHz

FC = 1 MHz

6

FC = 4 MHz

FC = 1 MHz

4

2

0

1

2

3

4

5

6

1

2

3

4

5

6

7

VCC(v)

38

MB89660 Series

(8) Pull-up Resistance

RPULU vs. VCC

R^PULU(kΩ)

1000

TA = +25°C

100

1

2

3

4

5

6

V^CC(V)

39

MB89660 Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

AH

AL

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

Lower 8 bits of accumulator A (8 bits)

T

TH

TL

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

IX

EP

PC

SP

PS

dr

CCR

RP

Ri

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

( × )

(( × ))

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~:

#:

The number of instructions

The number of bytes

Operation: Operation of an instruction

TL, TH, AH:

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

40

MB89660 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

–

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

AL

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

–

F0

Note During byte transfer to A, T ← A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

41

MB89660 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

42

MB89660 Series

(Continued)

Mnemonic

~

#

Operation

(A) ← (AL) ( (EP) )

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

43

MB89660 Series

■ INSTRUCTION MAP

44

MB89660 Series

■ MASK OPTIONS

MB89663

MB89665

MB89P665

MB89W665

Part number

Specifying procedure

Power-on reset selection

No.

Specify when ordering

masking

Set with EPROM

programmer

1

With power-on reset

Without power-on reset

Selectable

Setting possible

Selection of the oscillation stabilization

time

Crystal oscillator

2

(26.2 ms/10 MHz)

Ceramic oscillator

(1.64 ms/10 MHz)

Reset pin output

With reset output

Without reset output

3

4

Can be selected per pin.

(P50 to P57 are available for

without pull-up resistors

when an A/D converter is

used.)

Pull-up resistors

Can be set per pin.

(P54 to P57 must have the

same setting)

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P60 to P63

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89663P-SH

MB89665P-SH

MB89P665P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89663PF

MB89665PF

MB89P665PF

64-pin Plastic SH-DIP

(FPT-64P-M06)

64-pin Ceramic SH-DIP

(DIP-64C-A06)

MB89W665C-SH

45

MB89660 Series

■ PACKAGE DIMENSIONS

64-pin Plastic SH-DIP

(DIP-64P-M01)

58.00⁺^–0⁰^.^.⁵²⁵²

+.008

2.283–.022

INDEX-1

INDEX-2

17.00±0.25

(.669±.010)

5.65(.222)MAX

3.00(.118)MIN

0.25±0.05

(.010±.002)

+0.50

1.00^–0

0.45±0.10

(.018±.004)

0.51(.020)MIN

19.05(.750)

TYP

+.020

15°MAX

.039^–0

1.778±0.18

(.070±.007)

1.778(.070)

MAX

55.118(2.170)REF

C

1994 FUJITSU LIMITED D64001S-3C-4

Dimensions in mm (inches)

64-pin Plastic QFP

(FPT-64P-M06)

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

51

33

0.05(.002)MIN

(STAND OFF)

52

32

14.00±0.20 18.70±0.40

(.551±.008) (.736±.016)

12.00(.472)

REF

16.30±0.40

(.642±.016)

INDEX

64

20

"A"

1

19

LEAD No.

0.15±0.05(.006±.002)

Details of "B" part

1.00(.0394)

TYP

0.40±0.10

(.016±.004)

M

0.20(.008)

Details of "A" part

0.25(.010)

"B"

0.30(.012)

0.18(.007)MAX

0.63(.025)MAX

0.10(.004)

18.00(.709)REF

22.30±0.40(.878±.016)

0

10°

1.20±0.20

(.047±.008)

C

1994 FUJITSU LIMITED F64013S-3C-2

Dimensions in mm (inches)

46

MB89660 Series

64-pin Ceramic SH-DIP

(DIP-64C-A06)

56.90±0.56

(2.240±.022)

8.89(.350) DIA

TYP

R1.27(.050)

REF

18.75±0.25

(.738±.010)

INDEX AREA

1.27±0.25

(.050±.010)

5.84(.230)MAX

0.25±0.05

(.010±.004)

3.40±0.36

(.134±.014)

+0.13

1.778±0.180

(.070±.007)

0.90±0.10

(.0355±.0040)

0.46^–0.08

19.05±0.25

(.750±.010)

.018⁺^–.^.⁰⁰⁰⁰³⁵

0°~9°

1.45(.057)

MAX

55.118(2.170)REF

C

1994 FUJITSU LIMITED D64006SC-1-2

Dimensions in mm (inches)

47

MB89660 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

KAWASAKI PLANT, 4-1-1, Kamikodanaka,

Nakahara-ku, Kawasaki-shi,

Kanagawa 211-8588, Japan

Tel: +81-44-754-3763

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-44-754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F9602

FUJITSU LIMITED Printed in Japan


型号：	MB89P665
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总48页 (文件大小：610K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P665 [FUJITSU]

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