MB89P665RP-SH_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12532-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89660R Series

MB89663R/665R/P665/W665

■ OUTLINE

The MB89660R series has been developed as a general-purpose version of the F²MC*-8L family consisting of

proprietary 8-bit single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such

as timers, a UART, a serial interface, an 8-bit A/D converter, an input capture, an output compare, and an external

interrupt. The MB89660R series is applicable to a wide range of applications from consumer products to industrial

equipment.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Packages

QFP-64

SH-DIP-64

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

(Continued)

■ PACKAGE

64-pin Ceramic SH-DIP

64-pin Plastic QFP

64-pin Plastic SH-DIP

(DIP-64C-A06)

(FPT-64P-M06)

(DIP-64P-M01)

MB89660R Series

(Continued)

• Four types of timers

8-bit PWM timer

8/16-bit timer/counter

20-bit timebase timer

• Functions that permit communications with a variety of devices

UART which permits selection of synchronous/asynchronous communications

A serial interface that permits selection of the transfer direction

• 8-bit A/D converter: 8 channels

Sense function capable of performing voltage compare operation in 5 µs at 10 MHz

Started by external input possible

• Real-time control

Input capture: 2 channels

Output compare: 2 channels

• External interrupt: 4 channels

Four channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low power consumption (standby modes)

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

Hardware standby mode (Wake-up from this mode and activation by pin input only.)

2

MB89660R Series

■ PRODUCT LINEUP

Part number

MB89665R

MB89W665

MB89P665

MB89663R

Item

Classification

Mass-produced products

(mask ROM products)

One-time PROM product,

also used for evaluation

EPROM product

ROM size

8 K × 8 bits 16 K × 8 bits

(internal mask ROM) (internal mask ROM) (internal PROM, to be programmed with

general-purpose EPROM programmer)

16 K × 8 bits

RAM size

256 × 8 bits

512 × 8 bits

CPU functions

The number of instructions:

Instruction bit length:

Instruction length:

136

8 bits

1 to 3 bytes

1,8, 16 bits

Data bit length:

Minimum execution time:

Interrupt processing time:

0.4 µs at 10 MHz

3.6 µs at 10 MHz

Ports

Output ports (CMOS):

Output ports (N-ch open-drain):

8

8 (All also serve as peripherals.)

General-purpose I/O ports (CMOS): 36 (19 ports also serve as peripherals.)

Total: 52

8-bit interval timer operation (square wave output capable, operating clock cycle: 0.4 µs to 25.6 µs)

8-bit resolution PWM operation (conversion cycle: 102 µs to 6.6 ms)

8-bit PWM timer

8/16-bit timer/

counter

2-channel 8-bit timer/counter operation (timer 1 and timer 2, each operating clock

independence, square wave output capable), or 16-bit timer/counter operation (operating

clock cycle: 0.8 µs to 12.8 µs)

In timer 1 or 16-bit timer/counter operation, event counter operation by external clock input

UART

Variable data length (6-, 7-, 8-bit length), built-in baud rate generator, error detection function,

built-in full-duplex double buffer NRZ type transfer format, CLK synchronous/asynchronous

data transfer capable

Transfer rate setting by dedicated band rate generator, external clock, 8-bit PWM timer

8-bit serial I/O

8 bits

LSB/MSB first selectable

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

8-bit A/D

converter

8-bit resolution × 8 channels

A/D conversion function (conversion time: 18 µs at 10 MHz)

Sense function (conversion time: 5 µs at 10 MHz)

Capable of continuous activation by an external clock or an internal clock

Reference voltage input

Real-time I/O

16-bit timer: operating clock cycle (0.4 µs, 0.8 µs, 1.6 µs, 3.2 µs)

overflow interrupt

Input capture: 16 bits × 2 channels (External trigger edge selectable)

Output capture: 16 bits × 2 channels

(Continued)

3

MB89660R Series

(Continued)

Part number

MB89665R

MB89W665

MB89P665

MB89663R

Item

External interrupt

4 channels (source flag, enable flag independently)

Rising edge/falling edge/both edges selectable

Used also for wake-up from stop/sleep mode.

(Edge detection is also permitted in stop mode.)

(Wake-up from hardware standby mode is not possible)

Low-power

consumption

(standby modes)

Sleep mode, stop mode, and hardware standby mode

CMOS

Process

Operating voltage*

(when using A/D

converter)

2.2 V to 6.0 V

(3.5 V to 6.0 V)

2.7 V to 6.0 V

(3.5 V to 6.0 V)

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89663R

MB89665R

MB89P665

Package

MB89W665

DIP-64P-M01

×

FPT-64P-M06

DIP-64C-A06

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

4

MB89660R Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTPROM (one-time PROM) product (also used for evaluation), verify its differences

from the product that will actually be used: Take particular care on the following points:

• On the MB89663R, register bank from 16 to 32 cannot be used.

• On the MB89P665, address BFF0^Hto BFF6H comprise the option setting area, option settings can be read by

reading these addresses.

• The stack area, etc., is used.

2. Current Consumption

• When operated at low speed, the product with an OTPROM or an EPROM will consume more current than

the product with a mask ROM.

• However, the same is the current comsumption in sleep/stop modes. (For more information, see sections “■

Electrical Characteristics” and “■ Example Characteristics.”

3. Mask Options

Functions that can be selected as options and how to designate these options vary with product.

Before using options, check section “■ Mask Options.”

Take particular care on the following points:

• On the MB89P665, a pull-up resistor must be selected in a group of four pins for P54 to P57.

• For all products, P50 to P57 must be set for no pull-up resistor optional when an A/D converter is used.

4. Differences between the MB89660 and MB89660R Series

• Memory access area

Memory access area of both the MB89660R and MB89660 series is the same.

• Other Specifications

For MB89660R series, input level at P00 to P07 and P10 to P17 is fixed when the hardware is standing-by.

And for MB89660 series, input level at P00 to P07 and P10 to P17 is not fixed. Therefore, when the medium

voltage is input there such as input open, the standby current will increase.

• Electrical specifications/electrical characteristics

There are differences at pull down resistances of MOD0 and MOD1 between MB89660R series and MB89660

series. For more information, see “3. DC characteristics” in section “■ Electrical Characteristics”.

Electrical specification of the other items of MB89660R series and MB89660 series are equivalent.

However, it is possible that the valid characteristic will be modified. See the corresponding characteristic

respectively for detail.

5

MB89660R Series

■ PIN ASSIGNMENT

(Top view)

1

VCC

P36/RTO1

P37/ADST

P40/SCK1

P41/SO1

P42/SI1

P43/SCK2

P44/SO2

P45/SI2

P46/PTO

P47

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

P35/RTO0

P34/RTI1

P33/RTI0

P32/TO2

P31/TO1

P30/EC

V^SS

3

4

5

6

7

8

9

P00

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

AVR

AVSS

P60/INT0

P61/INT1

P62/INT2

P63/INT3

HST

P14

P15

P16

P17

P20

P21

P22

RST

P23

MOD0

P24

MOD1

P25

X0

P26

X1

P27

V^SS

(DIP-64P-M01)

(DIP-64C-A06)

(Top view)

P45/SI2

P46/PTO

P47

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P30/EC

V^SS

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

AVR

AV^SS

P60/INT0

P61/INT1

P62/INT2

P63/INT3

HST

(FPT-64P-M06)

6

MB89660R Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

X0

Function

SH-DIP^*1

QFP^*2

23

30

31

28

29

A

Crystal oscillator pins

24

X1

21

MOD0

MOD1

B

Operation mode select pins

Connect directly to V^CCor VSS.

A pull-down resistor is selectable as an option for mask

ROM products.

22

27

20

19

RST

C

Reset I/O pin

This port is an N-ch open-drain output type with pull-up

resistor and of hysteresis input type. “L” is output from this

pin by an internal reset source. The internal circuit is

initialized by the input of “L”.

26

HST

G

D

Hardware standby input pin

Connect directly to V^CCwhen hardware standby is not

used.

56 to 49

48 to 41

40 to 33

58

49 to 42

41 to 34

33 to 26

51

P00 to P07

P10 to P17

P20 to P27

P30/EC

General-purpose I/O ports

F

E

General-purpose output ports

General-purpose I/O port

Also serves as an external clock input for an 8/16-bit

timer/counter.

This pin is of hysteresis input type and with a noise

canceller.

59

60

52

53

P31/TO1

P32/TO2

E

General-purpose high-current I/O port

Also serves as an 8/16-bit timer/counter output. This pin

is of hysteresis input type and with a noise canceller.

General-purpose I/O port

Also serves as an 8/16-bit timer/counter output. This pin

is of hysteresis input type and with a noise canceller.

61

62

54

55

P33/RTI0

P34/RTI1

General-purpose I/O ports

Also serve as the data input for the input capture. This pin

is of hysteresis input type and with a noise canceller.

63

1

56

58

P35/RTO0

P36/RTO1

General-purpose I/O ports

Also serve as the data output for the output compare. This

pin is of hysteresis input type and with a noise canceller.

2

59

P37/ADST

General-purpose high-current I/O port

Also serves as the external starting input for the A/D

converter. This pin is of hysteresis input type and with a

noise canceller.

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-64P-M06

(Continued)

7

MB89660R Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

General-purpose I/O port

Also serves as the clock I/O for the UART. This pin is of

hysteresis input type and with a noise canceller.

SH-DIP^*1

QFP^*2

3

60

P40/SCK1

P41/SO1

P42/SI1

E

4

5

6

61

62

63

General-purpose I/O port

Also serves as the data output for the UART. This pin is of

hysteresis input type and with a noise canceller.

General-purpose I/O port

Also serves as the data input for the UART. This pin is of

hysteresis input type and with a noise canceller.

P43/SCK2

General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O

interface. This pin is of hysteresis input type and with a

noise canceller.

7

8

64

1

P44/SO2

P45/SI2

P46/PTO

P47

E

General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O

interface. This pin is of hysteresis input type and with a

noise canceller.

General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O

interface. This pin is of hysteresis input type and with a

noise canceller.

9

2

General-purpose I/O port

Also serves as a toggle output for an 8-bit PWM timer.

This pin is of hysteresis input type and with a noise

canceller.

10

3

General-purpose I/O port

This pin is of hysteresis input type and with a noise

canceller.

11 to 18

22 to 25

4 to 11

P50/AN0 to

P57/AN7

H

E

N-ch open-drain output ports

Also serve as the analog input for the A/D converter.

15 to 18

P60/INT0 to

P63/INT3

General-purpose I/O ports

These pins also serve as an external interrupt input.

These pins are of hysteresis input type and with a noise

canceller.

64

57

V^CC

—

Power supply pin

32

57

25

50

VSS

Power supply (GND) pins

19

20

21

12

13

14

AVCC

AVR

AV^SS

—

A/D converter power supply pin

A/D converter reference voltage input pin

A/D converter power supply pin

Use this pin at the same voltage as VSS.

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-64P-M06

8

MB89660R Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillation feedback resistor of approximately

1 MΩ at 5.0 V

X1

N-ch

P-ch

X0

N-ch

Standby control signal

B

C

• CMOS input

• Built-in pull-down resistor (mask ROM products only)

• Output pull-up resistor (P-ch) of approximately 50 kΩ

R

at 5.0 V

P-ch

• Hysteresis input

N-ch

D

• CMOS output

• CMOS input

R

• Pull-up resistor option of approximately

50 kΩ at 5.0 V

P-ch

N-ch

E

• CMOS output

• Hysteresis input

R

• Pull-up resistor option of approximately

50 kΩ at 5.0 V

P-ch

N-ch

F

• CMOS output

P-ch

N-ch

(Continued)

9

MB89660R Series

(Continued)

Type

Circuit

Remarks

G

• Hysteresis input

H

• N-ch open-drain output

• Analog input

R

• Pull-up resistor option of approximately

50 kΩ at 5.0 V

P-ch

N-ch

Analog input

10

MB89660R Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “ ■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D Converters

Connect to be AVCC = VCC and AVSS = AVR = VSS if the A/D converters are not in use.

4. Power Supply Voltage Fluctuations

Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the

voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC

is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple

fluctuations (P-P value) will be less than 10% of the standard V^CCvalue at the commercial frequency(50 to 60

Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as

when power is switched.

5. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

11

MB89660R Series

■ PROGRAMMING TO THE EPROM ON THE MB89P665

The MB89P665 is an OTPROM version of the MB89660R series.

1. Features

• 16-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

I/O

EPROM mode

(Corresponding addresses on the EPROM programmer)

0080H

0280H

RAM

Not available

0000H

Vacancy

(Read value FF^H)

BFF0H

BFF7H

C000H

3FF0H

Option area

Not available

Not availble

3FF7H

Vacancy

(Read value FF^H)

4000H

PROM

16 KB

EPROM

16 KB

FFFFH

7FFFH

12

MB89660R Series

3. Programming to the PROM

In EPROM mode, the MB89P665A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000^Hto 7FFFH (note that addresses C000H to FFFFH

while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode).

Load option data into addresses 3FF0^Hto 3FF6H of the EPROM programmer. (For information about each

corresponding option, see “8. Setting OTPROM Options.”)

(3) Program with the EPROM programmer.

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

13

MB89660R Series

5. Programming Yield

Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming

yield of 100% cannot be assured at all times.

6. Erasure Procedure

In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an

ultraviolet light source. A dosage of 10 W-seconds/cm²is required to completely erase an internal EPROM. This

dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity

of 12000 µW/cm²for 15 to 21 minuites. The internal EPROM should be about one inch from the source and all

filters should be removed from the UV light source prior to erasure.

It is important to note that the internal EPROM and similar devices, will erase with light sources having wave-

lengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,

nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and

exposure to them should be prevented to realize maximum system reliability. If used in such an environment,

the package windows should be covered by an opaque label or substance.

7. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Recommended programmer manufacturer

and programmer name

Compatible socket adapter

Part number

Package

Sun Hayato Co., Ltd.

Minato Electronics Inc. Data I/O Co., Ltd.

1890A

1891

1930

R4945A

MB89W665

SH-DIP-64 ROM-64QF-28DP-8L5

ROM-64QF-28DP-8L

SH-DIP-64 ROM-64SD-28DP-8L

—

Recommended

—

MB89P665PF QFP-64

MB89P665

Recommended

—

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

Minato Electronics Inc.: TEL: USA (1)-916-348-6066

JAPAN (81)-45-591-5611

Data I/O Co., Ltd.:TEL: USA/ASIA (1)-206-881-6444

EUROPE (49)-8-985-8580

Note: Connect the adapter jumper pin to V^SSwhen using.

14

MB89660R Series

8. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vacancy

Oscillation

Reset pin Power-on Vacancy

Vacancy

stabilization output

3FF0^HReadable Readable Readable time

reset

Readable Readable

and

writable

and

writable

and

writable

1: Crystal

0: Ceramic 0: No

1: Yes

0: No

and

writable

and

writable

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

1: Yes

Pull-up

1: No

1: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

3FF1^H

3FF2^H

3FF3^H

3FF4^H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P47

P46

P45

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P57 to P54 P53

P52

P51

P50

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

3FF5^HReadable Readable Readable

and

writable

and

writable

Vacancy

P63

P62

P61

P60

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

3FF6^HReadable Readable Readable Readable

and

writable

and

writable

and

writable

Note: • Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

15

MB89660R Series

■ BLOCK DIAGRAM

X0

X1

Oscillator

21-bit timebase timer

8-bit PWM timer

P47

P46/PTO

Clock controller

Reset circuit

(WDT)

P45/SI2

RST

HST

8-bit serial I/O

UART

P44/SO2

P43/SCK2

Hardware standby

CMOS I/O port

P42/SI1

P41/SO1

P40/SCK1

8

P00 to P07

P10 to P17

CMOS I/O port

P37/ADST

P36/RTO1

P35/RTO0

Output compare

16-bit timer

8

P20 to P27

P34/RTI1

P33/RTI0

Input capture

Real-time I/O

CMOS output port

P32/TO2

8/16-bit

timer/counter

P31/TO1

P30/EC

RAM

N-ch open-drain output port

F²MC-8L

CPU

8

4

P50/AN0

8-bit A/D converter

to P57/AN7

ROM

AVR

AV^CC

AVSS

4

P60/INT0

to P63/INT3

External interrupt

The other pins

VCC, VSS × 2

CMOS I/O port

MOD0, MOD1

16

MB89660R Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89660R series offer 64 Kbytes of memory for storing all of I/O, data, and program

areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/O

area. The data area can be divided into register, stack, and direct areas according to the application. The program

area is allocated from exactly the opposite end, that is, near the highest address. The tables of interrupt reset

vectors and vector call instructions are allocated from the highest address within the program area. The memory

space of the MB89660R series is structured as illustrated below.

Memory Space

MB89663R

I/O

MB89665R

MB89W665

MB89P665

0000H

0080H

0000H

0080H

0100H

I/O

RAM

256 B

RAM

512 B

0100H

0180H

Register

0200H

0280^H

Not available

C000H

ROM*

16 KB

E000H

FFFFH

ROM

8 KB

FFFFH

*: When the MB89P665 is used for evaluation, the internal ROM cannot be used.

17

MB89660R Series

2. Registers

The F²MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose

memory registers. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating the instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which is used for arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit pointer for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bits

PC

: Program counter

: Accumulator

FFFD^H

A

T

Indeterminate

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

• Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

Vacancy

PS

RP

Vacancy

H

IL1, 0

N

V

C

RP

CCR

18

MB89660R Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interruptisenabledwhenthisflagissetto‘1’. Interruptisdisabledwhentheflagisclearedto‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.

19

MB89660R Series

The following general-purpose registers are provided:

General-purpose registers: an 8-bit register for storing data

The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 16 banks can be used on the MB89663R and a total of 32 banks can be used

on the MB89665R/P665/W665. The bank currently in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

• Register Bank Configuration

This address = 0100H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

R7

32 banks

Memory area

20

MB89660R Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

STBC

WDTC

TBTC

Standby control register

Watchdog timer control register

Timebase timer control register

Vacancy

(R/W)

(W)

PDR3

DDR3

PDR4

DDR4

PDR5

Port 3 data register

Port 3 data direction register

Port 4 data register

Port 4 data direction register

Port 5 data register

Vacancy

(R/W)

(W)

(R/W)

(W)

PDR6

DDR6

Port 6 data register

Port 6 data direction register

Vacancy

(R/W)

(W)

ADC1

ADC2

ADCD

T2CR

T1CR

T2DR

T1DR

CNTR

COMR

A/D converter control register 1

A/D converter control register 2

A/D converter data register

Timer 2 control register

Timer 1 control register

Timer 2 data register

Timer 1 data register

PWM control register

PWM compare register

Vacancy

(Continued)

21

MB89660R Series

(Continued)

Address

20H

21H

22^H

23^H

24H

25^H

26^H

27H

28^H

29H

2A^H

2BH

2CH

2D^H

2EH

2FH

30^H

31H

32^H

33H

34H

35^H

36H

37H

38^H

7C^H

7DH

7EH

7F^H

Read/write

(R/W)

(R)

Register name

SMC

Register description

UART serial mode control register

UART serial rate control register

UART serial status/data register

UART serial data register

Serial mode register

SRC

SSD

SIDR/SODR

SMR

SDR

Serial data register

EIC1

External interrupt control register 1

External interrupt control register 2

Timer control register

EIC2

TMCR

TCHR

TCLR

Timer count register (H)

Timer count register (L)

(R)

(R/W)

(R)

OPCR

CPR0H

CPR0L

CPR1H

CPR1L

ICCR

Output control register

Output compare register 0 (H)

Output compare register 0 (L)

Output compare register 1 (H)

Output compare register 1 (L)

Input capture control register

Input capture interrupt control register

Input capture register 0 (H)

Input capture register 0 (L)

Input capture register 1 (H)

Input capture register 1 (L)

Vacancy

ICIC

ICR0H

ICR0L

ICR1H

ICR1L

(R)

Vacancy

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

Note: Do not use vacancies.

22

MB89660R Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

V^CC

AVCC

VSS – 0.3

VSS + 7.0

V

*

Power supply voltage

AVR must not exceed “AV^CC+ 0.3 V”

AVR

VI

V^SS– 0.3

VSS – 0.3

VSS + 7.0

VCC + 0.3

V

Input voltage

Output voltage

V^O

“L” level maximum output

current

I^OL

—

20

4

mA

“L” level average output

current

Average value (operating

current × operating rate)

I^OLAV

ΣI^OL

ΣI^OLAV

I^OH

“L” level total maximum output

current

100

40

“L” level total average output

current

Average value (operating

current × operating rate)

“H” level maximum output

current

–20

–4

“H” level average output

current

Average value (operating

current × operating rate)

I^OHAV

ΣI^OH

ΣI^OHAV

“H” level total maximum output

current

–50

–20

“H” level total average output

current

Average value (operating

current × operating rate)

Power consumption

Operating temperature

Storage temperature

P^D

—

300

+85

mW

°C

T^A

–40

–55

Tstg

+150

°C

* : Use AV^CCand VCC set to the same voltage.

Take care so that AV^CCdoes not exceed VCC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

23

MB89660R Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Sym-

Parameter

bol

Unit

Remarks

Min.

Max.

Normal operation assurance range*

MB89663R/665R

2.2*

2.7*

1.5

6.0*

V

V^CC

Normal operation assurance range*

MB89P665

6.0*

6.0

AVCC

Power supply voltage

Operating temperature

Retains the RAM state in the stop

mode

AVR

0.0

AV^CC

+85

V

TA

–40

°C

* : These values vary with the operating frequency and analog assurance range. See Figure. 1 and “5. A/D Converter

Electrical Characteristics.”

• Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MHz)

6

5

Analog accuracy assured in the

AV^CC= VCC = 3.5 to 6.0 V range

Operation assurance range

4

3

2

1

2

3

4

5

6

7

8

9

10

Main clock operating frequency (MHz)

Note: The shaded area is assured only for the MB89663R/665R.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

24

MB89660R Series

3. DC characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17

V^IH

—

0.7 V^CC

—

VCC + 0.3

V

“H” level input

voltage

RST, HST

P30 to P37,

P40 to P47,

P60 to P63

V^IHS

VIL

—

0.8 V^CC

V^SS– 0.3

—

VCC + 0.3

0.3 VCC

0.2 VCC

V

P00 to P07,

P10 to P17

“L” level input

voltage^*1

RST, HST

P30 to P37,

P40 to P47,

P60 to P63

VILS

Open-drain

output pin

V^D

P50 to P57

—

VSS – 0.3

—

VCC + 0.3

V

applied voltage

P00 to P07,

P10 to P17,

P20 to P27,

P30,

P32 to P36,

P40 to P47,

P60 to P63

V^OH1

IOH = –2.0 mA

IOH = –15 mA

2.4

—

V

“H” level output

voltage

V^OH2

P31, P37

P00 to P07,

P10 to P17,

P20 to P27,

P30,

P32 to P36,

P40 to P47,

P50 to P57,

P60 to P63

IOL = +1.8 mA

V^OL1

—

0.4

V

“L” level output

voltage

IOL = +12 mA

IOL = +4.0 mA

V^OL2

P31, P37

RST

—

0.4

V

VOL3

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P47,

P60 to P63

Input leakage

0.45 V

Withoutpull-up

resistor

current (Hi-z output

leakage current)

ILI

—

±5

µA

kΩ

< VI < VCC

Pull-up

resistance

RST,

option select pin

R^PULU

VI = 0.0 V

25

50

100

(Continued)

25

MB89660R Series

(Continued)

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Pull-down

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

Mask ROM

products only

R^PULD

MOD0, MOD1 VI = +5.0 mA

25

50

100

kΩ

mA

resistance

MB89663R/

665R

FC = 10 MHz

—

15

17

18

20

t^inst*3= 0.4 µs

I^CC

in the Normal

mode

MB89P665/

W665

FC = 10 MHz

t^inst*3= 0.4 µs

in the Sleep

mode

VCC

I^CCS

I^CCH

I^A

—

6

8

mA

µA

TA = +25°C

t^inst*3= 0.4 µs

in the Stop

mode

Power supply

current

—

10

4.5

FC = 10 MHz,

when A/D

conversionis

operating

2.5

mA

AVCC

FC = 10 MHz,

TA = +25°C,

I^AH

—

5

µA

when A/D

conversion is

not operating

Other than

Input

capacitance

AVCC, AVSS, VCC, f = 1 MHz

10

—

pF

C^IN

and VSS

*1: Fix MOD0 and MOD1 to V^SS.

*2: The power supply current is measured on the external clock at “V^CC= 5.0 V”.

*3: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

26

MB89660R Series

4. AC Characteristics

(1) Reset Timing, Hardware Standby Timing

(V^CC= +5.0 V±10%, AVSS =VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Max.

—

RST “L” pulse width

HST “L” pulse width

tZLZH

tHLHH

16 t^XCYL

16 tXCYL

ns

—

* : t^XCYLis the oscillation cycle (1/FC) to input to the X0 pin.

tZLZH

RST

HST

0.2 VCC

tHLHH

0.2 VCC

(2) Power-on Reset

Parameter

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Values

Symbol

Condition

Unit

Remarks

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

—

50

ms

—

Due to repeated

operations

t^OFF

1

—

Note: Make sure that power supply rises within the oscillation stabilization time selected.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tOFF

t^R

2.0 V

0.2 V

VCC

0.2 V

27

MB89660R Series

(3) Clock Timing

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

name

Min.

1

Typ.

—

Max.

10

Clock frequency

Clock cycle time

F^C

X0, X1

—

MHz

ns

t^XCYL

100

—

1000

Input clock pulse

width

P^WH

PWL

External clock

X0

—

20

—

ns

Input clock rising/

falling time

tCR

tCF

10

X0 and X1 Timing and Conditions of Applied Voltage

tXCYL

PWL

PWH

tCF

tCR

0.8 VCC

X0

0.2 VCC

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

When operating at “F^C= 10 MHz”

Instruction cycle

(minimum execution

time)

t^inst

4/FC

µs

28

MB89660R Series

(5) Serial I/O Timing and UART Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Pin name Condition

Unit

Remarks

Min.

Max.

SCK1,

SCK2

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

tSHIX

2 t^inst*

—

µs

ns

µs

ns

µs

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

SCK1, SO1

SCK2, SO2

–200

1/2 t^inst*

1 t^inst*

0

200

—

Internal

shift clock

mode

Valid SI1 → SCK1 ↑

SI1, SCK1

SI2, SCK2

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

—

SCK1,

SCK2

Serial clock “H” pulse width t^SHSL

Serial clock “L” pulse width t^SLSH

—

SCK1,

SCK2

—

External

shift clock

mode

SCK1 ↓ → SO1 time

t^SLOV

SCK1, SO1

SCK2, SO2

200

—

SCK2 ↓ → SO2 time

Valid SI1 → SCK1 ↑

t^IVSH

SI1, SCK1

SI2, SCK2

1/2 t^inst*

Valid SI2 → SCK2 ↑

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

tSHIX

—

SCK2 ↑ → valid SI2 hold time

* : For information on t^inst, see “(4) Instruction Cycle.”

29

MB89660R Series

• Serial I/O Timing and UART Timing (Internal Shift Clock Mode)

t^SCYC

2.4 V

SCK1

SCK2

0.8 V

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

• Serial I/O Timing and UART Timing (External Shift Clock Mode)

tSLSH

tSHSL

0.8 VCC

SCK1

SCK2

0.2 VCC

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

30

MB89660R Series

(6) Peripheral Input Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min.

Max.

Peripheral input “H” level

pulse width 1

t^ILIH1

t^IHIL1

t^ILIH2

t^IHIL2

t^ILIH3

t^IHIL3

t^ILIH3

tIHIL3

—

µs

RTI0, RTI1

INT0 to INT3

2 t^inst*

Peripheral input “L” level

pulse width 1

—

Peripheral input “H” level

pulse width 2

EC

1 tinst*

32 tinst*

8 tinst*

Peripheral input “L” level

pulse width 2

Peripheral input “H” level

pulse width 3

A/D mode

Peripheral input “L” level

pulse width 3

ADST

Peripheral input “H” level

pulse width 3

Sense mode

Peripheral input “L” level

pulse width 3

* : For information on t^inst, see “(4) Instruction cycle.”

tIHIL1

tILIH1

0.8 VCC

0.2 VCC

INT0 to 3

RTI0, RTI1

0.2 VCC

tIHIL2

tILIH2

0.8 VCC

0.2 VCC

EC

0.2 VCC

tIHIL3

tILIH3

0.8 VCC

0.2 VCC

ADST

0.2 VCC

31

MB89660R Series

(7) Noise Filter

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

P30 to P37,

P40 to P47,

P60 to P63

During port

operation

Noise filter width 1

Noise filter width 2

t^INF1

15

—

ns

During external

interrupt

t^INF2

P60 to P63

60

—

tINF 1,

2

tINF 1,

2

0.8 VCC

0.2 VCC

Input waveform

32

MB89660R Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Resolution

Symbol Pin name

Condition

Unit Remarks

Min.

—

Typ.

—

Max.

8

—

bit

Total error

—

±2.0

±1.0

±0.9

AVSS+

LSB

—

Linearity error

—

Differential linearity error

—

AVSS –

AVSS+

AVR = AV^CC

Zero transition voltage

V^OT

V^FST

mV

1.5 LSB 0.5 LSB 2.5 LSB

—

Full-scale transition

voltage

AVR – AVR – AVR +

3.5 LSB 1.5 LSB 0.5 LSB

Interchannel disparity

—

1

LSB

A/D mode conversion time

44 t^isnt*

—

µs

—

Sense mode conversion

time

—

12 t^inst*

—

µs

—

Analog port input circuit

Analog input voltage

Reference voltage

I^AIN

—

0

—

10

µA

V

AN0 to AN7

AVR

AVCC

—

0

V

AVR = 5.0 V

when A/D

conversion is

operating

I^R

—

150

—

5

µA

AVR

Reference voltage

supply current

AVR = 5.0 V

when A/D

conversion is

not operating

I^RH

* : For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

6. A/D Glossary

• Resolution

Analog changes that are identifiable by the A/D converter

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

33

MB89660R Series

Digital output

1111 1111

1111 _•1110

Theoretical conversion value

Actual conversion value

•

(1 LSB × N + V^OT)

AVR

256

1 LSB =

VNT – (1 LSB × N + VOT)

Linearity error =

1 LSB

V( N + 1 ) T – VNT

Differential linearity error =

– 1

1 LSB

Linearity error

VNT – (1 LSB × N + 1 LSB)

Total error =

1 LSB

0000 ^•0010

0000 0001

0000 0000

VOT

VNT

V( N+I )T

VFST

Analog input

7. A/D Converter

• Input impedance of analog input pins

The A/D converter used for the MB89660R series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 2 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

.

=

C

33 pF

.

Analog input pin

Comparator

.

=

R

6 kΩ

.

If the output impedance of

the external circuit is high, it

is recommended to connect

an external capacitor of

approx. 0.1 µF.

Closes for 8 instruction cycles

after starting A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

34

MB89660R Series

■ EXAMPLES CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

P00 to P07, P10 to P17,P20 to P27, P30, P32 to

P36, P40 to P47, P50 to P57, P60 to P63

P00 to P07, P10 to P17, P20 to P27, P30, P32

to P36, P40 to P47, P60 to P63

VOL vs. IOL

VCC - VOH vs. IOH

V^CC- VOH (V)

V^OL(V)

TA = +25°C

V^CC= 3.0 V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 4.0 V

TA = +25°C

V ^CC= 2.5 V

0.5

0.4

0.3

0.2

0.1

V^CC= 5.0 V

V^CC= 6.0 V

V^CC= 3.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0

I^OH(mA)

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(4) “H” Level Output Voltage

P31, P37

(3) “L” Level Output Voltage

P31, P37

VDD-VOH2 (V)

VDD-VOH2 vs. IOH2

VOL2 (V)

VOL2 vs. IOL2

VCC = 6.0 V

V^CC= 5.0 V

V^CC= 4.0 V

V^CC= 3.0 V

3

2

1

0

0.6

VCC = 6.0 V T^A= +25°C

V^CC= 5.0 V

V^CC= 4.0 V

TA = +25°C

0.5

0.4

0.3

0.2

0.1

0

V^CC= 3.0 V

0

5

10

15

20

25

I^OH2(–mA)

0

10

20

I^OL2(mA)

35

MB89660R Series

(5) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(6) “H” Level Input Voltage/“L” Level

Input Voltage (Hysteresis Input)

V^IN(V)

5.0

VIN vs. VCC

TA = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V^IN(V)

5.0

V IN vs. VCC

TA = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V^IHS

VILS

0.0

0

1

2

3

4

5

6

7

VCC (V)

0.0

0

Threshold when input voltage in hysteresis

characteristics is set to “H” level

V^IHS:

1

2

3

4

5

6

7

V^CC(V)

Threshold when input voltage in hysteresis

V^ILS:

characteristics is set to “L” level

(7) Power Supply Current (External Clock)

ICCS vs. VCC

ICC vs. VCC

I^CC(mA)

I^CCS(mA)

9

3

TA = +25°C

1 MHz

4 MHz

8 MHz

1 MHz

4 MHz

8 MHz

10 MHz

8

7

6

2

1

0

10 MHz

5

4

3

2

1

0

1

2

3

4

5

6

1

2

3

4

5

6

7

V^CC(V)

VCC (V)

36

MB89660R Series

(8) Pull-up Resistance

RPULL vs. VCC

R^PULL(kΩ)

1000

TA = +25°C

100

10

1

2

3

4

5

6

V^CC(V)

37

MB89660R Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

T

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

TH

TL

IX

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

38

MB89660R Series

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

The number of instructions

The number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

39

MB89660R Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

40

MB89660R Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

41

MB89660R Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

42

MB89660R Series

■ INSTRUCTION MAP

43

MB89660R Series

■ MASK OPTIONS

MB89663R

MB89665R

MB89P665

MB89W665

Part number

No.

Specify when ordering masking

Specify with EPROM programmer

Specifying procedure

Power-on reset

1

2

• Power-on reset provided

• No power-on reset

Selectable

Selection of the oscillation stabilization

time

• Crystal oscillator

Selectable

(26.2 ms at 10 MHz)

• Ceramic oscillator

(1.64 ms at 10 MHz)

Reset pin output

3

4

• With reset output

• Without reset output

Selectable

Can be selected per pin.

(Pull-up resistors can NOT

be selected for P50 to P57

when an A/D converter is

used.)

Pull-up resistors

Can be set per pin.

(P54 to P57 must have the

same setting)

• P00 to P07, P10 to P17,

• P30 to P37, P40 to P47,

• P50 to P57, P60 to P63

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89663RP-SH

MB89665RP-SH

MB89P665P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89663RPF

MB89665RPF

MB89P665PF

64-pin Plastic QFP

(FPT-64P-M06)

64-pin Ceramic SH-DIP

(DIP-64C-A06)

MB89W665C-SH

44

MB89660R Series

■ PACKAGE DIMENSION

58.00 ⁺^–0⁰^.^.⁵²⁵²

2.283 ⁺^–.^.⁰⁰²⁰²⁸

64-pin Plastic SH-DIP

(DIP-64P-M01)

INDEX-1

INDEX-2

17.00±0.25

(.669±.010)

5.65(.222)MAX

3.00(.118)MIN

0.25±0.05

(.010±.002)

1.00 –⁺0^0.50

.039 ⁺^–0^.020

0.45±0.10

(.018±.004)

0.51(.020)MIN

19.05(.750)

TYP

15°MAX

1.778±0.18

(.070±.007)

1.778(.070)

MAX

55.118(2.170)REF

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED D64001S-3C-4

64-pin Plastic QFP

(FPT-64P-M06)

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

51

33

0.05(.002)MIN

(STAND OFF)

52

32

14.00±0.20 18.70±0.40

(.551±.008) (.736±.016)

12.00(.472)

REF

16.30±0.40

(.642±.016)

INDEX

64

20

"A"

1

19

LEAD No.

0.15±0.05(.006±.002)

Details of "B" part

1.00(.0394)

TYP

0.40±0.10

(.016±.004)

M

0.20(.008)

Details of "A" part

0.25(.010)

"B"

0.30(.012)

0.18(.007)MAX

0.10(.004)

18.00(.709)REF

0

10°

1.20±0.20

0.63(.025)MAX

(.047±.008)

22.30±0.40(.878±.016)

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F64013S-3C-2

45

MB89660R Series

64-pin Ceramic SH-DIP

(DIP-64C-A06)

56.90±0.56

(2.240±.022)

8.89(.350) DIA

TYP

R1.27(.050)

REF

18.75±0.25

(.738±.010)

INDEX AREA

1.27±0.25

(.050±.010)

5.84(.230)MAX

3.40±0.36

0.25±0.05

(.010±.004)

1.778±0.180

(.070±.007)

0.90±0.10

(.0355±.0040)

0.46 –⁺0⁰.^.0¹8³

19.05±0.25

(.750±.010)

(.134±.014)

.018 ⁺^–.^.⁰⁰⁰⁰³⁵

0°~9°

1.45(.057)

MAX

55.118(2.170)REF

C

Dimensions in mm (inches)

1994 FUJITSU LIMITED D64006SC-1-2

46

MB89660R Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

measurement equipment, personal or household devices, etc.).

CAUTION:

Fax: (408) 922-9179

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded

(such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

http://www.fmap.com.sg/

F9901

FUJITSU LIMITED Printed in Japan

47


型号：	MB89P665RP-SH
厂家：	FUJITSU
描述：	Microcontroller, 8-Bit, UVPROM, F2MC-8L CPU, 10MHz, CMOS, PDIP64 可编程只读存储器微控制器光电二极管
文件：	总47页 (文件大小：649K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P665RP-SH [FUJITSU]

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