MB89P677APFM [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有![MB89P677APFM](http://pdffile.icpdf.com/pdf1/p00084/img/icpdf/MB89P677A_443753_icpdf.jpg)
型号: | MB89P677APFM |
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描述: | 8-bit Proprietary Microcontroller |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12514-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89670/A Series
MB89673/677A/P677A/PV670A
■ DESCRIPTION
The MB89670/A series has been developed as a line of proprietary 8-bit, single-chip microcontrollers.
In addition to the F2MC*-8L CPU core which can operate at low voltage but at high speed, the microcontrollers
contain pheripheral functions such as timers, a serial interface, an A/D converter, a UART, an up/down counter,
and an external interrupt.
TheMB89670/Aseriesisapplicabletoawiderangeofapplicationsfromwelfareproductstoindustrialequipment,
including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• High-speed processing at low voltage
• Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V, 2.0 µs/2.2 V
• I/O ports: max. 69 channels
(Continued)
■ PACKAGE
80-pin Plastic QFP
80-pin Plastic QFP
80-pin Ceramic MQFP
(FPT-80P-M11)
(FPT-80P-M06)
(MQP-80C-P01)
MB89670/A Series
(Continued)
• Timers: 9 channels (MB89670A: 12 channels)
8-bit PWM timer: 3 channels (MB89670A: 6 channels) (also usable as a reload timer)
16-bit timer/counter
21-bit time-base timer
8/16-bit timer (8 bits × 2 channels or 16 bits)
8/16-bit up/down counter timer (8 bits × 2 channels or 16 bits)
• Two serial interfaces
8-bit synchronized serial: 1 channel (Switchable transfer direction allows communication with various
equipment.)
UART: 1 channel (with full-duplex double buffer)
• External interrupts: 8 channels
Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Buzzer output
• 10-bit A/D converter
8-channel input
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
• Bus interface function
Including hold and ready functions
2
MB89670/A Series
■ PRODUCT LINEUP
Part number
MB89673*1
MB89677A
MB89P677A
MB89PV670A
Parameter
Piggyback/ evaluation
One-time PROM product
(for development)
Classification
Mass production products
(mask ROM products)
product (for development)
ROM size
8 K × 8 bits 32 K × 8 bits
(internal mask ROM) (internal mask ROM)
32 K × 8 bits
(internal PROM)
48 K × 8 bits
(external ROM)
RAM size
384 × 8 bits
1 K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Data bit length:
Minimum execution time:
Interrupt processing time:
0.4 µs/10 MHz to 6.4 µs/10 MHz
3.6 µs/10 MHz to 57.6 µs/10 MHz
Ports
Output ports (N-channel open-drain): 14 (12 also serve as peripherals.)
Output ports (CMOS):
I/O ports (N-channels open-drain):
I/O ports (CMOS):
Input ports:
8 (All also serve as peripherals.)
7 (All also serve as peripherals.)
32 (All also serve as peripherals.)
8 (All also serve as peripherals.)
69
Total:
Option
Set with EPROM
programmer
Specify when ordering masking
Setting not possible
21-bit time-
base timer
21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms/10 MHz)
8/16-bit up/
down counter
8 bits × 2 channels or 16 bits × 1 channel
Timer operation
Up/down counter operation
Phase difference counting (successive double mode, quadruple mode)
16-bit timer/
counter
16-bit timer operation
16-bit event counter operation (edge selectability)
8/16-bit timer
counter
8 bits × 2 channels or 16 bits × 1 channel
Reload timer operation (toggled output capable)
Event counter operation
8-bit PWM
timer 1,
8-bit PWM
timer 2
8 bits × 2 channels reload timer operation (toggled output capable)
8 bits × 2 channels PWM operation (four fixed frequency)
8 bits × 1 channel PPG operation (variable frequency)
Capable of output switching between 2 channels
8-bit PWM
timer 3,
8-bit PWM
timer 4, 5, 6
8-bit reload timer operation (toggled output capable)
8-bit PWM operation (four fixed frequency)
Capable of output switching between 2 channels
8-bit serial I/O
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks)
(Continued)
3
MB89670/A Series
(Continued)
Part number
MB89673*1
MB89677A
MB89P677A
MB89PV670A
Parameter
UART
Variable data length (7 or 8 bits)
Internal baud rate generator
Error detection function
Intenal full-duplex double buffer
NRZ transfer format
CLK synchrnous/asynchronous data transfer capable
10-bit A/D
converter
10 bit × 8 channels
External
interrupt
8 channels (Rising edge/falling edge)
Operating
2.2 V to 6.0 V
2.7 V to 6.0 V
voltage*2
EPROM for use
MBM27C512-20TV
(LCC package)
*1: 8-bit PWM timer 4, 5, and 6 is not provided for the MB89673.
*2: The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89673
Package
MB89677A
MB89PV670A
MB89P677A
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
×
×*
×
: Available
× : Not available
* : Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available
80QF-80QF2-8L-UP
+ (MQP-80C-P01 or FPT-80P-M06) → for conversion to FPT-80P-M11
80QF-80QF2-8L-DWN
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89670/A Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89P677A, the program area starts from address 8007H but on the MB89677A and MB89PV670A
starts from 8000H.
(On the MB89P677A, addresses 8000H to 8006H comprise the option setting area, option settings can be read
by reading these addresses. On the MB89677A and MB89PV670A, addresses 8000H to 8006H could also be
used as a program ROM. However, do not use these addresses in order to maintain compatibility of the
MB89P677A.)
• The stack area, etc., is set at the upper limit of the RAM.
• The external area is used.
2. Current Consumption
• InthecaseoftheMB89PV670A,addthecurrentconsumedbytheEPROMwhichisconnectedtothetopsocket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following point:
• Options are fixed on the MB89PV670A.
■ CORRESPONDENCE BETWEEN THE MB89670/A AND MB89670R/AR SERIES
• The MB89670R/AR series is the reduction version of the MB89670/A series.
For their differences, refer to the MB89670R/AR series data sheet.
MB89670/A series
MB89673
—
MB89677A
MB89P677A
MB89PV670A
MB89670R/AR series
MB89673R
MB89675R
MB89677AR
5
MB89670/A Series
■ PIN ASSIGNMENT
(Top view)
P73/UI
P72/UO
P71/UCK
P70/BZ1
P83
P82
P81
P80
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P66/INT6
P67/INT7
P84
P85
VSS
P40/PWM00
P41/PWM01
VCC
P42/PWM10/BZ2
P43/PWM11
P44/TCI
P45/TCO1
P46/TCO2
P47/EC
P30/PWM20
P31/PWM21
P32/UDZ1
P33/UDB1
P34/UDA1
P35/UDZ2
9
10
11
12
13
14
15
16
17
18
19
20
RST
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
(FPT-80P-M11)
6
MB89670/A Series
(Top view)
P75/SO
P74/SCK
P73/UI
P72/UO
P71/UCK
P70/BZ1
P83
P82
P81
P80
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P64/INT4
P65/INT5
P66/INT6
P67/INT7
P84
P85
VSS
101
102
103
104
105
106
107
108
109
93
92
91
90
89
88
87
86
85
P40/PWM00
P41/PWM01
VCC
P42/PWM10/BZ2
P43/PWM11
P44/TCI
P45/TCO1
P46/TCO2
P47/EC
P30/PWM20
P31/PWM21
P32/UDZ1
P33/UDB1
P34/UDA1
P35/UDZ2
P36/UDB2
P37/UDA2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RST
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
Each pin inside the dashed line
is for the MB89PV670A only.
(FPT-80P-M06)
(MQP-80C-P01)
• Pin assignment on package top (MB89PV670A only)
Pin no.
81
Pin name
N.C.
A15
A12
A7
Pin no.
89
Pin name
A2
Pin no.
97
Pin name
N.C.
O4
Pin no.
105
Pin name
OE/VPP
N.C.
A11
82
90
A1
98
106
83
91
A0
99
O5
107
84
92
N.C.
O1
100
101
102
103
104
O6
108
A9
85
A6
93
O7
109
A8
86
A5
94
O2
O8
110
A13
87
A4
95
O3
CE
111
A14
88
A3
96
VSS
A10
112
VCC
N.C.: Internally connected. Do not use.
7
MB89670/A Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
QFP*2
Pin name
Function
QFP*1
MQFP*3
11
12
9
13
14
11
12
16
X0
X1
A
B
C
Clock oscillator pins
MOD0
MOD1
RST
Operating mode selection pins
Connect directly to VCC or VSS.
10
14
Reset I/O pin
This pin is an N-ch open-drain output type with pull-up
resistor and a hysteresis input.
“L” is output from this pin by an internal reset source.
The internal circuit is initialized by the input of “L”.
38 to 31
30 to 23
22
40 to 33
32 to 25
24
P00/AD0 to
P07/AD7
D
General-purpose I/O ports
When an external bus is used, these ports function as
multiplex pins of lower address output and data I/O.
P10/A08 to
P17/A15
General-purpose I/O ports
When an external bus is used, these ports function as
upper address output pins.
P20/BUFC
P21/HAK
F
F
General-purpose output port
When an external bus is used, this port can also be
used as a buffer control output by setting the BCTR.
21
23
General-purpose output port
When an external bus is used, this port can also be
used as a hold acknowledge output by setting the
BCTR.
20
19
18
17
16
15
22
21
20
19
18
17
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
D
D
F
F
F
F
General-purpose output port
When an external bus is used, this port can also be
used as a hold request input by setting the BCTR.
General-purpose output port
When an external bus is used, this port functions as a
ready input.
General-purpose output port
When an external bus is used, this port functions as a
clock output.
General-purpose output port
When an external bus is used, this port functions as a
write signal output.
General-purpose output port
When an external bus is used, this port functions as a
read signal output.
P27/ALE
General-purpose output port
When an external bus is used, this port functions as an
address latch signal output.
(Continued)
*1: FPT-80P-M11
*2: FPT-80P-M06
*3: MQP-80C-P01
8
MB89670/A Series
Pin no.
Circuit
type
QFP*2
Pin name
Function
QFP*1
MQFP*3
46
48
P30/PWM20
D
D
E
E
E
E
E
E
D
D
D
D
E
D
General-purpose I/O port
Also serves as the PWM20 output for the 8-bit PWM
timer.
45
44
43
42
41
40
39
55
54
52
51
50
49
47
46
45
44
43
42
41
57
56
54
53
52
51
P31/PWM21
P32/UDZ1
P33/UDB1
P34/UDA1
P35/UDZ2
P36/UDB2
P37/UDA2
P40/PWM00
P41/PWM01
General-purpose I/O port
Also serves as the PWM21 output for the 8-bit PWM
timer.
General-purpose I/O port
Also serves as the Z-phase input for the 16-bit up/down
counter/timer.
General-purpose I/O port
Also serves as the B-phase input for the 16-bit timer/
counter.
General-purpose I/O ports
Also serves as the A-phase input for the 16-bit up/down
counter/timer.
General-purpose I/O port
Also serves as the Z-phase input for the 16-bit up/down
counter/timer.
General-purpose I/O port
Also serves as the B-phase input for the 16-bit up/down
counter/timer.
General-purpose I/O port
Also serves as the A-phase input for the 16-bit up/down
counter/timer.
General-purpose I/O port
Also serves as the PWM00 output for the 8-bit PWM
timer.
General-purpose I/O port
Also serves as the PWM01 output for the 8-bit PWM
timer.
P42/PWM10/
BZ2
General-purpose I/O port
Also serves as the PWM10 and the BZ2 output for the 8-
bit PWM timer.
P43/PWM11
P44/TCI
General-purpose I/O port
Also serves as the PWM11 output for the 8-bit PWM
timer.
General-purpose I/O port
Also serves as the TCI input for the 8/16-bit timer/
counter.
P45/TCO1
General-purpose I/O port
Also serves as the TCO1 output for the 8/16-bit timer/
counter.
(Continued)
*1: FPT-80P-M11
*2: FPT-80P-M06
*3: MQP-80C-P01
9
MB89670/A Series
(Continued)
Pin no.
Circuit
type
QFP*2
Pin name
P46/TCO2
Function
General-purpose I/O port
Also serves as the TCO2 output for the 8/16-bit timer/
counter.
QFP*1
MQFP*3
48
50
D
47
49
P47/EC
E
General-purpose I/O port
Also serves as input for the16-bit timer/counter.
The EC input is a hysteresis input type.
74 to 67
66
76 to 69 P50/AN0 to
P57/AN7
I
N-ch open-drain output ports
Also serve as the analog input for the A/D converter.
68
P60/INT0/
ADST
J
General-purpose input port
The software pull-up resistor is provided.
Also serves as an external interrupt input (INT0) and an
A/D converter external activation.
This port is a hysteresis input type.
65 to 59
67 to 61 P61/INT1 to
P67/INT7
J
General-purpose input ports
A software pull-up resistor is provided.
Also serve as an external interrupt input (INT1 to INT7).
These ports are a hysteresis input type.
4
3
6
P70/BZ1
P71/UCK
G
K
N-ch open-drain I/O port
Also serves as a buzzer output.
5
N-ch open-drain I/O port
Also serves as a UART clock I/O (UCK) switchable to
CMOS.
2
4
P72/UO
K
N-ch open-drain I/O port
Also serves as a UART data output (UO) switchable to
CMOS.
1
3
2
P73/UI
G
K
N-ch open-drain I/O port
Also serves as a UART data input (UI).
80
P74/SCK
N-ch open-drain I/O port
Also serves as the clock I/O for the serial I/O (SCK)
switchable to CMOS.
79
78
1
P75/SO
P76/SI
K
N-ch open-drain I/O port
Also serves as the data output (SO) for the serial I/O
switchable to CMOS.
80
G
H
N-ch open-drain I/O port
Also serves as the data input (SI) for the serial I/O.
8 to 5
57,
10 to 7
59,
P80 to P83
P85,
N-ch open-drain output ports
58
60
P84
53
13, 56
75
55
15, 58
77
VCC
—
—
—
—
—
Power supply pin
VSS
Power supply (GND) pin
AVCC
AVR
AVSS
A/D converter power supply pin
A/D converter reference voltage input pin
76
78
77
79
A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1: FPT-80P-M11
*2: FPT-80P-M06
*3: MQP-80C-P01
10
MB89670/A Series
• External EPROM pins (MB89PV670A only)
Pin no.
Pin name
A15
I/O
Function
82
83
84
85
86
87
88
89
90
91
O
Address output pins
A12
A7
A6
A5
A4
A3
A2
A1
A0
93
94
95
O1
O2
O3
I
Data input pins
96
VSS
O
I
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
103
CE
O
ROM chip enable pin
Outputs “H” during standby.
104
105
A10
O
O
Address output pin
OE/VPP
ROM output enable pin
Outputs “L” at all times.
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
VCC
O
O
O
81
92
N.C.
—
Internally connected pins
Be sure to leave them open.
97
106
11
MB89670/A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Crystal or ceramic oscillation type
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
R
50 kΩ/5.0 V
• Hysteresis input
P-ch
N-ch
D
• CMOS output
• CMOS inout
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (except P22 and P23)
E
• CMOS output
• CMOS input
• The peripheral is a hysteresis input type.
R
P-ch
P-ch
N-ch
Peripheral
Port
• Pull-up resistor optional
(Continued)
12
MB89670/A Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
P-ch
N-ch
G
• N-ch open-drain output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
• N-ch open-drain output
H
I
N-ch
• N-ch open-drain output
• Analog input
P-ch
N-ch
Analog input
J
• Hysteresis input
• With software pull-up resistor
R
P-ch
Pull-up control
signal
K
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
13
MB89670/A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
14
MB89670/A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P677A
The MB89P677A is an OTPROM version of the MB89670/A series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
Normal operating mode
I/O
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000H
0080H
0100H
0200H
Register
RAM
0480H
8000H
8007H
External area
Option area
0000H
Option area
0007H
PROM
Program area
(EPROM)
FFFFH
7FFFH
15
MB89670/A Series
3. Programming to the EPROM
In EPROM mode, the MB89P677A functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH
while operating as a normal operating mode assign to 0007H to 7FFFH in EPROM mode).
Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each
corresponding option, see “7. Bit Map for PROM Options.”)
(3) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
ROM-80QF2-28DP-8L
FPT-80P-M11
FPT-80P-M06
ROM-80QF-28DP-8L2
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or
VCC and VSS can stabilize programming operations.
16
MB89670/A Series
7. PROM Option Bit Map
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Oscillation stabilization time
Vacancy
Vacancy
Vacancy
Vacancy
Reset pin
output
1: Yes
Power-on
reset
1: Yes
0: No
00: 24/FC
10: 217/FC
01: 214/FC
11: 218/FC
0000H
0001H
0002H
0003H
0004H
0005H
0006H
Readable
Readable
Readable
Readable
0: No
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P37
P36
P35
P34
P33
P32
P31
P30
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P47
P46
P45
P44
P43
P42
P41
P40
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
P74
P73
P72
P71
P70
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
P04 to P07 P00 to P03 P76
Pull-up
1: No
P75
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable
Readable
Readable
Readable
0: Yes
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
17
MB89670/A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32(Rectangle) ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Address
0000H
Normal operating mode
I/O
Corresponding address on the EPROM programmer
0000H
0080H
Not available
RAM
0480H
4000H
External area
4000H
8000H
8007H
8000H
*
*
8007H
PROM
48 KB
EPROM
48 KB
FFFFH
FFFFH
*: Note that for the MB89P677A this area comprise an option setting area.
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 4000H to FFFFH.
(3) Program to 4000H to FFFFH with the EPROM programmer.
18
MB89670/A Series
■ BLOCK DIAGRAM
1. MB89673
X0
X1
Time-base timer
Oscillator
Clock controller
CMOS I/O port
16-bit up/down counter
Reset circuit
(WDT)
RST
P37/UDA2
P36/UDB2
P35/UDZ2
8-bit up/down
counter
RAM
P34/UDA1
P33/UDB1
P32/UDZ1
8-bit up/down
counter
F2MC-8L
CPU
P47/EC
16-bit timer/counter
ROM
8/16-bit timer
8-bit timer
P46/TCO2
CMOS I/O port
P45/TCO1
P44/TCI
8
P00/AD0 to
P07/AD7
8-bit timer
8
2-channel 8-bit
PWM timer
P10/A08 to
P17/A15
P43/PWM11
MOD0
MOD1
8-bit timer #2
8-bit timer #1
External bus
interface
P42/PWM10/BZ2
P41/PWM01
P40/PWM00
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
P31/PWM21
P30/PWM20
8-bit PWM timer #3
CMOS output port
P76/SI
P75/SO
P74/SCK
8-bit serial
UART
6
N-ch open-drain
output port
P80 to P85
8
P50/AN0 to
P57/AN7
8
P73/UI
P72/UO
P71/UCK
10-bit A/D converter
AVR
AVCC
AVSS
Buzzer output
P70/BZ1
Input port
N-ch open-drain I/O port
8
8
P60/INT0/ADST to
P67/INT7
External interrupt
19
MB89670/A Series
2. MB89677A/89P677A/89PV670A
Time-base timer
X0
X1
Oscillator
CMOS I/O port
Clock controller
16-bit up/down counter
Reset circuit
(WDT)
RST
P37/UDA2
P36/UDB2
P35/UDZ2
8-bit up/down
counter
P34/UDA1
P33/UDB1
P32/UDZ1
RAM
8-bit up/down
counter
F2MC-8L
CPU
P47/EC
16-bit timer/counter
8/16-bit timer
8-bit timer
ROM
P46/TCO2
P45/TCO1
P44/TCI
8-bit timer
CMOS I/O port
8
8
P00/AD0 to
P07/AD7
P30/PWM20
P31/PWM21
P41/PWM01
P43/PWM11
8-bit PWM timer #3
8-bit PWM timer #4
8-bit PWM timer #5
8-bit PWM timer #6
P10/A08 to
P17/A15
MOD0
MOD1
External bus
interface
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
2-channel 8-bit
PWM timer
P40/PWM00
P42/PWM10/BZ2
8-bit timer #1
8-bit timer #2
CMOS output port
6
8
N-ch open-drain
output port
P80 to P85
P76/SI
P75/SO
P74/SCK
8-bit serial
UART
8
P50/AN0 to
P57/AN7
10-bit AD converter
AVR
AVCC
AVSS
P73/UI
P72/UO
P71/UCK
Input port
P70/BZ1
Buzzer output
8
8
P60/INT0/ADST to
P67/INT7
External interrupt
N-ch open-drain I/O port
20
MB89670/A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89670/A series offer a memory space of 64 Kbytes for storing all of I/O, data,
and program areas. The I/O area is located at the lowest address. The data area is provided immediately above
the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables
of interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89670/A series is structured as illustrated below.
Memory Space
MB89673
MB89P677A
MB89677A
MB89PV670A
0000H
0080H
0000H
0080H
0000H
0080H
I/O
I/O
RAM
I/O
RAM
RAM
0100H
0200H
0100H
0200H
0100H
0200H
Register
Register
Register
0480H
4000H
0480H
External area
External area
External area
8000H
8007H
8000H
8007H
8000H
8007H
Option PROM (One-time
PROM product)*
*
*
Programmable
ROM
Programmable
ROM
E000H
FFFFH
ROM
FFFFH
FFFFH
*: Since addresses 8000H to 8006H for the MB89P677A comprise an option
area, do not use this area for the other products in this series.
21
MB89670/A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
22
MB89670/A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
23
MB89670/A Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89677A. On the MB89673, there are 16
banks in internal RAM. The remaining 16 banks can be extended externally by allocating an external RAM to
addresses 0180H to 01FFH using an external circuit. The bank currently in use is indicated by the register bank
pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
24
MB89670/A Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Initial value
Port 0 data register
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X X X X 0 1 B
DDR0
Port 0 data direction register
Port 1 data register
(R/W)
(W)
PDR1
DDR1
Port 1 data direction register
Port 2 data register
(R/W)
(W)
PDR2
BCTR
External bus pin control register
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
SYCC
STBC
WDTE
TBCR
System clock control register
Standby control register
Watchdog timer control register
Time-base timer control register
Vacancy
X – – M MX 0 0 B
0 0 0 1 X X X X B
X X X X X X X X B
0 0 X X X 0 0 0 B
(R/W)
(W)
PDR3
DDR3
PDR4
DDR4
PDR5
PDR6
PPCR
PDR7
PDR8
BUZR
CNTR
COMP
TMCR
TCHR
TCLR
Port 3 data register
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
1 1 1 1 1 1 1 1 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X 1 1 1 1 1 1 1 B
0 0 1 1 1 1 1 1 B
X X X X X 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
Port 3 data direction register
Port 4 data register
(R/W)
(W)
Port 4 data direction register
Port 5 data register
(R/W)
(R)
Port 6 data register
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Port 6 pull-up control register
Port 7 data register
Port 8 data/port 7 swiching register
Buzzer control register
PWM control register #3
PWM compare register #3
16-bit timer control register
16-bit timer count register H
16-bit timer count register L
Vacancy
(R/W)
(R/W)
SMR
SDR
Serial mode register
0 0 0 0 0 0 0 0 B
X X X X X X X X B
Serial data register
Vacancy
Vacancy
–: Unused, X: Undefined, M: Set using the mask option
(Continued)
25
MB89670/A Series
Address
20H
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
Register name
ADC1
Register description
A/D converter control register 1
A/D converter control register 2
A/D converter data register H
A/D converter data register L
Timer 2 control register
Timer 1 control register
Timer 2 data register
Initial value
0 0 0 0 0 0 0 0 B
X 0 0 0 0 0 0 1 B
– – – – – – X X B
X X X X X X X X B
X 0 0 0 X X X 0 B
X 0 0 0 X X X 0 B
X X X X X X X X B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X 0 0 0 0 0 B
X X X X X X X X B
X X X X X X X X B
21H
ADC2
22H
ADCH
23H
ADCL
24H
T2CR
25H
T1CR
26H
T2DR
27H
T1DR
Timer 1 data register
28H
CNTR1
CNTR2
CNTR3
COMR2
COMR1
PWM timer control register 1
PWM timer control register 2
PWM timer control register 3
PWM timer compare register 2
PWM timer compare register 1
Vacancy
29H
2AH
2BH
2CH
2DH
2EH
2FH
(W)
Vacancy
Vacancy
(R)
(W)
UDCR1
RCR1
Up/down counter register 1
Reload compare register1
X X X X X X X X B
X X X X X X X X B
30H
31H
(R)
(W)
UDCR2
RCR2
Up/down counter register 2
Reload compare register2
X X X X X X X X B
X X X X X X X X B
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
CCRA1
CCRA2
CCRB1
CCRB2
CSR1
CSR2
EIC1
Counter control register A1
Counter control register A2
Counter control register B1
Counter control register B2
Counter status register 1
Counter status register 2
External interrupt 1 control register 1
External interrupt 1 control register 2
External interrupt 2 enable register
External interrupt 2 flag register
Vacancy
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X X 0 0 0 0 B
EIC2
EIE2
EIF2
Vacancy
Vacancy
Vacancy
–: Unused, X: Undefined, M: Set using the mask option
(Continued)
26
MB89670/A Series
(Continued)
Address
40H
Read/write
(R/W)
Register name
USMR
Register description
Initial value
UART mode register
UART control register
UART status register
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 1 X X X B
41H
(R/W)
USCR
42H
(R/W)
USTR
(R)
(W)
RXDR
TXDR
UART receiver data register
UART transmitter data register
X X X X X X X X B
X X X X X X X X B
43H
44H
45H
Vacancy
(R/W)
RRDR
Baud rate generator reload data register
Vacancy
X X X X X X X X B
46H
47H
Vacancy
48H*
49H*
4AH*
4BH*
4CH*
4DH*
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
CNTR #4
COMP #4
CNTR #5
COMP #5
CNTR #6
COMP #6
PWM timer control register #4
PWM timer compare register #4
PWM timer control register #5
PWM timer compare register #5
PWM timer control register #6
PWM timer compare register #6
0 X 0 0 0 0 0 0 B
X X X X X X X X B
0 X 0 0 0 0 0 0 B
X X X X X X X X B
0 X 0 0 0 0 0 0 B
X X X X X X X X B
4E to
7AH
Vacancy
7BH
7CH
7DH
7EH
7FH
Vacancy
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
1 1 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
–: Unused, X: Undefined, M: Set using the mask option
* : For the MB89673, these are vacancies.
Note: Do not use vacancies.
27
MB89670/A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
VSS – 0.3
VSS – 0.3
VSS + 7.0
VCC + 0.3
V
V
Power supply voltage
*
AVCC
A/D converter reference input
voltage
AVR must not exceed
AVCC + 0.3 V.
AVR
VSS – 0.3
VCC + 0.3
V
Input voltage
VI
VSS – 0.3
VSS – 0.3
VSS – 0.3
VCC + 0.3
VCC + 0.3
VSS + 7.0
V
V
V
VO1
VO2
Except P80 to P85
P80 to P85
Output voltage
“L” level maximum output
current
IOL
—
—
20
4
mA
mA
Average value (operating
current × operating rate)
IOLAV1
“L” level average output current
Average value (operating
IOLAV2
—
8
mA current × operating rate)
P80 to P85
“L” level total maximum output
current
∑IOL
—
—
—
—
—
—
100
40
mA
“L” level total average output
current
Average value (operating
mA
∑IOLAV
IOH
current × operating rate)
“H” level maximum output
current
–20
–4
mA
Average value (operating
mA
“H” level average output current
IOHAV
∑IOH
∑IOHAV
current × operating rate)
“H” level total maximum output
current
–50
–20
mA
“H” level total average output
current
Average value (operating
mA
current × operating rate)
Power consumption
Operating temperature
Storage temperature
PD
—
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
* : Use AVCC and VCC set at the same voltage.
Take care so that AVR does not exceed AVCC + 0.3 V and AVCC does not exceed VCC, such as when power is
turned on.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func-
tional operation should be restricted to the conditions as detailed in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
28
MB89670/A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Normal operation assurance range
MB89673/677A
2.2*
6.0
V
Power supply voltage
VCC
Normal operation assurance range
MB89PV670A/P677A
2.7*
1.5
6.0
6.0
V
V
Retains the RAM state in stop mode
A/D converter reference input
voltage
AVR
TA
0.0
AVCC
+85
V
Operating temperature
–40
°C
* : These values vary with the operating frequency, and analog assurance range. See Figure 1 and “5. A/D Converter
Electrical Characteristics.”
6
5
A/D converter accuracy assured in the
Operation assurance range
VCC = AVCC = 3.5 V to 6.0 V range.
4
3
2
1
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Clock operating frequency (MHz)
4.0 2.0
0.8
0.4
Minimum execution time (µs)
Note: The shaded area is assured only for the MB89673/677A.
Figure 1 Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an minimum execution time of 4/FC.
Since the operating voltage range is dependent on the minimum execution time, see minimum execution time
if the operating speed is switched using a gear.
29
MB89670/A Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
P32 to P37,
P00 to P07, P10 to P17,
P30 to P37, P40 to P47
VCC + 0.3
P44, and P47
are port input.
P32 to P37,
P44, and P47
are peripheral
input.
VIH
0.7 VCC
V
V
V
“H” level input voltage
RST, MOD0, MOD1,
P32 to P37, P44, P47,
P60 to P67, P70 to P76
VCC + 0.3
0.3 VCC
VIHS
VIL
0.8 VCC
P32 to P37,
P44, and P47
are port input.
P32 to P37,
P44, and P47
are peripheral
input.
—
P00 to P07, P10 to P17,
P30 to P37, P40 to P47
VSS − 0.3
“L” level input voltage
RST, MOD0, MOD1,
P32 to P37, P44, P47,
P60 to P67, P70 to P76
VSS − 0.3
VSS − 0.3
4.0
VILS
VD
0.2 VCC
VSS + 6.0
V
V
V
Open-drain output
pin application voltage
P80 to P85
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P71, P72,
P74, P75
“H” level output
voltage
VOH
IOH = –2.0 mA
IOL = 4.0 mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P70 to P76
VOL1
0.4
V
“L” level output
voltage
VOL2
VOL3
P80 to P85
RST
IOL = 10 mA
IOL = 4.0 mA
0.5
0.4
V
V
—
—
—
—
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, P70 to P76,
MOD0, MOD1
Input leakage current
(Hi-z output leakage
current)
ILI1
0.0 V < VI < VCC
±5
µA
Without pull-
up resistor
0.0 V < VI < VCC
VI = 0.0 V
ILI2
P80 to P85
—
—
±1
µA
kΩ
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P60 to P67, P70 to P76,
RST
With pull-up
resistor
Pull-up resistance
RPULL
25
50
100
(Continued)
30
MB89670/A Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
FC = 10 MHz
VCC = 5.0 V
tinst*2 = 0.4 µs
ICC1
—
12
20
mA
MB89673
FC = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
MB89677A
—
—
—
1
1.5
3
2
2.5
7
mA
mA
mA
ICC2
MB89PV670A
MB89P677A
FC = 10 MHz
VCC = 5.0 V
tinst*2 = 0.4 µs
FC = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
VCC
ICCS1
ICCS2
ICCH
Power supply
current*1
—
—
—
1
—
6
1.5
1
mA
mA
mA
VCC = 3.0 V
TA = +25°C
Stop mode
FC = 10 MHz
When A/D
IA
8
converter starts
AVCC
FC = 10 MHz
TA = +25°C
IAH
—
—
—
1
µA
When A/D
converter stops
Other than AVCC,
AVSS, VCC, and VSS
Input capacitance CIN
f = 1 MHz
10
—
pF
*1: The measurement conditions of the power supply current are as follows: the external clock and open output pins.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
31
MB89670/A Series
4. AC Characteristics
(1) Reset Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min. Max.
Symbol Condition
Unit
Remarks
Power supply rising time
Power supply cut-off time
tR
—
1
50
—
ms
ms
Power-on reset function only
Due to repeated operations
—
tOFF
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tR
tOFF
2.0 V
0.2 V
0.2 V
0.2 V
VCC
32
MB89670/A Series
(3) Clock Timing
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit
Remarks
Min.
1
Max.
10
Clock frequency
Clock cycle time
FC
X0, X1
X0, X1
MHz
ns
tXCYL
100
1000
PWH
PWL
—
Input clock pulse width
X0
X0
20
—
—
ns
ns
External clock
External clock
Input clock rising/falling
time
tCR
tCF
10
X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal
or
ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
FC
Open
C1
C2
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
Instruction cycle
(minimum execution time)
(4/FC) tinst = 0.4 µs when operating at
FC = 10 MHz
tinst
4/FC, 8/FC, 16/FC, 64/FC
µs
33
MB89670/A Series
(5) Recommended Resonator Manufacturers
Sample Application of Piezoelectric Resonator (FAR series)
X 0
X 1
F A R *
C 1
C 2
*: Fujitsu Acoustic Resonator
C1 = C2 = 20 pF±8 pF (built-in FAR)
Initial deviation of
FAR frequency
(TA = +25°C)
Temperature characteristics of
FAR frequency
FAR part number
(built-in capacitor type)
Frequency
(TA = –20°C to +60°C)
FAR-C4CB-08000-M02
FAR-C4CB-10000-M02
8.00 MHz
±0.5%
±0.5%
±0.5%
±0.5%
10.00 MHz
Inquiry: FUJITSU LIMITED
34
MB89670/A Series
Sample Application of Ceramic Resonator
X 0
X 1
*
C 1
C 2
Resonator manufacturer*
Kyocera Corporation
Resonator
Frequency
7.68 MHz
8.0 MHz
C1 (pF)
33
C2 (pF)
33
R (kΩ)
—
KBR-7.68MWS
KBR-8.0MWS
CSA8.00MTZ
33
33
—
Murata Mfg. Co., Ltd.
8.0 MHz
30
30
—
Inquiry: Kyocera Corporation
• AVX Corporation
North American Sales Headquarters: TEL 1-803-448-9411
• AVX Limited
European Sales Headquarters: TEL 44-1252-770000
• AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL 852-363-3303
Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
35
MB89670/A Series
(6) Clock Output Timing
(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Parameter
Min.
Max.
—
Cycle time
CLK ↑ → CLK ↓
tCYC
tCHCL
CLK
CLK
1/2 tinst*
µs
µs
—
1/4 tinst – 0.07
1/4 tinst
* : For information on tinst, see “(4) Instruction Cycle.”
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
36
MB89670/A Series
(7) Bus Read Timing
Parameter
(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Min.
1/4 tinst* – 0.06
1/2 tinst *– 0.02
—
Max.
—
RD, A15 to 08,
AD7 to 0
Valid address → RD
↓ time
tAVRL
tRLRH
tAVDV
µs
RD pulse width
RD
—
µs
Valid address → Data
read time
AD7 to 0,
A15 to 08
1/2 tinst *
µs Wait
RD, AD7 to 0
AD7 to 0, RD
RD, ALE
1/2 t
inst *– 0.08
—
RD ↓ → Data read time tRLDV
RD ↑ → Data hold time tRHDX
—
0
µs No wait
ns
µs
µs
µs
ns
ns
1/4 tinst* – 0.04
RD ↑ → ALE ↑ time
RD ↑ → Address loss time
RD ↓ → CLK ↑ time
CLK ↓ → RD ↑ time
RD ↓ → BUFC ↓ time
tRHLH
tRHAX
tRLCH
tCLRH
tRLBL
—
—
RD, A15 to 08
RD, CLK
1/4 t
inst* – 0.04
—
1/4 tinst* – 0.04
—
RD, CLK
0
—
RD, BUFC
–5
—
A15 to 08,
AD7 to 0,
BUFC
BUFC ↑ → Valid
address time
tBHAV
5
—
ns
* : For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
tRHLH
ALE
0.8 V
0.7 VCC
0.7 VCC
0.3 VCC
2.4 V
2.4 V
AD
0.8 V
0.8 V
0.3 VCC
tAVDV
tRHDX
2.4 V
2.4 V
2.4 V
0.8 V
A
tRLCH
tCLRH
0.8 V
0.8 V
tAVRL
tRLDV
tRLRH
tRHAX
2.4 V
RD
0.8 V
tRLBL
tBHAV
2.4 V
BUFC
0.8 V
37
MB89670/A Series
(8) Bus Write Timing
(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Parameter
Min.
Max.
AD7 to 0, ALE,
A15 to 08
Valid address → ALE
↓ time
1/4 tinst* 2 – 0.064
tAVLL
tLLAX
—
µs
AD7 to 0, ALE,
A15 to 08
ALE ↓ time →
Address loss time
5*1
—
ns
Valid address → WR ↓ time
WR pulse width
1/4 tinst* 2 – 0.06
1/2 tinst* 2 – 0.02
1/2 tinst* 2 – 0.06
tAVWL
tWLWH
tDVWL
tWHAX
tWHDX
tWHLH
tWLCH
tCLWH
tLHLL
WR, ALE
WR
—
—
—
—
—
—
—
—
—
—
µs
µs
ns
µs
µs
µs
µs
ns
µs
µs
Writing data → WR ↑ time
WR ↑ → Address loss time
WR ↑ → Data hold time
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
CLK ↓ → WR ↑ time
ALE pulse width
AD7 to 0, WR
WR, A15 to 08
AD7 to 0, WR
WR, ALE
WR, CLK
WR, CLK
ALE
inst* 2 – 0.04
—
1/4 t
1/4 tinst* 2 – 0.04
1/4 tinst* – 0.04
1/4 tinst* 2 – 0.04
0
1/4 tinst* 2 – 0.035
1/4 tinst* 2 – 0.03
ALE ↓ → CLK ↑ time
tLLCH
ALE, CLK
*1: These characteristics are also applicable to the bus read timing.
*2: For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
ALE
0.8 V
tLHLL
tLLCH
tWHLH
2.4 V
0.8 V
0.8 V
tAVLL
tLLAX
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
AD
A
0.8 V
0.8 V
0.8 V
tWHDX
tDVWH
2.4 V
0.8 V
2.4 V
tCLWH
tWLCH
0.8 V
tAVWL
tWHAX
tWLWH
2.4 V
WR
0.8 V
38
MB89670/A Series
(9) Ready Input Timing
(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
tYVCH
tCHYX
Pin
Condition
Unit Remarks
Parameter
Min.
Max.
RDY valid → CLK
↑ time
RDY, CLK
RDY, CLK
60
—
ns
ns
*
*
—
CLK ↑ → RDY invalid
0
—
time
* : These characteristics are also applicable to the read cycle.
2.4 V
2.4 V
CLK
ALE
AD
A
Address
Data
WR
tYVCH tCHYX
RDY
tYVCH tCHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
39
MB89670/A Series
(10) Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
SCK
Condition
Unit Remarks
Parameter
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
tSCYC
Internal Shift Clock Mode
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI
External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SO
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI
40
MB89670/A Series
(11) Peripheral Input Timing
Parameter
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Min.
1 tinst*
1 tinst*
Max.
—
Peripheral input “H” pulse width 1 tILIH1
Peripheral input “L” pulse width 1 tIHIL1
TCI
TCI
EC,
µs
µs
—
—
Peripheral input “H” pulse width 2 tILIH2
Peripheral input “L” pulse width 2
2 tinst*
2 tinst*
—
—
µs
µs
INT0 to INT7
EC,
tIHIL2
INT0 to INT7
Peripheral input “H” pulse width 3 tILIH3
Peripheral input “L” pulse width 3 tIHIL3
Peripheral input “H” pulse width 3 tILIH3
Peripheral input “L” pulse width 3
ADST
ADST
ADST
ADST
64 tinst*
64 tinst*
64 tinst*
64 tinst*
—
—
—
—
µs
µs
µs
µs
A/D
mode
Sense
mode
tIHIL3
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
0.8 VCC
0.8 VCC
0.8 VCC
0.8 VCC
TCI
0.2 VCC
0.2 VCC
tIHIL2
tILIH2
0.8 VCC
EC
INT0 to INT7
0.2 VCC
0.2 VCC
tIHIL3
tILIH3
0.8 VCC
ADST
0.2 VCC
0.2 VCC
41
MB89670/A Series
(12) Up/down Counter Input Timing
(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit
Remarks
Parameter
Min.
2 tinst*
2 tinst*
2 tinst*
2 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AIN input “1” pulse width
AIN input “0” pulse width
BIN input “1” pulse width
BIN input “0” pulse width
AIN ↑ → BIN ↑ time
tAHL
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
tALL
tBHL
tBLL
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
tZHL
BIN ↑ → AIN ↓ time
P36, P37,
P33, P34
AIN ↓ → BIN ↓ time
—
BIN ↓ → AIN ↑ time
BIN ↑ → AIN ↑ time
AIN ↑ → BIN ↓ time
BIN ↓ → AIN ↓ time
AIN ↓ → BIN ↑ time
ZIN input “1” pulse width
ZIN input “0” pulse width
P32, P35
tZLL
* : For information on tinst, see “(4) Instruction Cycle.”
42
MB89670/A Series
tAHL
tALL
0.8 VCC
0.8 VCC
AIN
BIN
0.2 VCC
0.2 VCC
tAUBU
tBUAD
tADBD
tBDAU
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tBHL
tBLL
tBHL
tBLL
0.8 VCC
0.8 VCC
0.8 VCC
BIN
AIN
0.2 VCC
0.2 VCC
tBUAU
tAUBD
tBDAD
tADBU
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tAHL
tALL
0.8 VCC
0.8 VCC
tZHL
ZIN
tZLL
0.2 VCC
0.2 VCC
43
MB89670/A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min.
—
Max.
10
bit
Linearity error
—
—
±2.0
±1.5
±3.0
LSB
LSB
LSB
mV
—
—
Differential linearity error
Total error
—
—
—
—
AVCC =
AVR = VCC
Zero transition voltage
AN0 to AN7 AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
VOT
Full-scale transition
voltage
AN0 to AN7 AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB
VFST
mV
LSB
µs
Interchannel disparity
—
—
—
—
4
—
—
—
A/D mode conversion
time
At 10-MHz
oscillation
13.2
Analog port input current
Analog input voltage
Reference voltage
AN0 to AN7
AN0 to AN7
AVR
IAIN
—
0
—
—
—
10
µA
V
AVR
AVCC
0
V
Reference voltage
supply current
IR
AVR
—
200
µA AVR = 5.0 V
Precautions: • The smaller | AVR – AVSS |, the greater the error would become relatively.
• The output impedance of the external circuit for the analog input must satisfy the following conditions:
Output impedance of the external circuit < Approx. 10 kΩ
If the output impedance of the external circuit is too high, an analog voltage sampling time might be
insufficient (sampling time = 6 µs at 10 MHz oscillation).
An analog input equivalent circuit is shown below.
Sample hold circuit
R ≤ 10 kΩ is
recommended.
.
C = 60 pF
.
AN
Comparator
.
R = 3 kΩ
.
Analog channel selector
Close for approx. 15 instruction cycles
after activating A/D conversion.
If R > 10 kΩ, it is recommended
to connect an external capacitor
of approx. 0.1 µF.
Microcontroller’s internal circuit
Since the A/D converter contains sample hold circuit, the level of the analog input pin might not stabilize within the
sampling period after A/D activation, resulting in inaccurate A/D conversion values, if the input impedance to the
analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin.
It is recommended to keep the input impedance to the analog pin not exceed 10 kΩ. If it exceeds 10 kΩ, it is
recommended to connect a capacitor of approx. 0.1 µF for the analog input pin.
ExceptforthesamplingperiodafterA/Dactivation, theinputleakagecurrentoftheanaloginputpinislessthan10µA.
44
MB89670/A Series
(1) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise.
Theoreticall I/O characteristics
VFST
Total error
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
value
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
VNT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VFST – VOT
VNT – {1 LSB × N + 0.5 LSB}
1 LSB =
(V)
Total error of digital output N
1022
1 LSB
(Continued)
45
MB89670/A Series
(Continued)
Zero transition error
Full-scale transition error
004
Theoretical value
Actual conversion
value
3FF
3FE
3FD
3FC
Actual conversion
value
003
002
VFST (Actual
measured value)
Theoretical
value
Actual conversion
value
Actual conversion
value
001
VOT (Actual measured value)
Analog input
AVSS
AVR
Analog input
Linearity error
Differential linearity error
3FF
3FE
3FD
Theoretical value
Actual conversion
value
N + 1
{1 LSB × N + VOT}
Actual conversion
value
V(N + 1)T
VFST (Actual
measured
value)
N
VNT
004
003
002
001
N – 1
N – 2
VNT
Actual conversion
value
Actual conversion
value
Theoretical value
VOT (Actual measured value)
Analog input
AVSS
AVR
AVSS
AVR
– 1
Analog input
VNT – {1 LSB × N + VOT}
V(N+1)T – VNT
Linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB
1 LSB
46
MB89670/A Series
■ EXAMPLE CHARACTERISTICS
(2) “H” Level Output Voltage
(1) “L” Level Output Voltage
VCC – VOH vs. IOH
VOL vs. IOL
VOL (V)
VCC – VOH (V)
1.0
VCC = 2.5 V
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
VCC = 3.0 V
0.5
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.3
0.2
0.1
0.0
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
IOH (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
TA = +25°C
VIN vs. VCC
VIN (V)
4.5
5.0
4.0
VIHS
TA = +25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3.0
2.5
2.0
VILS
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
0
1
2
3
4
5
6
7
VCC (V)
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
47
MB89670/A Series
(5) Power Supply Current (External Clock)
ICCS1 vs. VCC, ICCS2 vs. VCC
I
CC1 vs. VCC, ICC2 vs. VCC
I
CC (mA)
ICCS (mA)
25
25
20
15
10
TA = +25°C
FC = 10 MHz
External clock
T
F
A
C
= +25°C
= 10 MHz
External clock
I
CC1 (Divide by 4)
20
15
10
ICCS1 (Divide by 4)
ICCS2 (Divide by 64)
I
CC2 (Divide by 64)
5
0
5
0
2
3
4
5
6
7
2
3
4
5
6
7
V
CC (V)
VCC (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
500
100
50
10
1
2
3
4
5
6
VCC (V)
48
MB89670/A Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
49
MB89670/A Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
CCR
RP
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
50
MB89670/A Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
–
–
–
–
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
51
MB89670/A Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
A
C
←
C ← A
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
52
MB89670/A Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
53
MB89670/A Series
■ INSTRUCTION MAP
54
MB89670/A Series
■ MASK OPTIONS
MB89673
MB89677A
Part number
MB89P677A
MB89PV670A
No.
Specify when
ordering masking
Set with EPROM
programmer
Specifying procedure
Setting not possible
Pull-up resistors
P10 to P17,
1
Selectable by pin
Selectable by pin
P30 to P37, P40 to P47,
P70 to P76
Fixed to without
pull-up resistor
Pull-up resistors
P00 to P03
Selectable in 4-pin
unit
2
3
Selectable by pin
Selectable by pin
Pull-up resistors
P04 to P07
Selectable in 4-pin
unit
Power-on reset
Fixed to with
power-on reset
4
5
6
With power-on reset
Without power-on reset
Selectable
Selectable
Selectable
Selectable
Selectable
Selectable
Oscillation stabilization time
selection (at 10 MHz)
Approx. 218/FC (about 26.2 ms)
Fixed to Approx.
218/FC (Approx.
26.2 ms)
Approx. 217/FC (about 13.1 ms)
Approx. 214/FC (about 1.6 ms)
Approx. 24/FC (about 0 ms)
FC: Clock frequency
Reset pin output
With reset output
Without reset output
Fixed to with reset
output
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89673PF
MB89677APF
MB89P677APF
80-pin Plastic QFP
(FPT-80P-M06)
MB89673PFM
MB89677APFM
MB89P677APFM
80-pin Plastic QFP
(FPT-80P-M11)
80-pin Ceramic MQFP
(MQP-80C-P01)
MB89P670ACF
55
MB89670/A Series
■ PACKAGE DIMENSIONS
80-pin Plastic QFP
(FPT-80P-M11)
16.00±0.20(.630±.008)SQ
1.50+–00..1200
.059+–..000048
60
61
41
40
14.00±0.10(.551±.004)SQ
15.00
(.591)
NOM
12.35
(.486)
REF
1 PIN INDEX
80
21
1
Details of "A" part
0.10±0.10
LEAD No.
"A"
0.127–+00..0025
.005–+..000012
20
(STAND OFF)
0.65(.0256)TYP
0.30±0.10
(.012±.004)
M
(.004±.004)
0.13(.005)
0.50±0.20
(.020±.008)
0.10(.004)
0
10°
C
1994 FUJITSU LIMITED F80016S-1C-2
Dimensions in mm (inches)
56
MB89670/A Series
80-pin Plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
0.05(.002)MIN
(STAND OFF)
64
41
65
40
12.00(.472)
REF
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
1
24
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.16(.006)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
0.58(.023)MAX
18.40(.724)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
57
MB89670/A Series
80-pin Ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20–+00..2400
4.50(.177)
TYP
.047 –+..000186
0.80±0.25
(.0315±.010)
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
14.22(.560)
TYP
0.30(.012)
24.70(.972)
TYP
TYP
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20–+00..2400
.047–+..000186
1.50(.059)
TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
58
MB89670/A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 1015, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
All Rights Reserved.
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Com-
plete information sufficient for construction purposes is not nec-
essarily given.
Tel: (06103) 690-0
Fax: (06103) 690-122
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu as-
sumes no responsibility for inaccuracies.
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
The information contained in this document does not convey any
license under the copyrights, patent rights or trademarks claimed
and owned by Fujitsu.
#06-04 to #06-07
Singapore 189554
Tel: 336-1600
Fujitsu reserves the right to change products or specifications
without notice.
Fax: 336-1609
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear con-
trol systems or medical equipments for life support.
F9602
FUJITSU LIMITED Printed in Japan
59
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