MB89P677APMC1 [FUJITSU]
Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 10MHz, CMOS, PQFP80, 14 X 14 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-80;
| 型号： | MB89P677APMC1 |
| 厂家： | 
FUJITSU |
| 描述： | Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 10MHz, CMOS, PQFP80, 14 X 14 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-80 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总56页 (文件大小：1656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12537-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89670AR Series
MB89673AR/675AR/677AR/P677A/PV670A
■ OUTLINE
The MB89670AR series has been developed as a line of proprietary 8-bit, single-chip microcontrollers.
In addition to the F2MC*-8L family CPU core which can operate at low voltage but at high speed, the
microcontrollers contain pheripheral functions such as timers, a serial interface, a 10-bit A/D converter, a UART,
an 8/16-bit up/down counter/timer, and an external interrupt.
The MB89670AR series is applicable to a wide range of applications from consumer appliances to industrial
equipment, including portable devices.
*: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• High-speed processing at low voltage
• Minimum execution time: 0.4 µs@3.5 V, 0.8 µs@2.7 V, 2.0 µs@2.2 V
• I/O ports: max. 69 channels
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©1998-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.10
MB89670AR Series
(Continued)
• Timers: 12 channels
8-bit PWM timer: 6 channels (also usable as a reload timer or 8-bit PWM timer)
16-bit timer/counter
21-bit timebase timer
8/16-bit timer (8 bits × 2 channels or 16 bits)
8/16-bit up/down counter/timer (8 bits × 2 channels or 16 bits)
• 2-channel serial interfaces
8-bit synchronized serial: 1 channel (Switchable transfer direction allows communication with various
equipment.)
UART: 1 channel (internal full-duplex double buffer)
• External interrupts: 8 channels
Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Buzzer output
• 10-bit A/D converter
Input: 8 channels
10-bit resolution
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
• Bus interface function
Including hold and ready functions
2
DS07-12537-2E
MB89670AR Series
■ PRODUCT LINEUP
Part number
MB89673AR
MB89675AR
MB89677AR
MB89P677A
MB89PV670A
Item
Classification
One-time PROM
product
(for development) (for development)
Piggyback/
evaluation product
Mass-produced products
(mask ROM products)
ROM size
RAM size
8 K × 8 bits
(internal mask
ROM)
16 K × 8 bits
(internal mask
ROM)
32 K × 8 bits
(internal mask ROM)
48 K × 8 bits
(external ROM)
384 × 8 bits
512 × 8 bits
1 K × 8 bits
CPU
functions
The number of instructions:
Instruction bit length:
Instruction length:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Data bit length:
Minimum execution time:
Interrupt processing time:
0.4 µs@10 MHz to 6.4 µs@10 MHz
3.6 µs@10 MHz to 57.6 µs@10 MHz
Ports
Output ports (N-channel open-drain):
Output ports (CMOS):
I/O ports (N-channel open-drain):
I/O ports (CMOS):
Input ports:
Total:
14 (12 also serve as peripherals.)
8 (All also serve as peripherals.)
7 (All also serve as peripherals.)
32 (All also serve as peripherals.)
8 (All also serve as peripherals.)
69
Option
Set with EPROM
programmer
Setting not
possible
Specify when ordering masking
Timebase
timer
21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms@10 MHz)
8/16-bit
up/down
8 bits × 2 channels or 16 bits × 1 channel
Timer operation
counter/timer
Up/down counter operation
Phase difference counting (double mode, quadruple mode)
16-bit
timer/counter
16-bit timer operation
16-bit event counter operation (edge selectable)
8/16-bit
timer/counter
8 bits × 2 channels or 16 bits × 1 channel
Reload timer operation (toggled output capable)
Event counter operation
8-bit PWM
timer 1, 2
8 bits × 2 channels reload timer operation (toggled output capable)
8 bits × 2 channels PWM operation (four frequencies fixed)
8 bits × 1 channel PPG operation (variable frequency)
Capable of output switching between 2 channels in any mode
8-bit PWM
timer 3, 4, 5, 6
8-bit reload timer operation (toggled output capable)
8-bit PWM operation (four frequencies fixed)
Capable of output switching between 2 channels in any mode
8-bit serial I/O
8 bits
LSB first/MSB first selectable
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks)
(Continued)
DS07-12537-2E
3
MB89670AR Series
(Continued)
Part number
MB89673AR
MB89675AR
MB89677AR
MB89P677A
MB89PV670A
Item
UART
Variable data length (7 or 8 bits)
On-chip baud rate generator
Error detection function
On-chip full-duplex double buffer
NRZ transfer format
CLK synchrnous/asynchronous data transfer capable
10-bit A/D
converter
10 bits × 8 channels
External
interrupt
8 channels (Rising edge/falling edge)
Power supply
voltage*
2.2 V to 6.0 V
2.7 V to 6.0 V
EPROM for
use
—
MBM27C512-20TV
* : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89673AR
MB89675AR
MB89677AR
Package
MB89P677A
MB89PV670A
FPT-80P-M06
FPT-80P-M22
MQP-80C-P01
×
×*
×
×
: Available
× : Not available
* : Lead pitch converter sockets are available
Note: For more information about each package, see section “■ Package Dimensions”.
4
DS07-12537-2E
MB89670AR Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, make sure of its differences from the product that will actually
be used. Take particular care on the following points:
• OntheMB89P677A, theprogramareastartsfromaddress8007H, whileontheMB89677ARandMB89PV670A
starts from 8000H.
(On the MB89P677A, the option setting data can be read by reading the addresses “8000H” to “8006H”, while
on the MB89677AR and MB89PV670A, addresses 8000H to 8006H could also be used as a program ROM.
However, do not use these addresses in order to maintain compatibility of the MB89P677A.)
• The stack area, etc., is set at the upper limit of the RAM.
• The external area is used.
2. Current Consumption
• InthecaseoftheMB89PV670A,addthecurrentconsumedbytheEPROMwhichisconnectedtothetopsocket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics”.)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options”.
Take particular care on the following point:
• Options are fixed on the MB89PV670A.
4. Differences between the MB89670/670A and MB89670AR Series
• Memory access area
Memory access area of both the MB89677A and MB89677AR is the same.
The access are of the MB89673 is different from that of the MB89673AR respectively in the external bus mode.
See below.
Memory area
Address
MB89673
MB89673AR
0000H to 007FH
0080H to 01FFH
0200H to 027FH
0280H to BFFFH
C000H to DFFFH
E000H to FFFFH
I/O area
I/O area
RAM area
RAM area
Access prohibited
External area
Access prohibited
ROM area
External area
ROM area
DS07-12537-2E
5
MB89670AR Series
• Electrical specifications/characteristics
Electrical specifications/characteristics of the MB89673AR/677AR are the same with that of the MB89670/
670A series.
• The other specifications
Both the MB89673AR/677AR and the MB89670/670A series are the same.
6
DS07-12537-2E
MB89670AR Series
■ PIN ASSIGNMENT
(Top view)
P73/UI
P72/UO
P71/UCK
P70/BZ1
P83
P82
P81
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P66/INT6
P67/INT7
P84
P85
VSS
P40/PWM00
P41/PWM01
VCC
P42/PWM10/BZ2
P43/PWM11
P44/TCI
P45/TCO1
P46/TCO2
P47/EC
P30/PWM20
P31/PWM21
P32/UDZ1
P33/UDB1
P34/UDA1
P35/UDZ2
P80
MOD0
MOD1
X0
X1
VSS
9
10
11
12
13
14
15
16
17
18
19
20
RST
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
(FPT-80P-M22)
DS07-12537-2E
7
MB89670AR Series
(Top view)
P75/SO
P74/SCK
P73/UI
P72/UO
P71/UCK
P70/BZ1
P83
P82
P81
P80
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P64/INT4
P65/INT5
P66/INT6
P67/INT7
P84
P85
101
102
103
104
105
106
107
108
109
93
92
91
90
89
88
87
86
85
VSS
P40/PWM00
P41/PWM01
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
MOD0
MOD1
X0
P42/PWM10/BZ2
P43/PWM11
P44/TCI
P45/TCO1
P46/TCO2
P47/EC
P30/PWM20
P31/PWM21
P32/UDZ1
P33/UDB1
P34/UDA1
P35/UDZ2
P36/UDB2
P37/UDA2
X1
VSS
RST
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
Each pin inside the dashed line
is for the MB89PV670A only.
(FPT-80P-M06)
(MQP-80C-P01)
• Pin assignment on package top (MB89PV670A only)
Pin no.
81
Pin name
N.C.
A15
A12
A7
Pin no.
89
Pin name
A2
Pin no.
97
Pin name
N.C.
O4
Pin no.
105
Pin name
OE/VPP
N.C.
A11
82
90
A1
98
106
83
91
A0
99
O5
107
84
92
N.C.
O1
100
101
102
103
104
O6
108
A9
85
A6
93
O7
109
A8
86
A5
94
O2
O8
110
A13
87
A4
95
O3
CE
111
A14
88
A3
96
VSS
A10
112
VCC
N.C.: Internally connected. Do not use.
8
DS07-12537-2E
MB89670AR Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
QFP*2
LQFP*1
MQFP*3
11
12
9
13
14
11
12
16
X0
X1
A
B
C
Clock oscillator pins
MOD0
MOD1
RST
Operating mode selection pins
Connect directly to VCC or VSS.
10
14
Reset I/O pin
This pin is of a N-ch open-drain output type with pull-up
resistor and a hysteresis input type.
“L” is output from this pin by an internal reset source.
The internal circuit is initialized by the input of “L”.
38 to 31
30 to 23
22
40 to 33
32 to 25
24
P00/AD0 to
P07/AD7
D
D
F
F
General-purpose I/O ports
When an external bus is used, these ports function as
multiplex pins of lower address output and data I/O.
P10/A08 to
P17/A15
General-purpose I/O ports
When an external bus is used, these ports function as
upper address output pins.
P20/BUFC
P21/HAK
General-purpose output port
When an external bus is used, this port can also be
used as a buffer control output by setting the BCTR.
21
23
General-purpose output port
When an external bus is used, this port can also be
used as a hold acknowledge output by setting the
BCTR.
20
19
18
17
16
15
22
21
20
19
18
17
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
D
D
F
F
F
F
General-purpose output port
When an external bus is used, this port can also be
used as a hold request input by setting the BCTR.
General-purpose output port
When an external bus is used, this port functions as a
ready input.
General-purpose output port
When an external bus is used, this port functions as a
clock output.
General-purpose output port
When an external bus is used, this port functions as a
write signal output.
General-purpose output port
When an external bus is used, this port functions as a
read signal output.
P27/ALE
General-purpose output port
When an external bus is used, this port functions as an
address latch signal output.
(Continued)
*1: FPT-80P-M22
*2: FPT-80P-M06
*3: MQP-80C-P01
DS07-12537-2E
9
MB89670AR Series
Pin no.
Circuit
type
QFP*2
Pin name
Function
General-purpose I/O port
Also serves as the PWM20 output for the 8-bit PWM
timer.
LQFP*1
MQFP*3
46
48
47
46
45
44
43
42
41
57
56
54
53
52
51
50
P30/PWM20
D
D
E
E
E
E
E
E
D
D
D
D
E
D
D
45
44
43
42
41
40
39
55
54
52
51
50
49
48
P31/PWM21
P32/UDZ1
P33/UDB1
P34/UDA1
P35/UDZ2
P36/UDB2
P37/UDA2
P40/PWM00
P41/PWM01
General-purpose I/O port
Also serves as the PWM21 output for the 8-bit PWM
timer.
General-purpose I/O port
Also serves as the Z-phase input for the 8/16-bit
up/down counter/timer.
General-purpose I/O port
Also serves as the B-phase input for the 8/16-bit
up/down counter/timer.
General-purpose I/O ports
Also serves as the A-phase input for the 8/16-bit
up/down counter/timer.
General-purpose I/O port
Also serves as the Z-phase input for the 8/16-bit
up/down counter/timer.
General-purpose I/O port
Also serves as the B-phase input for the 8/16-bit
up/down counter/timer.
General-purpose I/O port
Also serves as the A-phase input for the 8/16-bit
up/down counter/timer.
General-purpose I/O port
Also serves as the PWM00 output for the 8-bit PWM
timer.
General-purpose I/O port
Also serves as the PWM01 output for the 8-bit PWM
timer.
P42/PWM10/
BZ2
General-purpose I/O port
Also serves as the PWM10 and the BZ2 output for the
8-bit PWM timer.
P43/PWM11
P44/TCI
General-purpose I/O port
Also serves as the PWM11 output for the 8-bit PWM
timer.
General-purpose I/O port
Also serves as the TCI input for the 8/16-bit
timer/counter.
P45/TCO1
P46/TCO2
General-purpose I/O port
Also serves as the TCO1 output for the 8/16-bit
timer/counter.
General-purpose I/O port
Also serves as the TCO2 output for the 8/16-bit
timer/counter.
(Continued)
*1: FPT-80P-M22
*2: FPT-80P-M06
*3: MQP-80C-P01
10
DS07-12537-2E
MB89670AR Series
(Continued)
Pin no.
Circuit
type
QFP*2
Pin name
P47/EC
Function
LQFP*1
MQFP*3
47
49
E
General-purpose I/O port
Also serves as the input for the16-bit timer/counter.
The EC input is of a hysteresis input type.
74 to 67
66
76 to 69 P50/AN0 to
P57/AN7
I
N-ch open-drain output ports
Also serve as the analog inputs for the 10-bit A/D
converter.
68
P60/INT0/
ADST
J
General-purpose input port
The software pull-up resistor is provided.
Also serves as an external interrupt input (INT0) and an
10-bit A/D converter external start-up.
This port is of a hysteresis input type.
65 to 59
67 to 61 P61/INT1 to
P67/INT7
J
General-purpose input ports
A software pull-up resistor is provided.
Also serve as external interrupt inputs (INT1 to INT7).
These ports are of a hysteresis input type.
4
3
6
5
P70/BZ1
P71/UCK
G
K
N-ch open-drain I/O port
Also serves as a buzzer output.
N-ch open-drain I/O port
Also serves as a UART clock I/O (UCK), switchable to
CMOS.
2
4
P72/UO
K
N-ch open-drain I/O port
Also serves as a UART data output (UO), switchable to
CMOS.
1
3
2
P73/UI
G
K
N-ch open-drain I/O port
Also serves as a UART data input (UI).
80
P74/SCK
N-ch open-drain I/O port
Also serves as the clock I/O (SCK) for the 8-bit serial I/O,
switchable to CMOS.
79
78
1
P75/SO
P76/SI
K
N-ch open-drain I/O port
Also serves as the data output (SO) for the 8-bit serial
I/O, switchable to CMOS.
80
G
H
N-ch open-drain I/O port
Also serves as the data input (SI) for the 8-bit serial I/O.
8 to 5,
57,
10 to 7,
59,
P80 to P83,
P85,
N-ch open-drain output ports
58
60
P84
53
55
VCC
VSS
—
—
Power supply pin
13,
56
15,
58
Power supply (GND) pin
75
77
AVCC
—
A/D converter power supply pin
Use this pin at the same voltage as VCC.
76
77
78
79
AVR
AVSS
—
—
A/D converter reference voltage input pin
A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1: FPT-80P-M22
*2: FPT-80P-M06
*3: MQP-80C-P01
DS07-12537-2E
11
MB89670AR Series
• External EPROM pins (MB89PV670A only)
Pin no.
Pin name
A15
I/O
Function
82
83
84
85
86
87
88
89
90
91
O
Address output pins
A12
A7
A6
A5
A4
A3
A2
A1
A0
93
94
95
O1
O2
O3
I
Data input pins
96
VSS
O
I
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
103
CE
O
ROM chip enable pin
Outputs “H” during standby.
104
105
A10
O
O
Address output pin
OE/VPP
ROM output enable pin
Outputs “L” at all times.
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
VCC
O
O
O
Power supply pin for EPROM
81
92
N.C.
—
Internally connected pins
Be sure to leave them open.
97
106
12
DS07-12537-2E
MB89670AR Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Crystal or ceramic oscillation type
• Oscillation feedback resistor of approximately
X1
1 MΩ at 5.0 V
X0
Standby control signal
B
C
• Output pull-up resistor (P-ch) of approximately
50 kΩ at 5.0 V
• Hysteresis input
R
P-ch
N-ch
D
• CMOS output
• CMOS inout
R
• Pull-up resistor optional (except P22 and P23)
P-ch
P-ch
N-ch
E
• CMOS output
• CMOS input
• The peripheral is of a hysteresis input type.
• Pull-up resistor optional
R
P-ch
P-ch
N-ch
Peripheral
Port
(Continued)
13
DS07-12537-2E
MB89670AR Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
P-ch
N-ch
G
• N-ch open-drain output
• Hysteresis input
• Pull-up resistor optional
R
P-ch
P-ch
N-ch
H
I
• N-ch open-drain output
N-ch
• N-ch open-drain output
• Analog input
P-ch
N-ch
Analog input
J
• Hysteresis input
• With software pull-up resistor
R
P-ch
Pull-up control
signal
K
• CMOS output
• Hysteresis input
• Pull-up resistor optional
R
P-ch
P-ch
N-ch
14
DS07-12537-2E
MB89670AR Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
DS07-12537-2E
15
MB89670AR Series
■ PROGRAMMING TO THE PROM ON THE MB89P677A
The MB89P677A is an OTPROM version of the MB89670AR series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in the EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
Address
Single chip
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000H
I/O
0080H
0480H
RAM
External area
Not available
8000H
8007H
0000H
Option area
0007H
PROM
EPROM
32 KB
32 KB
FFFFH
7FFFH
16
DS07-12537-2E
MB89670AR Series
3. Programming to the PROM
In EPROM mode, the MB89P677A functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH
while operating as a single chip assign to 0007H to 7FFFH in the EPROM mode).
Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each
corresponding option, see “7. Setting OTPROM Options”.)
(3) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
Due to the nature of the blanked OTPROM microcomputer, bit programming test can’t be conducted as Fujitsu’s
shipping test. Therefore a programming yield of 100% cannot be assured at all times.
DS07-12537-2E
17
MB89670AR Series
6. Setting PROM Options
The programming procedure is the same as that for the PROM.
Options can be set by programming values at the addresses shown on the memory map. The relationship
between bits and options is shown on the following bit map:
• PROM option bit map
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Oscillation stabilization time
00: 24/FC 01: 214/FC
10: 217/FC 11: 218/FC
Bit 0
Vacancy
Vacancy
Vacancy
Vacancy
Reset pin Power-on
output
reset
1: Yes
0: No
0000H
Readable Readable Readable Readable 1: Yes
0: No
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0001H
0002H
0003H
0004H
0005H
0006H
P37
P36
P35
P34
P33
P32
P31
P30
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P47
P46
P45
P44
P43
P42
P41
P40
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable Readable Readable Readable Readable Readable Readable Readable
Vacancy
Vacancy
Vacancy
P74
Pull-up
P73
P72
P71
P70
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable Readable Readable 1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
P04 to P07 P00 to P03 P76
Pull-up
P75
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable Readable Readable Readable 1: No
0: Yes
Notes: • Each bit is set to “1” as the initialized value.
• Do not write “0” to the vacant bit.
The read value of the vacant bit is “1”, unless “0” is written to it.
18
DS07-12537-2E
MB89670AR Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Memory Space
Memory space in each mode is diagrammed below.
Address
0000H
Single chip
I/O
EPROM mode
(Corresponding address on the EPROM programmer)
0000H
0080H
Not available
RAM
0480H
4000H
External area
4000H
8000H
8007H
8000H
*
*
8007H
PROM
48 KB
EPROM
48 KB
FFFFH
FFFFH
*: Note: For the MB89P677A, this area is an option setting area.
3. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 4000H to FFFFH.
(3) Program to 4000H to FFFFH with the EPROM programmer.
DS07-12537-2E
19
MB89670AR Series
■ BLOCK DIAGRAM
• Block Diagram of MB89673AR /89675AR/89677AR/89P677A/89PV670A
Timebase timer
X0
X1
Oscillator
CMOS I/O port
Clock controller
16-bit up/down
counter/timer
Reset circuit
P37/UDA2
P36/UDB2
P35/UDZ2
RST
(WDT)
8-bit up/down
counter/timer
P34/UDA1
P33/UDB1
P32/UDZ1
8-bit up/down
counter/timer
RAM
F
2MC-8L
CPU
16-bit timer/counter
P47/EC
8/16-bit timer
8-bit timer
ROM
P46/TCO2
P45/TCO1
P44/TCI
8-bit timer
CMOS I/O port
8
8
8-bit PWM timer #3
8-bit PWM timer #4
8-bit PWM timer #5
8-bit PWM timer #6
P00/AD0 to
P07/AD7
P30/PWM20
P31/PWM21
P41/PWM01
P43/PWM11
16
P10/A08 to
P17/A15
MOD0
MOD1
External bus
interface
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
2-channel 8-bit
PWM timer
P40/PWM00
P42/PWM10/BZ2
8-bit timer #1
8-bit timer #2
CMOS I/O port
6
N-ch open-drain
output port
P76/SI
P75/SO
P74/SCK
P80 to P85
8-bit serial I/O
8
8
P50/AN0 to
P57/AN7
10-bit AD converter
P73/UI
P72/UO
P71/UCK
AVR
AVCC
AVSS
UART
Input port
Buzzer output
P70/BZ1
8
8
P60/INT0/ADST to
P67/INT7
External interrupt
N-ch open-drain I/O port
VCC, VSS,
MOD0, MOD1
20
DS07-12537-2E
MB89670AR Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89670AR series offer 64 Kbytes of memory for storing all of I/O, data, and program
areas. The I/O area is allocated at the lowest address. The data area is allocated immediately above the I/O
area. Thedataarea can bedividedintoregister, stack, anddirectareasaccordingto the application. Theprogram
area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables of
interrupt reset vectors and vector call instructions are allocated from the highest address within the program
area. The memory space of the MB89670AR series is structured as illustrated below.
• Memory Space
MB89675AR
MB89673AR
MB89677AR
MB89P677A
MB89PV670A
0000H
0080H
0000H
0080H
0000H
0080H
0000H
0080H
I/O
I/O
I/O
I/O
RAM
RAM
384 B
RAM
RAM
0100H
0100H
0100H
0200H
0100H
0200H
512 B
1 KB
1 KB
Register
Register
Register
Register
0200H
0280H
0200H
0280H
Not available
0480H
4000H
0480H
External area
External area
External area
External area
8000H
8000H
8007H
8000H
8007H
8000H
Option PROM (One-time
PROM product)*
*
*
*
8007H
C000H
8007H
C000H
External area
External area
Not available
ROM
16 KB
Programmable
ROM
Programmable
ROM
E000H
32 KB
48 KB
ROM
8 KB
FFFFH
FFFFH
FFFFH
FFFFH
*: Since addresses 8000H to 8006H for the MB89P677A comprise an option area, pay attention to
use this area for the other products in this series.
DS07-12537-2E
21
MB89670AR Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose
registers in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating the instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Indeterminate
Indeterminate
T
: Temporary accumulator
: Index register
IX
Indeterminate
Indeterminate
EP
SP
PS
: Extra pointer
: Stack pointer
Indeterminate
: Program status
I-flag = 0, IL1, IL0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, IL0
N
V
C
RP
CCR
22
DS07-12537-2E
MB89670AR Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, IL0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low
N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit
is cleared to ‘0’.
Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.
DS07-12537-2E
23
MB89670AR Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are of 8 bits each and allocated in the register banks of the memory. One bank
contains eight registers and up to 32 banks can be used on every product of the MB89670AR series. The bank
currently in use is indicated by the register bank pointer (RP).
• Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
24
DS07-12537-2E
MB89670AR Series
■ I/O MAP
Address
00H
Read/Write
(R/W)
(W)
Register abbreviation
Register name
Port 0 data register
PDR0
DDR0
PDR1
DDR1
PDR2
BCTR
01H
Port 0 data direction register
Port 1 data register
02H
(R/W)
(W)
03H
Port 1 data direction register
Port 2 data register
04H
(R/W)
(W)
05H
External bus pin control register
06H
(Vacancy)
07H
(R/W)
(R/W)
(R/W)
(R/W)
SYCC
STBC
WDTC
TBTC
System clock control register
Standby control register
08H
09H
Watchdog timer control register
Timebase timer control register
0AH
0BH
0CH
0DH
0EH
0FH
10H
(Vacancy)
(R/W)
(W)
PDR3
DDR3
PDR4
Port 3 data register
Port 3 data direction register
Port 4 data register
(R/W)
(W)
DDR4
PDR5
Port 4 data direction register
Port 5 data register
(R/W)
(R)
11H
PDR6
Port 6 data register
12H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
PPCR
PDR7
Port 6 pull-up control register
Port 7 data register
13H
14H
PDR8
Port 8 data/port 7 swiching register
Buzzer register
15H
BZCR
CNTR #3
COMP #3
TMCR
TCHR
TCLR
16H
PWM control register #3
PWM compare register #3
16-bit timer control register
16-bit timer count register (H)
16-bit timer count register (L)
17H
18H
19H
1AH
1BH
1CH
1DH
1EH, 1FH
(Vacancy)
(R/W)
(R/W)
SMR
SDR
Serial mode register
Serial data register
(Vacancy)
(Continued)
DS07-12537-2E
25
MB89670AR Series
Address
20H
Read/Write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
Register abbreviation
ADC1
Register name
A/D converter control register 1
A/D converter control register 2
A/D converter data register H
A/D converter data register L
Timer 2 control register
21H
ADC2
22H
ADCH
23H
ADCL
24H
T2CR
25H
T1CR
Timer 1 control register
26H
T2DR
Timer 2 data register
27H
T1DR
Timer 1 data register
28H
CNTR1
CNTR2
CNTR3
COMR2
COMR1
PWM 1 control register
29H
PWM 2 control register
2AH
PWM 3 control register
2BH
PWM 2 compare register
PWM 1 compare register
2CH
(W)
2DH to 2FH
(Vacancy)
(R)
(W)
UDCR1
RCR1
Up/down counter register 1
Reload compare register1
30H
31H
(R)
(W)
UDCR2
RCR2
Up/down counter register 2
Reload compare register2
32H
33H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
CCRA1
CCRA2
CCRB1
CCRB2
CSR1
CSR2
EIC1
Counter control register A1
Counter control register A2
34H
Counter control register B1
35H
Counter control register B2
36H
Counter status register 1
37H
Counter status register 2
38H
External interrupt 1 control register 1
External interrupt 1 control register 2
External interrupt 2 control register
External interrupt 2 flag register
39H
EIC2
3AH
EIE2
3BH
EIF2
3CH to 3FH
(Vacancy)
(Continued)
26
DS07-12537-2E
MB89670AR Series
(Continued)
Address
Read/Write
(R/W)
Register abbreviation
Register name
UART serial mode register
UART serial rate control register
UART status register
40H
41H
42H
USMR
USCR
USTR
(R/W)
(R/W)
(R)
(W)
RXDR
TXDR
UART receiving data register
UART transmitting data register
43H
44H
45H
(Vacancy)
(R/W)
RRDR
Baud rate generator reload data register
46H, 47H
48H
(Vacancy)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
CNTR #4
COMP #4
CNTR #5
COMP #5
CNTR #6
COMP #6
PWM control register #4
PWM compare register #4
PWM control register #5
PWM compare register #5
PWM control register #6
PWM compare register #6
49H
4AH
4BH
4CH
4DH
4E to 7BH
7CH
(Vacancy)
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
7DH
7EH
7FH
(Vacancy)
Note: Do not use (vacancies).
DS07-12537-2E
27
MB89670AR Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Rated value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
VSS – 0.3
VSS – 0.3
VSS + 7.0
VCC + 0.3
V
V
*
*
Power supply voltage
AVCC
A/D converter reference input
voltage
AVR must not exceed
“AVCC + 0.3 V”.
AVR
VSS – 0.3
VCC + 0.3
V
Input voltage
VI
VSS – 0.3
VSS – 0.3
VSS – 0.3
VCC + 0.3
VCC + 0.3
VSS + 7.0
V
V
V
VO1
VO2
Except P80 to P85
P80 to P85
Output voltage
“L” level maximum output
current
IOL
—
—
20
4
mA
mA
Average value (operating current
× operating rate)
IOLAV1
“L” level average output current
Average value (operating current
IOLAV2
—
8
mA × operating rate)
P80 to P85
“L” level total maximum output
current
∑IOL
—
—
—
—
—
—
100
40
mA
“L” level total average output
current
Average value (operating current
× operating rate)
∑IOLAV
IOH
mA
mA
mA
mA
mA
“H” level maximum output
current
–20
–4
Average value (operating current
× operating rate)
“H” level average output current
IOHAV
∑IOH
∑IOHAV
“H” level total maximum output
current
–50
–20
“H” level total average output
current
Average value (operating current
× operating rate)
Power consumption
Operating temperature
Storage temperature
PD
—
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
* : Use AVCC and VCC set at the same voltage.
Take care that AVR does not exceed “AVCC + 0.3 V” and AVCC does not exceed VCC, such as when power is turned
on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
DS07-12537-2E
MB89670AR Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Rated value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Normal operation assurance range
MB89673AR/675AR/677AR
2.2*
6.0
V
VCC
AVCC
Power supply voltage
Normal operation assurance range
MB89PV670A/P677A
2.7*
1.5
6.0
6.0
V
V
Retains the RAM state in the stop mode
A/D converter reference input
voltage
AVR
TA
0.0
AVCC
+85
V
Operating temperature
–40
°C
* : Thesevalues vary with the operating frequency, and analog assurance range. See Figure 1 and “5. A/D Converter
Electrical Characteristics”.
Figure 1 Operating Voltage vs. Clock Operating Frequency
6
5
A/D converter accuracy assured in the
Operation assurance range
VCC = AVCC = 3.5 V to 6.0 V range.
4
3
2
1
Clock operating frequency (MHz)
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Minimum execution time (µs)
4.0 2.0
0.8
0.4
Note: The shaded area is additional operating assurance range only for the MB89673AR/675AR/677AR.
DS07-12537-2E
29
MB89670AR Series
The horizontal line of the graph in the figure 1 indicates the operating frequency of the external oscillator and
the lower horizontal line indicates the min. instruction execution time = 4/FC.
In the case of changing the operating clock with the clock gear function, be sure to convert it into the min.
instruction execution time on the lower horizontal line since the operating voltage range is dependent on the
min. instruction execution time.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
30
DS07-12537-2E
MB89670AR Series
3. DC Characteristics
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Parameter
Pin name
Condition
Unit Remarks
Min.
Typ.
Max.
P32 to P37,
P00 to P07, P10 to P17,
P30 to P37, P40 to P47
P44, and P47
are of a port
VCC + 0.3
VIH
0.7 VCC
⎯
V
input type.
“H” level input
voltage
P32 to P37,
P44, and P47
are of a
peripheral
input type.
RST, MOD0, MOD1,
P32 to P37, P44, P47,
P60 to P67, P70 to P76
VCC + 0.3
0.3 VCC
0.2 VCC
VIHS
VIL
0.8 VCC
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
V
P32 to P37,
P44, and P47
are of a port
input type.
—
P00 to P07, P10 to P17,
P30 to P37, P40 to P47
V
“L” level input
voltage
P32 to P37,
P44, and P47
are of a
peripheral
input type.
RST, MOD0, MOD1,
P32 to P37, P44, P47,
P60 to P67, P70 to P76
VILS
V
Open-drain output
pin applied voltage
P80 to P85
VSS − 0.3
VSS + 6.0
VD
⎯
⎯
V
V
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P71, P72,
P74, P75
“H” level output
voltage
VOH
IOH = –2.0 mA
IOL = 4.0 mA
4.0
⎯
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P70 to P76
VOL1
⎯
⎯
0.4
V
“L” level output
voltage
P80 to P85
RST
VOL2
VOL3
IOL = 10 mA
IOL = 4.0 mA
⎯
⎯
0.5
0.4
V
V
—
—
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, P70 to P76,
MOD0, MOD1
Input leakage
current
(Hi-z output
leakage current)
Without
0.0 V < VI < VCC
ILI1
—
—
5
µA
µA
pull-up
resistor
option
P80 to P85
0.0 V < VI < VCC
VI = 0.0 V
ILI2
—
—
1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P60 to P67, P70 to P76,
RST
With pull-up
Pull-up
resistance
RPULL
25
50
100
kΩ resistor
option
(Continued)
DS07-12537-2E
31
MB89670AR Series
(Continued)
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Parameter
Pin name
Condition
Unit Remarks
Min.
Typ.
Max.
FC = 10 MHz
VCC = 5.0 V
ICC1
—
12
20
mA
tinst*2 = 0.4 µs
MB89673AR/
675AR/677AR/
PV670A
FC = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
—
—
—
1
1.5
3
2
2.5
7
mA
mA
mA
ICC2
MB89P677A
FC = 10 MHz
VCC
VCC = 5.0 V
ICCS1
ICCS2
ICCH
IA
tinst*2 = 0.4 µs
FC = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
Power supply
current*1
—
—
—
1
—
6
1.5
1
mA
mA
mA
VCC = 3.0 V
TA = +25°C
Stop mode
FC = 10 MHz
When A/D
converter starts
8
FC = 10 MHz
TA = +25°C
When A/D
converter is at a
stop
AVCC
IAH
—
—
—
1
µA
Other than AVCC,
AVSS, VCC, and VSS
f = 1 MHz
Input capacitance CIN
10
—
pF
*1: The measurement conditions of the power supply current are as follows.
The external clock is used.
The output pins are open.
VCC is upon the condition above the table.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics”.
Note: The current consumption of connected EPROM and ICE is not considered on MB89PV670A.
32
DS07-12537-2E
MB89670AR Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
tZLZH
0.8 VCC
RST
0.2 VCC
0.2 VCC
(2) Specifications for Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol Condition
Unit
Remarks
Parameter
Min.
Max.
Power supply rising time
Power supply cut-off time
tR
—
50
ms
ms
Power-on reset function only
—
Min. interval time to next
power-on reset
tOFF
1
—
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
t
R
t
OFF
2.0 V
0.2 V
0.2 V
0.2 V
V
CC
DS07-12537-2E
33
MB89670AR Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Min. Max.
10
Pin
Symbol
Condition
Unit
Remarks
Parameter
Clock frequency
name
FC
X0, X1
X0, X1
1
MHz
ns
Clock cycle time
tXCYL
100
20
1000
—
PWH
PWL
—
Input clock pulse width
X0
X0
ns
ns
External clock
External clock
Input clock rising/falling
time
tCR
tCF
—
10
• Clock Timing Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock Configurations
When a crystal
or
ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
FC
Open
C1
C2
(4) Instruction Cycle
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Rated value (typical)
Unit
Remarks
Instruction cycle
(minimum execution time)
(4/FC) tinst = 0.4 µs when operating at
FC = 10 MHz
tinst
4/FC, 8/FC, 16/FC, 64/FC
µs
34
DS07-12537-2E
MB89670AR Series
(5) Clock Output Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
—
Cycle time
CLK ↑ → CLK ↓
tCYC
CLK
CLK
1/2 tinst*
µs
µs
—
1/4 tinst – 0.07
tCHCL
1/4 tinst
* : For information on tinst, see “(4) Instruction Cycle.”
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
DS07-12537-2E
35
MB89670AR Series
(6) Bus Read Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
1/4 tinst* – 0.06
1/2 tinst *– 0.02
—
Max.
—
Valid address → RD
↓ time
RD, A15 to A08,
AD7 to AD0
tAVRL
tRLRH
tAVDV
µs
RD
RD pulse width
—
µs
Valid address → Data
read time
AD7 to AD0,
A15 to A08
1/2 tinst *
µs No wait
RD, AD7 to AD0
AD7 to AD0, RD
RD, ALE
1/2 tinst *– 0.08
RD ↓ → Data read time tRLDV
RD ↑ → Data hold time tRHDX
—
0
µs No wait
—
—
ns
1/4 tinst* – 0.04
RD ↑ → ALE ↑ time
tRHLH
µs
—
RD ↑ → Address loss
time
RD, A15 to A08
1/4 tinst* – 0.04
tRHAX
—
µs
RD, CLK
RD, CLK
RD, BUFC
1/4 tinst* – 0.04
RD ↓ → CLK ↑ time
CLK ↓ → RD ↑ time
RD ↓ → BUFC ↓ time
tRLCH
tCLRH
tRLBL
—
—
—
µs
ns
ns
0
–5
A15 to A08,
AD7 to AD0,
BUFC
BUFC ↑ → Valid
address time
tBHAV
5
—
ns
* : For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
t
RHLH
ALE
0.8 V
0.7 VCC
0.7 VCC
2.4 V
2.4 V
AD7 to AD0
0.8 V
0.8 V
0.3 VCC
0.3 VCC
t
AVDV
t
RHDX
2.4 V
0.8 V
t
2.4 V
2.4 V
0.8 V
A15 to A08
t
RLCH
t
CLRH
0.8 V
AVRL
t
RLDV
t
RHAX
t
RLRH
2.4 V
RD
0.8 V
t
RLBL
t
BHAV
2.4 V
BUFC
0.8 V
36
DS07-12537-2E
MB89670AR Series
(7) Bus Write Timing
Parameter
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Remarks
Symbol
Pin name
Condition
Unit
Min.
Max.
Valid address → ALE
↓ time
AD7 to AD0,
ALE, A15 to A08
tAVLL
tLLAX
1/4 tinst* 2 – 0.064
—
µs
ALE ↓ time →
Address loss time
AD7 to AD0,
ALE, A15 to A08
5*1
—
ns
Valid address → WR ↓ time
WR, ALE
WR
1/4 tinst* 2 – 0.06
1/2 tinst* 2 – 0.02
1/2 tinst* 2 – 0.06
tAVWL
—
—
—
µs
µs
µs
WR pulse width
tWLWH
Writing data → WR ↑ time tDVWL
AD7 to AD0, WR
WR ↑ → Address loss
time
WR, A15 to A08
1/4 tinst* 2 – 0.04
—
µs
—
tWHAX
AD7 to AD0, WR
WR, ALE
WR, CLK
WR, CLK
ALE
WR ↑ → Data hold time tWHDX
1/4 tinst* 2 – 0.04
1/4 tinst* – 0.04
1/4 tinst* 2 – 0.04
0
—
—
—
—
—
—
µs
µs
µs
ns
µs
µs
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
CLK ↓ → WR ↑ time
ALE pulse width
tWHLH
tWLCH
tCLWH
tLHLL
1/4 tinst* 2 – 0.035
1/4 tinst* 2 – 0.03
ALE, CLK
ALE ↓ → CLK ↑ time
tLLCH
*1: These characteristics are also applicable to the bus read timing.
*2: For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
ALE
0.8 V
tLHLL
tLLCH
tWHLH
2.4 V
0.8 V
0.8 V
tLLAX
tAVLL
2.4 V
2.4 V
2.4 V
2.4 V
AD7 to AD0
0.8 V
0.8 V
0.8 V
0.8 V
tWHDX
tDVWH
2.4 V
2.4 V
tCLWH
tWLCH
A15 to A08
0.8 V
0.8 V
tAVWL
tWHAX
tWLWH
2.4 V
WR
0.8 V
DS07-12537-2E
37
MB89670AR Series
(8) Ready Input Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
RDY valid → CLK
↑ time
tYVCH
tCHYX
RDY, CLK
RDY, CLK
60
—
ns
ns
*
*
—
CLK ↑ → RDY loss
time
0
—
* : These characteristics are also applicable to the read cycle.
2.4 V
2.4 V
CLK
ALE
AD7 to AD0
Address
Data
A15 to A08
WR
tYVCH tCHYX
2.4 V
2.4 V
RDY
0.8 V
0.8 V
tYVCH tCHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
38
DS07-12537-2E
MB89670AR Series
(9) Serial I/O Timing
Parameter
(AVCC = 5.0 V 10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol Pin name
Condition
Unit Remarks
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
SCK
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle”.
• Internal Shift Clock Mode
t
SCYC
SCK
2.4 V
0.8 V
0.8 V
t
SLOV
2.4 V
0.8 V
SO
t
IVSH
t
SHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI
• External Shift Clock Mode
t
SLSH
t
SHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t
SLOV
2.4 V
0.8 V
SO
t
IVSH
t
SHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI
DS07-12537-2E
39
MB89670AR Series
(10) Peripheral Input Timing
(AVCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Pin name Condition
Unit Remarks
Parameter
Min.
1 tinst*
1 tinst*
Max.
—
Peripheral input “H” pulse width 1 tILIH1
TCI
TCI
µs
µs
Peripheral input “L” pulse width 1
Peripheral input “H” pulse width 2 tILIH2
Peripheral input “L” pulse width 2 tIHIL2
tIHIL1
—
EC,
INT0 to INT7
—
2 tinst*
2 tinst*
—
—
µs
µs
EC,
INT0 to INT7
Peripheral input “H” pulse width 3 tILIH3
Peripheral input “L” pulse width 3 tIHIL3
Peripheral input “H” pulse width 3 tILIH3
Peripheral input “L” pulse width 3 tIHIL3
ADST
ADST
ADST
ADST
64 tinst*
64 tinst*
64 tinst*
64 tinst*
—
—
—
—
µs
µs
µs
µs
A/D
mode
Sense
mode
* : For information on tinst, see “(4) Instruction Cycle”.
tIHIL1
tILIH1
tILIH2
tILIH3
0.8 VCC
0.8 VCC
0.8 VCC
0.8 VCC
TCI
0.2 VCC
0.2 VCC
tIHIL2
0.8 VCC
0.2 VCC
EC
INT0 to INT7
0.2 VCC
tIHIL3
0.8 VCC
ADST
0.2 VCC
0.2 VCC
40
DS07-12537-2E
MB89670AR Series
(11) Up/down Counter Input Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Symbol
Pin name
Condition
Unit
Remarks
Parameter
Min.
2 tinst*
2 tinst*
2 tinst*
2 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
1 tinst*
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AIN input “1” pulse width
AIN input “0” pulse width
BIN input “1” pulse width
BIN input “0” pulse width
AIN ↑ → BIN ↑ time
tAHL
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
tALL
tBHL
tBLL
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
tZHL
AIN = UDA1,
UDA2
BIN = UDB1,
UDB2
BIN ↑ → AIN ↓ time
AIN ↓ → BIN ↓ time
—
BIN ↓ → AIN ↑ time
BIN ↑ → AIN ↑ time
AIN ↑ → BIN ↓ time
BIN ↓ → AIN ↓ time
AIN ↓ → BIN ↑ time
ZIN input “1” pulse width
ZIN input “0” pulse width
ZIN = UDZ1,
UDZ2
tZLL
* : For information on tinst, see “(4) Instruction Cycle”.
DS07-12537-2E
41
MB89670AR Series
tAHL
tALL
0.8 VCC
0.8 VCC
AIN
0.2 VCC
0.2 VCC
(UDA1, UDA2)
tAUBU
tBUAD
tADBD
tBDAU
0.8 VCC
0.8 VCC
BIN
0.2 VCC
0.2 VCC
(UDB1, UDB2)
tBHL
tBLL
tBHL
tBLL
0.8 VCC
0.8 VCC
0.8 VCC
BIN
(UDB1, UDB2)
0.2 VCC
0.2 VCC
tBUAU
tAUBD
tBDAD
tADBU
0.8 VCC
0.8 VCC
AIN
(UDA1, UDA2)
0.2 VCC
0.2 VCC
tAHL
tALL
0.8 VCC
0.8 VCC
tZHL
ZIN
(UDZ1, UDZ2)
tZLL
0.2 VCC
0.2 VCC
42
DS07-12537-2E
MB89670AR Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 3.5 V to 6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Rated value
Parameter
Resolution
Symbol Pin name
Unit
Remarks
Min.
—
Typ.
—
Max.
10
bit
Linearity error
—
—
2.0
LSB
—
—
Differential linearity
error
—
—
—
—
1.5
3.0
LSB
LSB
V
Total error
AVCC =
AVR = VCC
AN0 to
AN7
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
Zero transition voltage VOT
Full-scale transition
VFST
AN0 to
AN7
AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB
V
voltage
Interchannel disparity
—
—
—
—
4
LSB
µs
A/D mode conversion
time
At 10 MHz
oscillation
13.2
—
—
—
Sense mode
conversion time
At 10 MHz
oscillation
—
—
—
—
7.2
10
µs
Analog port input
current
AN0 to
AN7
IAIN
µA
AN0 to
AN7
Analog input voltage
Reference voltage
0
0
—
—
AVR
AVCC
⎯
V
V
AVR
Reference voltage
IR
AVR
—
200
µA AVR = 5.0 V
supply current
6. Notes on Using A/D Converter
• The smaller | AVR – AVSS |, the greater the error would become relatively.
• The output impedance of the external circuit for the analog input must satisfy the following conditions:
Output impedance of the external circuit < Approx. 10 kΩ If the output impedance of the external circuit is too
high, an analog voltage sampling time might be insufficient (sampling time = 6 µs at 10 MHz oscillation).
An analog input equivalent circuit is shown below.
• Analog Input Equivalent Circuit
Sample & hold circuit
R ≤ 10 kΩ is
recommended. Analog input pin
C
60 pF
Comparator
R
3 kΩ
Analog channel selector
closes for approx. 15 instruction cycles
after starting A/D conversion.
If R > 10 kΩ, it is recommended
to connect an external capacitor
of approx. 0.1 µF.
Microcontrollers internal circuit
DS07-12537-2E
43
MB89670AR Series
Since the A/D converter contains a sample & hold circuit, the level of the analog input pin might not stabilize within
the sampling period after starting A/D, resulting in inaccurate A/D conversion values, if the input impedance to the
analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin.
It is recommended to keep the input impedance to the analog pin from exceeding 10 kΩ. If it exceeds 10 kΩ, it is
recommended to connect a capacitor of approx. 0.1 µF to the analog input pin.
Except for the sampling period after starting A/D, the input leakage current of the analog input pin is less than 10 µA.
7. A/D Converter Glossary
• Resolution
Analog-change that are identifiable with the A/D converter.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of the input voltage needed to change the output code by 1 LSB from the theoretical voltage
• Total error
The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise.
Theoreticall I/O characteristics
VFST
Total error
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
value
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
VNT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VFST – VOT
V
NT
–
{1 LSB × N + 0.5 LSB }
1 LSB =
(V)
Total error of digital output N =
1022
1 LSB
(Continued)
44
DS07-12537-2E
MB89670AR Series
(Continued)
004
Zero transition error
Full-scale transition error
Theoretical value
3FF
3FE
3FD
3FC
Actual conversion
003
002
001
value
Actual conversion
value
VFST (Actual
measured value)
Theoretical
value
Actual conversion
value
Actual conversion
value
VOT (Actual measured value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
Differential linearity error
Theoretical value
3FF
3FE
3FD
Actual conversion
value
N + 1
{1 LSB × N + VOT
}
Actual conversion
V(N + 1)T
value
VFST (Actual
measured
value)
N
004
003
002
001
VNT
N – 1
N – 2
VNT
Actual conversion
value
Actual conversion
value
Theoretical value
VOT (Actual measured value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
V(N+1)T – VNT
VNT – {1 LSB × N + VOT}
Linearity error of digital output N =
Differential linearity error of digital output N =
– 1
1 LSB
1 LSB
DS07-12537-2E
45
MB89670AR Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
VOL1 vs. IOL
VOL1 (V)
VOL2 vs. IOL
VOL2 (V)
0.8
0.8
0.7
0.6
0.7
0.6
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 3.0 V
0.5
0.4
0.5
0.4
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.3
0.2
0.3
0.2
0.1
0
0.1
0
2
1
2
3
4
5
6
4
6
8
10
12
IOL (mA)
IOL (mA)
(2) “H” Level Output Voltage
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
VIN vs. VCC
VCC – VOH vs. IOH
V
IN (V)
V
CC – VOH (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
T
A
= +25°C
T = +25°C
A
V
CC = 2.5 V
CC = 3.0 V
V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
I
0
1
2
3
4
5
6
7
OH (mA)
VCC (V)
46
DS07-12537-2E
MB89670AR Series
(4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
TA = +25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIHS
VILS
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level
(5) Power Supply Current (External Clock)
ICC (mA)
20
ICC vs. VCC
ICCS vs. VCC
ICCS (mA)
10
15
10
5
ICC1
8
6
4
2
ICCS1
ICCS2
0
3
4
5
6
ICC2
VCC (V)
0
3
4
5
6
VCC (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
500
100
50
10
1
2
3
4
5
6
VCC (V)
DS07-12537-2E
47
MB89670AR Series
■ MASK OPTIONS
MB89673AR
MB89675AR
MB89677AR
Part number
No.
MB89P677A
MB89PV670A
Specify when
ordering masking
Set with EPROM
programmer
Specifying procedure
Setting not possible
Pull-up resistors
P10 to P17,
P30 to P37, P40 to P47,
1
Selectable by pin
Selectable by pin
P70 to P76
Fixed to “without
pull-up resistor”
Pull-up resistors
Selectable in 4-pin
unit
2
Selectable by pin
Selectable by pin
P00 to P03
Pull-up resistors
Selectable in 4-pin
unit
3
P04 to P07
Power-on reset
Fixed to “with
power-on reset”
4
5
6
With power-on reset
Without power-on reset
Selectable
Selectable
Selectable
Selectable
Selectable
Selectable
Oscillation stabilization time
selection (at 10 MHz)
Approx. 218/FC (approx. 26.2 ms)
Approx. 217/FC (approx. 13.1 ms)
Approx. 214/FC (approx. 1.6 ms)
Approx. 24/FC (approx. 0 ms)
FC: Clock frequency
Fixed to Approx.
218/FC (Approx.
26.2 ms)
Reset pin output
With reset output
Without reset output
Fixed to “with reset
output”
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89673ARPF
MB89675ARPF
MB89677ARPF
MB89P677APF
80-pin Plastic QFP
(FPT-80P-M06)
MB89673ARPMC1
MB89675ARPMC1
MB89677ARPMC1
MB89P677APMC1
80-pin Plastic LQFP
(FPT-80P-M22)
80-pin Ceramic MQFP
(MQP-80C-P01)
MB89PV670ACF
48
DS07-12537-2E
MB89670AR Series
■ PACKAGE DIMENSIONS
80-pin plastic QFP
Lead pitch
0.80 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP80-14×20-0.80
Code
(Reference)
(FPT-80P-M06)
80-pin plastic QFP
(FPT-80P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
64
41
65
40
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
80
25
0.25(.010)
3.05 –+00..2300
.120 –+..000182
(Mounting height)
1
24
0~8
°
0.80(.031)
0.37±0.05
(.015±.002)
0.17±0.06
(.007±.002)
M
0.16(.006)
0.30 +–00..2150
0.80±0.20
(.031±.008)
"A"
.012 +–..001004
0.88±0.15
(Stand off)
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-12537-2E
49
MB89670AR Series
80-pin plastic LQFP
Lead pitch
0.65 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.62 g
Code
(Reference)
P-LFQFP80-14×14-0.65
(FPT-80P-M22)
80-pin plastic LQFP
(FPT-80P-M22)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
0.145±0.055
(.006±.002)
60
41
61
40
0.10(.004)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
0.25(.010)
INDEX
0~8
˚
80
21
0.10±0.10
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
"A"
0.60±0.15
1
20
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2007-2008 FUJITSU MICROELECTRONICS LIMITED F80036S-c-1-2
2007 FUJITSU LIMITED F80036S--1-
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
50
DS07-12537-2E
MB89670AR Series
(Continued)
80-pin ceramic MQFP
Lead pitch
0.8 mm
Straight
Ceramic
Plastic
Lead shape
Motherboard
material
Mounted package
material
(MQP-80C-P01)
80-pin ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20 +–00..2400
4.50(.177)
TYP
.047 +–..000186
0.80±0.25
(.0315±.010)
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
TYP
14.22(.560)
TYP
0.30(.012)
24.70(.972)
TYP
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
0.40±0.10
(.016±.004)
1.20 +–00..2400
.047 +–..000186
1.50(.059)
TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
1994-2008 FUJITSU MICROELECTRONICS LIMITED M80001SC-4-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12537-2E
51
MB89670AR Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Changed the series name;
MB89670R/670AR Series → MB89670AR series
—
—
Deleted the part numbers.
MB89673R, MB89675R
—
—
—
—
Changed the package code.
FPT-80P-M11 → FPT-80P-M22
■ CORRESPONDENCE BETWEEN THE
MB89670/670A SERIES AND MB89670R/
670AR SERIES
Deleted the “■ CORRESPONDENCE BETWEEN THE
MB89670/670A SERIES AND MB89670R/670AR
SERIES”.
6
■ PROGRAMMING TO THE EPROM ON
THE MB89P677A
17
Deleted the “6. EPROM Programmer Socket Adapter”.
■ PROGRAMMING TO THE EPROM WITH
PIGGYBACK/EVALUATION DEVICE
19
20
Deleted the “2. Programming Socket Adapter”.
■ BLOCK DIAGRAM
Deleted the “1. Block Diagram of MB89673R/89675R”.
■ ELECTRICAL CHARACTERISTICS
5. A/D Converter Electrical Characteristics
Changed the items of “Zero transition voltage” and
“Full-scale transition voltage”.
mV → V
43
47
■ INSTRUCTIONS (136 instructions)
■ INSTRUCTION MAP
Deleted the “■ INSTRUCTIONS (136 instructions)”.
Deleted the “■ INSTRUCTION MAP”.
■ ORDERING INFORMATION
Changed the order informations.
MB89673ARPFM → MB89673ARPMC1
MB89675ARPFM → MB89675ARPMC1
MB89677ARPFM → MB89677ARPMC1
MB89P677APFM → MB89P677APMC1
48
50
■ PACKAGE DIMENSIONS
Changed the package figure.
FPT-80P-M11 → FPT-80P-M22
The vertical lines marked in the left side of the page show the changes.
52
DS07-12537-2E
MB89670AR Series
MEMO
DS07-12537-2E
53
MB89670AR Series
MEMO
54
DS07-12537-2E
MB89670AR Series
MEMO
DS07-12537-2E
55
MB89670AR Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Business & Media Promotion Dept.
相关型号：
©2020 ICPDF网 联系我们和版权申明