MB15E65UV [FUJITSU]
PLL Frequency Synthesizer, PBCC18, PLASTIC, BCC-18;
| 型号： | MB15E65UV |
| 厂家： | 
FUJITSU |
| 描述： | PLL Frequency Synthesizer, PBCC18, PLASTIC, BCC-18 |
| 文件： | 总28页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fujitsu semiconductor
Rev2.0
ASSP
Sigma delta Fractional-N PLL Frequency Synthesizer
(2.0GHz single PLL)
MB15E65UV
ꢀDESCRIPTION
The Fujitsu MB15E65UV includes a serial input Sigma delta Fractional Phase Locked Loop (PLL) frequency
synthesizer with fast lock up function. The PLL consists of 2.0GHz sigma delta Fractional-N PLL.
The new package (BCC18) decreases a mount area of MB15E65UV about 50% comparing with the latest package,
BCC20.
MB15E65UV is ideally suitable for digital mobile communications, such as PHS.
ꢀFEATURE
-Operating frequency
-Fractional-N PLL
: 100MHz - 2.0GHz
: modulo 262144(218) or 32768(215)
Fast lock up and low noise.
:Vcc=2.7V to 3.3V
-Power supply voltage
-Low current consumption : Icc (typ)=4.6mA(Vcc=Vp=3.0V, Ta=25C)
-Direct power saving function : Power supply current in power saving mode
Typ. 0.1 uA(Vcc=3.0V, Ta=25°C), Max. 10 uA(Vcc=3.0V)
-Integrate the automatic selector circuit for the switching the loop filter (Possible to change the switching time)
-Switching charge pump current by a serial data.
Stable mode:94uA / Fast lock mode:4.5mA
-Integrate the open drain switch for the loop filter.
-2-modulus prescaler 16/17
-Serial input programmable reference divider : Binary 6bit R=1 to 63
-Serial input programmable divider consisting of
Binary 4 bit swallow counter : 0 to 15
Binary 8 bit programmable counter : 9 to 255
-Digital lock detector
-On-chip phase control for the phase comparator
-Operating temperature :Ta=-40 to +85 degree C
ꢀPACKAGE
18-pad Plastic BCC
LCC-18P-M05
1
Rev2.0
MB15E65UV
ꢀPIN ASSIGNMENT
BCC-18
TOP VIEW
GND
Do
SW
Vp
Vcc
NC
Xfin
fin
NC
1
2
3
4
5
6
18 17 16 15
VccSD
GND
LD/fout
PS
14
13
12
11
LE
GND
7
8
9
10
Data
OSCin
Clock
LCC-18P-M05
- 2 -
Rev2.0
MB15E65UV
ꢀPIN DESCRIPTIONS
Pin No Pin name I/O
Descriptions
Power supply voltage input pin for the Charge Pump circuit.
Power supply voltage input pin. Except for CP circuit.
No connection
1
2
3
Vp
Vcc
NC
−
−
−
Prescaler complimentary input.
4
5
Xfin
fin
I
I
This pin should be grounded via a capacitor.
Prescaler input pin.
Connection to an external VCO should be via AC coupling.
Load Enable signal input.
When LE is “H”, data in the shift register is transferred to the corresponding latch
according to the control bits in the serial programming data.
6
LE
I
Serial data input. Data is transferred to the corresponding latch ref counter or
program counter according to the control bits setting in the serial programming data.
Clock input for the 24 or 29 bit shift register.
One bit data is shifted into the shift register on a rising edge of the clock.
The programmable reference divider input. External TCXO reference oscillator input
or connection to crystal. TCXO should be connected with via AC coupling.
7
8
Data
CLK
I
I
9
OSCin
GND
I
Ground
10
−
Power saving mode control pin.
This pin must be set at “L” when the power supply is started up. (Open is prohibited)
PS=”H”: Normal mode (according to serial data)
11
12
PS
I
PS=”L”: Power saving mode
Lock detect signal output (LD) / phase comparator monitoring output (fout).
The output signal is selected by the LD1, LD2 and LD3 bits in the serial data.
Lock detector (LD) output has two mode, Buffer output or Open drain output.
The LD signal is outputted by VDIG (3V system) in the Buffer mode. When Open
drain mode is selected, the LD/fout pin should be connected to the outside power
supply via pulled-up resistor. When the resistor is 50ohm, the leakage current of low
state is about 50uA and the constant value is 4usec. (Recommendation value)
LD/fout
O
Ground
13
14
GND
−
−
Power supply voltage input pin for the sigma delta modulation section.
Except for CP.
VccSD
No connection
15
16
NC
−
Open drain switch for the high speed up mode
SW
O
Ground
17
18
GND
Do
−
Charge Pump output.
O
- 3 -
Rev2.0
MB15E65UV
ꢀBLOCK DIAGRAM
Input
Buffer
OSCin
Phase
Detector
Proportional
Charge Pump
Reference
Counter
Do
Dual modulus
Prescaler
Main Counter &
Swallow Counter
Lock
Detector
fin
LD/fout
SW
Selector
Sigma delta
Fractional modulation
PS
Speedup
Switch Timer
Data
LE
Control logic
(29bitShift Register)
Clock
- 4 -
Rev2.0
MB15E65UV
ꢀABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Symbol
Vcc
Vp
Rating
-0.5 to 3.6
Vcc to 3.6
-0.5 to Vcc+0.5
max. +8
Unit
V
Remark
Vcc=VccSD
V
Vi
V
PI
dBm
V
RF Input power
AC Input voltage
VIRF
Vo
max. Vcc
GND to Vcc
GND to Vp
-10 to +10
-55 to +125
V
LD/fout
Do
Output voltage
VDo
IMAX
TSTG
V
Input current
mA
°C
Storage temperature
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ꢀRECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ. Max.
Vcc
Vp
Vi
3.0
3.3
3.3
V
V
Vcc=VccSD
Power supply voltage
Input voltage
Vcc
GND
-40
-
-
-
Vcc
+85
V
Operating temperature
Ta
°C
Note: Vcc must supply equal voltage.
Handling Precautions
-This device should be transported and stored in anti-static containers.
-This is a static-sensitive device ; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
-Always turn the power supply off before inserting or removing the device from its socket.
-Protect leads with a conductive sheet when handling or transporting PC boards with devices
- 5 -
Rev2.0
MB15E65UV
ꢀELECTRICAL CHARACTERISITCS
(Vcc=2.7V to 3.3V, Ta=-40 to +85°C)
Value
Typ.
4.9
Parameter
Symbol
Condition
Vcc=Vp=3.0V
Unit
Min.
Max.
Icc*1
Ips
−
6.5
mA
uA
Power supply current
Power saving current
Vcc current at PS=”L
−
0.1*2
10
fin*3
AC coupling.
100
−
2000
MHz
MHz
Operating frequency
Input sensitivity
−
R=1
5
20
fosc
min. 500mVpp
−
−
2 ≤ R ≤ 63
5
40
+2
PfinRF
50Ω termination
-10
0.5
dBm
Vp-p
Vosc
1.0
1.5
Phase Detector
Operating Frequency
fMAIN_PD
0.4
−
20
MHz
Data,
Clock
LE
0.7Vcc+0
VIH
VIL
VIH
VIL
Schmitt trigger input
Schmitt trigger input
−
−
−
−
V
V
V
V
0.3Vcc-0.
−
Input voltage
Input current
Output voltage
0.7Vcc
−
PS
−
−
−
−
−
0.3Vcc
+1.0
+1.0
−
Data
Clock
LE
IIH*4
IIL*4
VOH
-1.0
uA
uA
V
-1.0
Vcc=3.0V, IOH=-1mA
Vcc-0.4
LD/fout
Vcc=3.0V, IOL=1mA
VOL
VOH
VOL
−
Vp-0.4
−
−
−
−
−
0.4
−
V
V
Vcc=Vp=3.0V, IOH=-0.01mA
Vcc=Vp=3.0V, IOH=0.01mA
Do
Do
SW
0.4
2.5
V
High impedance
cutoff current
Vcc=3.0V, VOFF=0.5V to Vcc-0.5V
IOFF
−
nA
Normal mode (Switch at OFF)
Hi speed mode(Switch at ON)
100
−
−
kΩ
Hi-Speed mode
output Resistance
ZSSH
−
35
70
Ω
- 6 -
Rev2.0
MB15E65UV
ꢀELECTRICAL CHARACTERISITCS (Continued)
Value
TYP
Parameter
Symbol
Condition
Unit
MIN
MAX
IOH*5
IOL
−
−
−
-1.0
−
mA
mA
uA
Vcc=3.0V
Vcc=3.0V
LD/fout
+1.0
-0.16
+0.04
-6.1
IDOH*4
IDOL
-0.094
+0.094
-4.5
-0.04
+0.16
-2.4
+6.1
Vcc=Vp=3.0V,VDOH=Vp/2
Ta=25°C, TMC=CS=”L”
Output current
uA
Do
IDOH*4
IDOL
mA
mA
Vcc=Vp=3.0V,VDOH=Vp/2
Ta=25°C, TMC=”L”,CS=”H”
+2.4
+4.5
CP current RF
ratio
VDO=Vp/2,Ta=25°C
IDOL/IDOH
IDOMT*5
−
8
15
%
∗1:Conditions: Vcc=VccSD=Vp=3.0V,Ta=25°C, fvco=1800MHz,fosc=19.2MHz(-2dBm), fr=4.8MHz in locking state
∗2:Conditions: Vcc=VccSD=Vp=3.0V, Ta=25°C, fosc=19.2MHz(-2dBm),CLK,Data,LE:VIL=GND, VIH=Vcc
∗3:AC coupling. The minimum frequency is specified with a connecting coupling capacitor of 1000pF.
∗4: The minus “-“ means the direction of current flow.
∗5:Conditions: Vcc=Vp=3.0V, Ta=25°C ( | | IDOL | - | IDOH | | )/ [( | IDOL | + | IDOH| )/2] × 100%
- 7 -
Rev2.0
MB15E65UV
ꢀFUNCTIONAL DESCRIPTION
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Serial data of binary data is entered
through Data pin. On rising edge of clock, one bit of serial data is transferred into the shift register. When
load enable signal is high, the data stored in the shift register is transferred to one of latch them depending
upon the control bit data setting.
Control bit (CN1, CN2 and CN3) and shift resistor format are as follows.
According to “LEN” bit, the serial data length can be changed. At that time, the order of the bits is also changed.
When “LEN” bit is “0”, the format of first byte can be changed according to MODE bit.
*The 3rd Line with Mode bit should be inputted at first. If the 3rd Line is inputted finally after Power-ON, the 1st Line will
be invalid.
Table1. Shift Register Configuration at “LEN” bit=1
LSB
Data Flow
MSB
CN CN CN
Line
1st
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1
1
2
3
TM TM
U1 U2
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 A1 A2 A3 A4 N1 N2 N3 N4
TM TM TM TM TM TM TM
2nd
3rd
0
0
1
0
0
0
R1 R2 R3 R4 R5 R6
LD LD LD DE
X
X
X
X
X
X
N5 N6 N7 N8
PW LE
X
X
X
X
X
X
X
X
X
X
1
2
3
4
5
6
7
OD
SW
MO
DE
FC
X
X
X
X
X
CS
SC
TMC
X
X
1
2
3
T
DN
N
Table2. Shift Register Configuration at “LEN” bit=0 and “MODE” bit=0
LSB
Data Flow
MSB
CN CN CN
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
1
2
3
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 A1 A2 A3 A4 N1
0
0
1
0
0
0
R1 R2 R3 R4 R5 R6 TM1 TM2 TM3 TM4 TM5 TM6 TM7
X
X
N2 N3 N4 N5 N6 N7 N8
LD LD LD DE
OD
SW
MO
DE
TM TM PW LE
FC
X
X
X
X
X
CS
SC
TMC
X
1
2
3
T
U1 U2 DN
N
Table3. Shift Register Configuration at “LEN”bit=0 and “MODE” bit=1
LSB
Data Flow
MSB
CN CN CN
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
1
2
3
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 A1 A2 A3 A4 N1 N2 N3 N4
0
0
1
0
0
0
R1 R2 R3 R4 R5 R6 TM1 TM2 TM3 TM4 TM5 TM6 TM7
X
X
X
X
X
X
N5 N6 N7 N8
TM TM PW LE
LD LD LD DE
OD
SW
MO
DE
FC
X
X
X
X
X
CS
SC
TMC
1
2
3
T
U1 U2 DN
N
Note: Data input with MSB first.
- 8 -
Rev2.0
MB15E65UV
Description for the serial data
F1 to F18
: Fractional-N increment setting bit for the fractional accumulator
(F1 to F15)
At MODE bit=0 (MODE1): 0 to 262143.
At MODE bit=1 (MODE2): 0 to 32767 (F<Q)
A1 to A4
N1 to N8
R1 to R6
TMC
TM1 to TM7
TMU1 to TMU2
: Divide ratio setting bits for the swallow counter. (0 to 15)
: Divide ratio setting bits for the programmable counter. (9 to 255)
: Divide ratio setting bits for the reference counter. (1 to 63)
: Timer circuit switch bit. (TMC=1:Enable, TMC=0:Disable)
: Delay time setting bits for timer at speed up mode.
: Compensate time setting bits at speed up. (The range is 0D to 15D, TM+TMU)
At LEN bit=1:Set it on 1st Line.
At LEN bit=0:Set it on 3rd Line.
LD1 to LD3
DET
: Select bit for the lock detect output or a monitoring the counter output.
: Select bit for the lock detect output. *1
DET bit=”0”: Buffer output mode
DET bit=”1”: Open drain mode
FC
CS
:Phase control bit for the phase detector.
:Charge pump current setting bit for speed up timer
CS bit=”0”: Change charge pump current. The switching time depends on setting time
of TM bit.(Icp is 4.5mA to 0.1mA).
CS bit=”1”: Fix charge pump current (Icp=4.5mA)
:Open drain (NMOS-Tr) switch control bit for the speed up mode.
ODSW bit=”0”: Active. The period of ON/OFF depends on setting time of TM bit.
ODSW bit=”1”: OFF
ODSW
SC
: Order of sigma delta setting bit
SC bit=”0” : 2nd order
SC bit=”1” : 3rd order
MODE
: Modulo setting bit and data format of 1st Line setting bit.
MODE bit=”0”: MODE1 Modulo=262144=(218)
MODE bit=”1”: MODE2 Modulo=32768=(215)
: Power saving setting bit. Control the power saving mode by the relation of the PWDN bit
and PS pin
PWDN
LEN
: Data length setting bit
LEN bit=”0”: 24bit
LEN bit=”1”: 29bit
X
:Dummy bit(Set "0")
Note : Data input with MSB first
*1: Lock detector (LD) output has two mode, Buffer output or Open drain output.
The LD signal is outputted by Vcc (3V system) in the Buffer mode. When Open drain mode is selected, the
LD/fout pin should be connected to the outside power supply via pulled-up resistor. When the resistor is
50kohm, the leakage current of low state is about 50uA and the time constant value is 4usec.
(Recommended value)
- 9 -
Rev2.0
MB15E65UV
Synthesizer data setting (Fractional-N)
Fractional-N PLL divide ratio can be calculated using the following equation:
fvco =NTOTAL x fosc / R
NTOTAL = P × N + A + 3 + F/Q
fvco : Output frequency of external voltage controlled oscillator (VCO)
NTOTAL: Total divide ratio
fosc : Reference oscillation frequency
R
P
N
A
F
: Preset divide ratio of binary 6-bit reference counter (1 to 63)
: Preset divide ratio of 2- modulus prescaler (16)
: Preset divide ratio of binary 8-bit programmable counter (9 to 255)
: Preset divide ratio of binary 4-bit swallow counter (0 to15)
: A numerator of Fractional-N (MODE1:0 to 262143 or MODE2:0 to 32767)
: A denominator of Fractional-N (MODE1:2^18 or MODE2:2^15)
Q
When F value is an even number, the value is added +1 at MODE1, and the value is added +1/8 at MODE2.
EX) fosc=19.8MHz, fvco=2000MHz and R=6
fr=19.8MHz/6=3.3MHz
NTOTAL=2000MHz/3.3MHz=606.060606
Integer part: 606=PxN+A+3
At P=16 ∴N=37, A=11
Fraction part: F/Q=(2000MHz/3.3MHz/2)-606
At Q=262144, F=15887.51499
Select Cut off the decimal. ∴F=15887
At that time, the frequency gap is for F=0.51499
∴fgap=0.51499/262144x(19.8MHz/6)=6.5Hz
Table4. Fractional-N increment of the fractional accumulator Data setting (F1 toF18)
Divide
F
F
F
F
F
F
F
F
F
F
9
F
8
F
7
F
6
F
5
F
4
F
3
F
2
F
1
ratio ( F ) 18 17 16 15 14 13 12 11 10
0
0
0
0
•
0
•
•
1
0
0
0
•
0
•
•
1
0
0
0
•
0
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
0
•
1
•
•
1
0
0
1
•
1
•
•
1
0
1
0
•
1
•
•
1
1
2
•
32767
•
•
262144
Note: When the Modulo (Q) is 2^18, F1 to F=15 are available. F=0 to 32767
When the Modulo (Q) is 2^15, F1 to F=18 are available. F=0 to 262143
- 10 -
Rev2.0
MB15E65UV
Table.5 Binary 8 bit Programmable counter data setting (N1 to N8)
Divide
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
9
0
0
•
1
0
0
•
1
0
0
•
1
0
0
•
1
1
1
•
1
0
0
•
1
0
1
•
1
1
0
•
1
10
•
255
Note: Divide ratio less than 9 is prohibited.
Table.6 Binary 4 bit swallow counter data setting (A1 to A4)
Divide
ratio (A)
A
4
A
3
A
2
A
1
0
1
0
0
•
1
0
0
•
1
0
0
•
1
0
1
•
1
•
15
Note: Divide ratio (A) range=0 to 15, A<N
Table.7 Binary 6 bit programmable reference counter data setting (R1 to R6)
Divide
ratio (R)
R
6
R
5
R
4
R
3
R
2
R
1
1
0
0
0
0
0
1
2
•
63
0
•
1
0
•
1
0
•
1
0
•
1
1
•
1
0
•
1
Table.8 Phase comparator phase switching data setting (FC)
FC=”1”
FC=”0”
Do
(1)
(2)
fr > fp
fr < fp
H
L
L
H
VCO output
Frequency
fr = fp
Z
Z
VCO polarity
(1)
(2)
VCO Input Voltage
NOTE: Z= High impedance
When the LPF and VCO characteristics are similar to (1), set FC bit high
When the VCO characteristics are similar to (2), set FC bit low.
- 11 -
Rev2.0
MB15E65UV
Timer circuit
Fast lock up time can be achieved by using the timer circuit for speed up mode.
The timer circuit for speed up mode controls the time to switch the charge pump current, or internal open drain output
or serial switch according to setting time automatically. The time set by TM bits. The variable charge pump current can
be set by CS bit. Also the switching time of the open drain can be controlled by ODSW bit.
Table 9. Switching time setting bit (TM1 to TM7)
Value for the
switching time(TM)
1
TM7
TM6
TM5
TM4
TM3
TM2
TM1
Ex. fosc=19.2MHz
0
-
0
-
0
-
0
-
0
-
0
-
1
-
3.3us
-
-
126
127
0
1
1
1
1
1
1
1
1
1
1
1
0
1
420us
423.3us
The switching time depends on oscillator frequency (fosc).
Switching time = 64 / fosc x TM
Table.10 Compensate time setting bits at speed up (TMU1 to TMU2)
Compensate value
TMU2
TMU1
(TMU)
0
5
0
0
1
1
0
1
0
1
10
15
*Total value for the switching time of speed up is calculated by the following
Switching time =64/foscx(TM+TMU), TM+TMU=1 to 142
Table.11 High-speed mode function setting (ODSW)
ODSW
1
0
OFF
Active
Table.12 Charge pump current setting bits (CS)
Charge pump
current
TMC bit
CS
(Timer circuit)
+/-0.094mA(fixed)
+/-4.5mA(fixed)
0
1
0
1
0
0
1
1
+/-4.5mA to +/-0.094mA
+/-4.5mA(fixed)
- 12 -
Rev2.0
MB15E65UV
Table.13 LD/fout output setting bit(LD1 to LD3)
Maximum operating
frequency
LD/fout output
LD
LD3
LD2
LD1
-
0
1
-
-
0
1
1
1
1800 MHz
1
1
0
fr
fout
2000 MHz
fp
Prohibit
When Lock detector output is selected, there are two outputs mode, Buffer output or Open drain.
In case of Buffer output, the output is digital output at 3V system.
In case of Open drain output, should pull up to the external voltage via resistor. When the resistor is
50kohm, the time constant is at 4usec, and then the leak current is about 50uA.
- 13 -
Rev2.0
MB15E65UV
ꢀ Power saving mode
Table.14 Power saving mode setting
PLL State
Normal
PS pin
PWDN bit
H
L
1
1
Power
saving
0
0
H
L
The intermittent mode control circuit reduces the PLL power consumption.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Operation mode
The set section and reference oscillation circuit are operated. It is normal operation.
Power save mode
The power supply current in power save mode is at 0.1uA(typ). Max.10uA.
The phase detector output, Do, becomes high impedance.
The lock detector, LD, remains high, indicating a locked condition.
OFF
ON
Vcc
tv>1us
Clock
Data
LE
tps>100ns
PS
(1)
(3)
(2)
(1) Set PS=”L” (power saving mode) at Power-ON.
(2) Set serial data 1us later after power supply remains stable (Vcc>2.2V).
(3) Release power saving mode (PS : “L” “H”) at least 100ns after setting serial data.
- 14 -
Rev2.0
MB15E65UV
ꢀ Serial data input timing
MSB
LSB
Data
Clock
LE
t0
t1
t5
t2
t3 t6 t4
Table15.Timing parameters
Parameter
MIN.
100
20
TYP.
MAX.
Unit
Note
CK Rate
t0
t1
t2
t3
t4
t5
t6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
tsu CK→Data
th CK→ Data
tsu LE
20
30
tsu inactive
tw CK
20
30
tw LE
100
Note: LE should be “L” when the data is transferred into the shift register.
On rising edge of the clock, one bit of the data is transferred into the shift register.
- 15 -
Rev2.0
MB15E65UV
ꢀSetting method
Example: In case that the serial data length of 1st Line is 29bit..
1.Power-ON
Supply the voltage on all Vcc pins at the same time. If the voltage for Vcc is supplied at the different timing, the leak
current is caused.
PS pin should be low at Power-ON.
2.Initial setting (PS pin is low)
LSB
Data Flow
MSB
CN CN CN
Line
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1
0
0
1
2
0
0
3
0
0
LD LD LD DE
1
OD
SW
MO
DE
PW LE
FC
1
X
0
X
0
X
0
X
0
X
0
CS
0
X
0
X
0
TMC
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
3rd
2
3
T
DN
N
0
0
0
0
0
0
0
1
1
TM TM
U1 U2
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 A1 A2 A3 A4 N1 N2 N3 N4
1st
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
X
0
0
X
0
0
X
0
1
X
0
0
0
1
1
0
X
0
0
X
0
0
X
0
0
X
0
0
X
0
TM TM TM TM TM TM TM
R1 R2 R3 R4 R5 R6
N5 N6 N7 N8
1
2
3
4
5
6
7
2nd
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
(1) Input the binary data from 3rd Line as the above table.
(2) Set each value in F bits, A bits, N bits and R bits of the initial operating frequency.
(3) 2nd and 3rd Lines are almost used at fixed status, so it is not necessary to reload the Lines after initial setting.
(It is necessary to write the 2nd Line according to the frequency setting after initial setting.)
In case that 1st Line is with 29bit length, you should only write the 1st Line when the frequency is changed.
(4) Monitor the state of LD/fout pin after data setting. When LD/fout is at “High”, the state of PLL is power
saving and the operation is normal.
(5) Dummy bit, “x” should be set at “0”.
3.Release the power saving
(1) PS pin change to “High”, and then PLL should be locked. When LD/fout is at “High”, PLL is locked.
*Turn on a VCO or a reference oscillator as TCXO before PS pin change to “High”.
4.Change the frequency
(1) Write 1st Line only according to frequency setting.
(If the N5 to N8 bit in 2nd Line need to be changed for setting frequency, it is necessary to write the 2nd Line.)
CN CN CN
Line
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1
2
3
F
F
F
F
F
F
F
F
F
TM TM
U1 U2
1
F1 F2 F3 F4 F5 F6 F7 F8 F9
A1 A2 A3 A4 N1 N2 N3 N4
10 11 12 13 14 15 16 17 18
1st
up up up up up up up up up up up up up up up up up up up
up up up
1
up up up
up
up up
- 16 -
Rev2.0
MB15E65UV
ꢀPhase detector output waveform
fr
fp
twL
twu
LD
(FC bit=“1”)
Z
Do
Do
(FC bit=“0”)
Z
LD output logic table
PLL state
Locking state/Power save state
Unlocking state
LD output
H
L
Note: 1.Phase error detection range = -2π to +2π
2.Pulses on Do signal during locked state are output to prevent dead zone.
3.LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for eight cycles or more.
4.tWU and tWL depend on fin input frequency.
tWU > 1/(fin/16) (s) (e.g. tWU > 9.82ns, fin=1629.9MHz)
tWL < 2/(fin/16) (s) (e.g. tWL < 19.63ns, fin=1629.9MHz)
- 17 -
Rev2.0
MB15E65UV
ꢀMeasurement circuit (for measuring input sensitivity of fin and OSCin)
Do
GND
SW
0.1uF
Vp
NC
1
2
3
4
5
6
18 17 16 15
14
VccSD
Vcc
NC
0.1uF
0.1uF
GND
LD/fout
PS
13
MB15E65UV
1000pF
Oscilloscope
Xfin
fin
12
11
LE
GND
50Ω
7
8
9
10
Data Clock OSCin
1000pF
50Ω
Controller
(Divide ratio setting)
- 18 -
Rev2.0
MB15E65UV
ꢀTYPCAL CHARACTERISTICS
1.fin input sensetivity
fin input sensitivity
10
5
0
SPEC
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
Vcc=2.7V
Vcc=3.0V
Vcc=3.3V
0
500
1000
1500
2000
2500
Frequency (MHz)
2.OSCin input sensetivity
OSCin input sensitivity
10
5
Vcc=2.6V
Vcc=3.0V
Vcc=3.4V
SPEC
0
-5
-10
-15
-20
-25
-30
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz)
- 19 -
Rev2.0
MB15E65UV
3.Do output current
CP=94uA
150
Vcc=Vp=3.0V
100
50
0
-50
-100
-150
-1
0
1
2
3
4
VDO[V]
CP=4.5mA
6
4
Vcc=Vp=3.0V
2
0
-2
-4
-6
-1
0
1
2
3
4
VDO[V]
- 20 -
Rev2.0
MB15E65UV
4.fin input impedance
5.OSCin input impedance
- 21 -
Rev2.0
MB15E65UV
ꢀLOOP CHARACTERISTICS
fvco=800MHz Vcc=3.0V
Kv=25MHz/V
Vvco=5.0V
OSCin
S.G
Do
fr=3.25MHz(R=4) Ta=25°C
LPF
fosc=13.0MHz
TMC=”1”,TM=”5”
SW
fin
PD1=PD2=”1”,CS=”0”,ODSW=”0”,SC=”1”,MODE=”0”
Do
VCO
Spectrum
Analyzer
VCO
7400pF
2200pF
1.3kΩ
4.7kΩ
SW
PLL Phase Noise & Spurious Noise
C/N 1kHz Offset
C/N 100kHz Offset
C/N 200kHz Offset
Ref.Leakage 3.25MHz Offset
- 22 -
Rev2.0
MB15E65UV
PLL Lock Up time
L:800MHz -> H:835MHz ±1kHz
Lch -> Hch 380us
PLL Lock Up time
H:835MHz -> L:800MHz ±1kHz
Hch -> Lch 422us
- 23 -
Rev2.0
MB15E65UV
ꢀApplication example
LPF
Output
VCO
Do GND SW
0.1uF
0.1uF
NC
Vp
1
2
3
4
5
6
18 17 16 15
14
VccSD
Vcc
NC
Xfin
fin
0.1uF
GND
LD/fout
PS
13
MB15E65UV
1000pF
12
11
Lock Det.
GND
LE
7
8
9
10
Data Clock OSCin
TCXO
Clock, Data, LE: Schmitt trigger circuit provided (Insert a pull-down or pull-up resister as needed to
prevent oscillation when the terminals are left open)
- 24 -
Rev2.0
MB15E65UV
ꢀSIGMA DELTA FRACTIONAL-N FUNCTION
Fractional-N type PLL uses the sigma delta modulation method, and has the following features.
(1) Integer operation at F=0
In F=0, the sigma delta circuit block is completely stopped, and RF PLL operates same as Integer-N PLL.
Therefore, it is the best of the noise characteristic.
(2) Spurious characteristics
Spurious is generated in the offset part of fp, which is the comparison frequency. (It corresponds to reference
Leak in the Integer-N PLL.)
(Ex.)
Ntotal becomes 247 in the use condition of fvco=802.75MHz, fosc=13MHz, and R=4, and F becomes 0(Integer
mode). At this time, spurious generation in the fp/R=13MHz/4=3.25MHz offset. (Reference Leak) (Spurious
becomes a waveforms like RefLeakage of P22, and can improve by the filter design)
Spurious is generated in F/Q×fp or (Q-F)/Q×fp offset by the sigma delta circuit operation.
(Ex.)
Ntotal is 248.0615385, and F becoming 16131, and the spurious generation in the F/Q x fp=200kHz offset at
fosc=13MHz, R=4, and fvco=806.2MHz.
200kHz Offset
It is possible to adjust the filter as a method of decreasing this spurious. Moreover, spurious can be lost by
changing R value, and changing fr.
For instance, F value becomes 16131 by Ntotal=247.0615385, and spurious is generated in F/Q x fp=200kHz
and 200kHz offset in fvco=802.95MHz at fosc=13MHz and R=4. However, F value becomes 216772 by
Ntotal=308.8269231 when changing to R=5. Spurious is attenuated by LPF and disappears though generates
spurious in the F/Q x fp=2.1499MHz offset.
There is a possibility to which CN is deteriorated because the comparison frequency changes. Therefore, the
characteristic confirmation by the use condition is necessary. The example of the waveforms in that case is
appended to the next page.
- 25 -
Rev2.0
MB15E65UV
R=4 (200kHz offset)
R=5 (200kHz offset)
R=4 (In band waveform)
R=5 (In band waveform)
R=4 (1kHz offset)
R=5 (1kHz offset)
- 26 -
Rev2.0
MB15E65UV
F/Q=1/2, 1/4, and 1/8 ··· When the binary dividing frequency is set, spurious is generated. When the decrease of spurious is
difficult, spurious can be decreased by moving F value to the range of the allowance of the frequency gap.
(Ex.)
Spurious noise generation on the entire floor when F=131072(F/Q=1/2) is set.
Spurious noise generation on the floor when F=65536(F/Q=1/4) is set.
The example of the generation at that time in the following of the spurious waveform is shown. Moreover, the example of the
waveform in case of F value +5 and F value +10 is shown.
F=65536(F/Q=1/4)
F=131072(F/Q=1/2)
F=131072+5
F=65536+5
F=131072+10
F=65536+10
Rev2.0
MB15E65UV
ꢀLOOP FILTER (Hi-Speed mode)
Option
DO
C2
R1
R2
C1
SW
ꢀPACKAGE DIMENSION
Plastic BCC 18pin
Unit : mm(inches)
Note: ( )values:Reference
- 28 -
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