MB15F02SLPFV1 [FUJITSU]
Dual Serial Input PLL Frequency Synthesizer; 双串行输入锁相环频率合成器
| 型号： | MB15F02SLPFV1 |
| 厂家： | 
FUJITSU |
| 描述： | Dual Serial Input PLL Frequency Synthesizer |
| 文件： | 总25页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21356-3E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F02SL
■ DESCRIPTION
The Fujitsu MB15F02SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1200 MHz and a
500 MHz prescalers. The 1200 MHz and 500 MHz prescalers have a dual modulus division ratio of 128/129 or
64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15F02SL uses the latest BiCMOS process. As a result,
the supply current is typically 3 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5
mA or 6 mA. The charge pump current is selectable by serial data.
MB15F02SL is ideally suited for wireless mobile communications, such as GSM and PDC.
■ FEATURES
• High frequency operation: RF synthesizer: 1200 MHz max
IF synthesizer: 500 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 3.0 mA typ. (VCC = 2.7 V, Ta = +25°C, in IF, RF locking state)
ICC = 3.5 mA typ. (VCC = 3.0 V, Ta = +25°C, in IF, RF locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = 3.0 V, Ta = +25°C), Max. 10 µA (VCC = 3.0 V)
• Dual modulus prescaler: 1200 MHz prescaler (64/65, 128/129)/500 MHz prescaler (8/9 or 16/17)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
• Pin compatible with MB15F02, MB15F02L
■ PACKAGES
16-pad plastic BCC
16-pin plastic SSOP
(LCC-16P-M04)
(FPT-16P-M05)
MB15F02SL
■ PIN ASSIGNMENTS
16-pin SSOP
16-pad BCC
GNDRF Clock
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDRF
OSCIN
GNDIF
finIF
Clock
Data
LE
16 15
OSCIN
1
14
Data
GNDIF
finIF
2
3
4
5
6
13
12
11
10
9
LE
finRF
VCCRF
XfinRF
PSRF
DORF
finRF
VCCRF
XfinRF
PSRF
TOP
VIEW
TOP
VIEW
VCCIF
LD/fout
PSIF
VCCIF
LD/fout
PSIF
7
8
DOIF
DOIF DORF
(FPT-16P-M05)
(LCC-16P-M04)
2
MB15F02SL
■ PIN DESCRIPTIONS
Pin no.
Pin
SSOP-16 BCC-16
I/O
Descriptions
name
1
2
3
4
5
16
1
GNDRF
OSCIN
GNDIF
finIF
–
I
Ground for RF-PLL section.
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
2
–
I
Ground for the IF-PLL section.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
3
4
VCCIF
–
Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
6
7
5
6
LD/fout
PSIF
O
I
The output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PSIF = “H” ; Normal mode
PSIF = “L” ; Power saving mode
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
8
9
7
8
DoIF
O
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
DoRF
Power saving mode control for the RF-PLL section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PSRF = “H” ; Normal mode
10
9
PSRF
I
PSRF = “L” ; Power saving mode
Prescaler complementary input for the RF-PLL section.
This pin should be grounded via a capacitor.
11
12
13
14
10
11
12
13
XfinRF
VCCRF
finRF
LE
I
–
I
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RF-PLL
is lost.
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
I
Serial data input (with a schmitt trigger input buffer.)
Data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
15
16
14
15
Data
I
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
Clock
3
MB15F02SL
■ BLOCK DIAGRAM
VCCIF GNDIF
5 (4) 3 (2)
Intermittent
PSIF 7
3-bit latch
7-bit latch
11-bit latch
mode control
(6)
fpIF
(IF-PLL)
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programmable
counter (IF-PLL)
Charge
pump
(IF-PLL)
Phase
comp.
(IF-PLL)
8
(7)
DoIF
Current
Switch
LDS SWIF FCIF
Lock
Det.
(IF-PLL)
Prescaler
finIF 4
(IF-PLL)
(3)
8/9, 16/17
1-bit latch
2-bit latch
T1 T2
14-bit latch
LDIF
Binary 14-bit
programmable ref.
counter (IF-PLL)
C/P setting
current CP
frIF
OSCIN 2
(1)
Selector
AND
frRF
LD
Binary 14-bit
programmable ref.
counter (RF-PLL)
frIF
C/P setting
current CP
T1 T2
6
(5)
frRF
fpIF
fpRF
LD/
fout
OR
2-bit latch
14-bit latch
1-bit latch
(12)
finRF 13
Prescaler
(RF-PLL)
64/65, 128/129
Lock
Det.
11
XfinRF
(RF-PLL)
(10)
Charge
Phase
comp.
(RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
9
(8)
Current
switch
DoRF
pump
LDS SWRF FCRF
Intermittent
mode control
(RF-PLL)
(RF-PLL)
PSRF 10
(9)
fpRF
3-bit latch
7-bit latch
11-bit latch
Schmitt
circuit
LE 14
(13)
Latch selector
(14)
Data 15
Schmitt
circuit
C
N
1
C
N
2
23-bit shift register
Schmitt
circuit
Clock 16
(15)
(11)
(16)
1
12
VCCRF
GNDRF
O : SSOP
( ) : BCC
4
MB15F02SL
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Remark
Min.
–0.5
–0.5
GND
–55
Max.
Power supply voltage
Input voltage
VCC
VI
+4.0
V
V
VCC +0.5
VCC
Output voltage
VO
V
Storage temperature
Tstg
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.4
Typ.
3.0
–
Max.
3.6
Power supply voltage
Input voltage
VCC
VI
V
V
GND
–40
VCC
Operating temperature
Ta
–
+85
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F02SL
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
finIF = 500 MHz, VCCIF = 2.7 V
(VCCIF = 3.0 V)
1.2
*1
ICCIF
–
–
mA
mA
(1.5)
Power supply current*1
finRF = 1200 MHz, VCCRF = 2.7 V
(VCCRF = 3.0 V)
1.8
(2.0)
*1
ICCRF
–
–
0.1*2
IPSIF
IPSRF
finIF
PSIF = PSRF = “L”
PSIF = PSRF = “L”
IF PLL
–
–
10
10
µA
Power saving current
Operating frequency
0.1*2
µA
*3
finIF
50
100
3
–
–
–
–
–
500
1200
40
MHz
MHz
MHz
dBm
dBm
Vp-p
*3
finRF
finRF
fosc
RF PLL
OSCIN
–
*8
finIF
PfinIF IF PLL, 50 Ω system
PfinRF RF PLL, 50 Ω system
–15
–15
0.5
+2
Input sensitivity
finRF
+2
OSCIN
VOSC
–
VCC
VCC ×0.7
“H” level input voltage
“L” level input voltage
VIH
Schmitt trigger input
–
–
–
Data,
Clock,
LE
+ 0.4
V
VCC × 0.3
– 0.4
VIL
Schmitt trigger input
–
“H” level input voltage
“L” level input voltage
VIH
–
–
VCC × 0.7
–
–
–
PSIF,PSRF
V
VIL
–
VCC × 0.3
*4
Data,
Clock,
“H” level input current
“L” level input current
IIH
–
–
–1.0
–1.0
–
–
+1.0
+1.0
µA
µA
LE,
*4
IIL
PSIF, PSRF
“H” level input current
“L” level input current
IIH
–
–
0
–
–
+100
0
OSCIN
*4
IIL
–100
“H” level output
voltage
VOH
VOL
VCC = 3.0 V, IOH = –1 mA
VCC = 3.0 V, IOL = 1 mA
VCC = 3.0 V, IDOH = –0.5 mA
VCC = 3.0 V, IDOL = 0.5 mA
VCC – 0.4
–
–
–
–
–
–
–
–
0.4
–
LD/fout
V
“L” level output
voltage
–
“H” level output
voltage
VDOH
VDOL
IOFF
VCC – 0.4
DoIF
DoRF
V
“L” level output
voltage
–
–
0.4
2.5
–1.0
–
High impedance
cutoff current
DoIF
DoRF
VCC = 3.0 V,
VOFF = 0.5 V to VCC – 0.5 V
nA
mA
“H” level output
current
*4
IOH
VCC = 3.0 V
VCC = 3.0 V
–
LD/fout
“L” level output
current
*4
IOL
1.0
(Continued)
6
MB15F02SL
(Continued)
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
VCC = 3.0 V,
CS bit = “H”
CS bit = “L”
CS bit = “H”
CS bit = “L”
–
–6.0
–
*4
“H” level output current
“L” level output current
IDOH
VDOH = VCC/2,
–
–
–
–1.5
6.0
–
–
–
Ta = +25°C
DoIF
DoRF
mA
VCC = 3.0 V,
VDOL= VCC/2,
Ta = +25°C
IDOL
1.5
*5
IDOL/IDOH
IDOMT
VDO = VCC/2
–
–
3
–
–
%
%
*6
Charge pump
current rate
vs VDO
IDOVD
0.5 V ≤ VDO ≤ VCC – 0.5 V
10
–40°C ≤ Ta ≤ +85°C,
VDO = VCC/2
*7
vs Ta
IDOTA
–
10
–
%
*1: Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.
*2: VCCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode.
*3: AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
*4: The symbol “–” (minus) means direction of current flow.
*5: VCC = 3.0 V, Ta = +25°C (|I3| – |I4|)/[(|I3| + |I4|)/2] × 100(%)
*6: VCC = 3.0 V, Ta = +25°C [(|I2| – |I1|)/2]/[(|I1| + |I2|)/2] × 100(%) (Applied to each IDOL, IDOH)
*7: VCC = 3.0 V, [|IDO(+85°C) – IDO(–40°C)|/2]/[|IDO(+85°C) + IDO(–40°C)|/2] × 100(%) (Applied to each IDOL, IDOH)
*8: Prescaler divided ratio
Charge pump current
finIF
fin
fin
VfinIF(min)
–15 dBm
–15 dBm
–10 dBm
–15 dBm
–15 dBm
–15 dBm
–10 dBm
16/17
1.5 mA mode
6.0 mA mode
50 MHz
50 MHz
500 MHz
300 MHz
500 MHz
300 MHz*
500 MHz
300 MHz*
500 MHz
300 MHz < fin
50 MHz fin
300 MHz < fin
8/9
1.5 mA mode
6.0 mA mode
50 MHz
fin
300 MHz < fin
* : VCC = 2.7 V to 3.6 V at 500 MHz,
VCC = 2.4 V to 3.6 V, Ta = –40°C to +85°C at fin < 500 MHz
I1
I3
I2
IDOL
IDOH
I4
I2
I1
0.5
Vcc/2
Vcc − 0.5
Vcc
Charge Pump Output Voltage (V)
7
MB15F02SL
■ FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation:
fVCO = {(M × N) + A} × fOSC ÷ R (A < N)
fVCO :
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
Reference oscillation frequency
M
N
A
:
:
:
fOSC :
R
:
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table 1. Control Bit
Control bit
Destination of serial data
CN1
L
CN2
L
The programmable reference counter for the IF-PLL
H
L
The programmable reference counter for the RF-PLL
L
H
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
H
H
Shift Register Configuration
Programmable Reference Counter
LSB
1
MSB
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
C
S
X
X
X
X
10 11 12 13 14
CN1,2
: Control bit
[Table 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)[Table 2]
T1, 2
CS
X
: Test purpose bit
: Charge pump currnet select bit
: Dummy bits (Set “0” or “1”)
[Table 3]
[Table 9]
NOTE: Data input with MSB first.
8
MB15F02SL
Programmable Counter
MSB
LSB
1
Data Flow
10 11 12 13 14 15 16 17 18 19 20 21 22 23
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
2
3
4
5
6
7
8
9
SWIF/ FCIF/
SWRF FCRF
CN1 CN2 LDS
CN1, CN2 : Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
[Table 1]
[Table 4]
[Table 5]
[Table 6]
A1 to A7
SWIF/SWRF : Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
: Divide ratio setting bits for the swallow counter (0 to 127)
FCIF/FCRF
LDS
: Phase control bit for the phase detector (IF: FCIF, RF: FCRF)
: LD/fout signal select bit
[Table 7]
[Table 8]
NOTE: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio
R14 R13 R12 R11 R10 R9
R8
R7
R6
R5
R4
R3
R2
R1
(R)
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
4
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
T1
L
T2
L
LD/fout pin state
Outputs frIF.
H
L
L
Outputs frRF.
Outputs fpIF.
Outputs fpRF.
H
H
H
9
MB15F02SL
Table 4. Binary 11-bit Programmable Counter Data Setting
Divide ratio
N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
(N)
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
4
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 5. Binary 7-bit Swallow Counter Data Setting
Divide ratio
A7
A6
A5
A4
A3
A2
A1
(A)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table 6. Prescaler Data Setting
SW = “H”
8/9
64/65
SW = “L”
16/17
IF-PLL
Prescaler
divide ratio
RF-PLL
128/129
Table 7. Phase Comparator Phase Switching Data Setting
FCIF, FCRF = “H”
FCIF, FCRF = “L”
(1)
DoIF, DoRF
fr > fp
fr = fp
H
Z
L
Z
VCO Output
Frequency
fr < fp
L
H
VCO polarity
(1)
(2)
(2)
LPF Output Voltage
Note: • Z = High-impedance
• Depending upon the VCO and LPF polarity, FC bit should be set.
Table 8. LD/fout Output Select Data Setting
LDS
H
LD/fout output signal
fout (frIF/frRF, fpIF/fpRF) signals
LD signal
L
10
MB15F02SL
Table 9. Charge Pump Current Setting
CS
H
Current value
±6.0 mA
L
±1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: • When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
• PS pin must be set at “L” for Power-ON.
OFF
ON
tv ≥ 1 µs
VCC
Clock
Data
LE
tps ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = “L” (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.
11
MB15F02SL
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit Invalid data
LSB
Data
MSB
Clock
LE
t1
t2
t3
t6
t7
t4
t5
On rising edge of the clock, one bit of the data is transfered into the shift register.
Parameter
Min. Typ. Max. Unit
Parameter
Min. Typ. Max. Unit
t1
t2
t3
t4
20
20
30
30
–
–
–
–
–
–
–
–
ns
ns
ns
ns
t5
t6
t7
100
20
–
–
–
–
–
–
ns
ns
ns
100
Note: LE should be “L” when the data is transferred into the shift register.
12
MB15F02SL
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/frRF
fpIF/fpRF
tWU
tWL
LD
(FC bit = High)
DOIF/DORF
(FC bit = Low)
DOIF/DORF
LD Output Logic Table
IF-PLL section
RF-PLL section
Locking state/Power saving state
Unlocking state
LD output
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes:• Phase error detection range = –2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc: i. e. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc: i. e. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F02SL
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
VCCIF
0.1 µF
S.G.
1000 pF
1000 pF
50 Ω
50 Ω
S.G.
DOIF
PSIF LD/fout
VCCIF
finIF
4
GNDIF OSCIN
GNDRF
8
7
6
5
3
2
1
9
10
11
12
13
14
LE
15
16
DORF
PSRF
XfinRF
Data
Clock
VCCRF
finRF
S.G.
1000 pF
Controller (divide ratio setting)
VCCRF
50 Ω
1000 pF
0.1 µF
Note: SSOP-16
14
MB15F02SL
■ TYPICAL CHARACTERISTICS
1. fin input impedance
RF-PLL input sensitivity − Input frequency
Ta = +25 °C
10
5
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
500
1000
1500
2000
Input frequency finRF (MHz)
IF-PLL input sensitivity − Input frequency
Ta = +25 °C
10
5
0
−5
SPEC
−10
−15
−20
−25
−30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
100
200
300
400
500
600
700
800
900
1000
Input frequency finIF (MHz)
15
MB15F02SL
2. OSCIN input sensitivity
Input sensitivity − Input frequency
Ta = +25 °C
SPEC
10
0
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
20
40
60
80
100
120
140
160
180
200
220
240
Input frequency fOSC (MHz)
16
MB15F02SL
3. Do output current (RF-PLL)
• 1.5 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
• 6.0 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
17
MB15F02SL
4. Do output current (IF-PLL)
• 1.5 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
• 6.0 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
18
MB15F02SL
5. fin input impedance
finRF input impedance
1 : 351.03 Ω
−699.34 Ω
100 MHz
33.18 Ω
−208.83 Ω
400 MHz
2 :
3 :
4 :
12.895 Ω
−94.023 Ω
800 MHz
10.543 Ω
−48.268 Ω
1200 MHz
1
2
4
3
START
100.000 000 MHz
STOP 1 200.000 000 MHz
finIF input impedance
1 : 859.06 Ω
−1.0314 kΩ
50 MHz
92.656 Ω
−413.59 Ω
200 MHz
2 :
3 :
4 :
28.531 Ω
−204.21 Ω
400 MHz
20.859 Ω
−159.23 Ω
500 MHz
1
2
4
3
START
50.000 000 MHz
STOP 500.000 000 MHz
19
MB15F02SL
6. OSCIN input impedance
OSCIN input impedance
1 : 9.0005 kΩ
−3.281 kΩ
3 MHz
3.9238 kΩ
2 :
−4.8648 kΩ
10 MHz
1.4543 kΩ
−3.45 kΩ
20 MHz
3 :
4
3
2
4 :
1
395.5 Ω
−1.8983 kΩ
40 MHz
START
3.000 000 MHz
STOP
40.000 000 MHz
20
MB15F02SL
■ APPLICATION EXAMPLE
VCO
LPF
OUTPUT
3 V
0.1 µF
1000 pF
1000 pF
from controller
Clock
16
Data
15
XfinRF
11
PSRF
10
DoRF
9
LE
14
finRF
13
VCCRF
12
MB15F02SL
1
2
3
4
5
6
7
8
GNDRF OSCIN GNDIF
finIF
VCCIF
LD/fout
PSIF
DoIF
3 V
LockDet
1000 pF
1000 pF
0.1 µF
TCXO
OUTPUT
VCO
LPF
Note: SSOP-16
■ USAGE PRECAUTIONS
(1) VCCRF must equal VccIF.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF and VCCIF tokeep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
21
MB15F02SL
■ ORDERING INFORMATION
Part number
Package
Remarks
16-pin, plastic SSOP
(FPT-16P-M05)
MB15F02SLPFV1
16-pad, plastic BCC
(LCC-16P-M04)
MB15F02SLPV1
22
MB15F02SL
■ PACKAGE DIMENSIONS
16-pin, Plastic SSOP
(FPT-16P-M05)
Note 1 ) * : These dimensions do not include resin protrusion.
Note 2 ) Pins width and pins thickness include plating thickness.
*
5.00±0.10(.197±.004)
0.17±0.03
(.007±.001)
16
9
*
4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.25 –+00..1200
.049 –+..000048
(Mounting height)
1
8
LEAD No.
"A"
0.65(.026)
0.24±0.08
(.009±.003)
M
0.13(.005)
0~8°
0.10±0.10
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
0.25(.010)
0.45/0.75
(.018/.030)
0.10(.004)
Dimensions in mm (inches)
C
1999 FUJITSU LIMITED F16013S-3C-5
(Continued)
23
MB15F02SL
(Continued)
16-pad, Plastic BCC
(LCC-16P-M04)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.65(.026)
0.325±0.10
(.013±.004)
TYP
14
9
9
14
0.80(.031)
REF
INDEX AREA
4.20±0.10
(.165±.004)
3.25(.128)
TYP
1.55(.061)
REF
"B"
"A"
0.40±0.10
(.016±.004)
0.075±0.025
(.003±.001)
(Stand off)
1.725(.068)
REF
1
6
6
1
Details of "A" part
0.75±0.10
Details of "B" part
0.60±0.10
(.024±.004)
(.030±.004)
0.05(.002)
0.40±0.10
0.60±0.10
(.016±.004)
(.024±.004)
C
Dimensions in mm (inches)
1999 FUJITSU LIMITED C16015S-1C-1
24
MB15F02SL
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
All Rights Reserved.
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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Tel: +81-44-754-3763
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
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The contents of this document may not be reproduced or copied
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(such as aerospace systems, atomic energy controls, sea floor
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Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
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Any semiconductor devices have inherently a certain rate of
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such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
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Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
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F0001
FUJITSU LIMITED Printed in Japan
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