MB15F02SLPFV1-ER [FUJITSU]
PLL Frequency Synthesizer, BICMOS, PDSO16, PLASTIC, SSOP-16;
| 型号： | MB15F02SLPFV1-ER |
| 厂家： | 
FUJITSU |
| 描述： | PLL Frequency Synthesizer, BICMOS, PDSO16, PLASTIC, SSOP-16 信息通信管理 光电二极管 |
| 文件： | 总39页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB15FxxSL Series
Dual PLL Frequency Synthesizers
with On-Chip Prescalers
Packages
Description
The Fujitsu FxxSL series dual PLLs are serial input frequency
synthesizers operating up to 2.5 GHz. They have built-in
dual-modulus prescalers enabling pulse swallow operation.
The latest advanced BiCMOS technology is used resulting in a
super low supply current. A refined charge pump design
(Fujitsu’s Super Charger) provides fast tuning along with low
spurious noise and phase noise characteristics. The F-series is
ideally suited for digital mobile communications, including
GSM, DCS1800, PCS1900, IS-136, IS-95: and ISM applications.
16-pin plastic SSOP,
FPT-16P-M05
16-pin plastic BCC,
LCC-16P-M06
Features
• Plastic 16-pin SSOP and 16-pin BCC packages
• MB15F02SL and MB15F03SL: RF and IF PLLs
• MB15F07SL and MB15F08SL: Dual RF PLLs
• Very low spurious and phase noise characteristics
• Low operating voltage: 2.4 to 3.6 volts
• Low operating current: 3.0 to 7.5 mA (typical)
• Power-saving current: 0.1µA (typical)
• Wide operating temperature: –40 to +85°C
• Reference counter:
– 14-bit programmable divider: 3 to 16383
• 18-bit programmable divider:
– Binary 7-bit swallow counter: 0 to 127
– Binary 11-bit programmable counter: 3 to 2047
• Software selectable charge pump current (±1.5 or ±6.0 mA)
• Evaluation Kits available
Parameter
MB15F02SL
MB15F03SL
MB15F07SL
MB15F08SL
RF Frequency of Operation, max.
IF/RF Frequency of Operation, max
Low Power Supply Voltage
1.2 GHz
500 MHz
2.7V
1.75 GHz
600 MHz
2.7V
1.1 GHz
1.1 GHz
2.7V
2.5 GHz
1.1 GHz
2.7V
Low Power Supply Current
3.0 mA
5.0 mA
5.0 mA
7.0 mA
RF = 64/65 or 128/129,
IF = 8/9 or 16/17
RF = 64/65 or 128/129
RF = 64/65 or 128/129
Rx = 32/33 or 64/65
Tx = 16/17 or 32/33
Prescaler Divide Ratios
Power-Saving Function
0.1µA typ.
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Table of Contents
Pin Descriptions: MB15F02SL, MB15F03SL........................................................................................................................... 2
Block Diagram: MB15F02SL, MB15F03SL............................................................................................................................. 3
Pin Descriptions: MB15F07SL, MB15F08SL ......................................................................................................................... 4
Block Diagram: MB15F07SL, MB15F08SL............................................................................................................................. 5
Absolute Maximum Ratings ................................................................................................................................................... 6
Recommended Operating Conditions....................................................................................................................................... 6
Handling Precautions..................................................................................................................................................... 6
Electrical Characteristics ....................................................................................................................................................... 7
Measurement Circuit (f , OSC Input Sensitivity)................................................................................................................... 9
IN
IN
Typical Electrical Characteristics: MB15F02SL ...................................................................................................................... 10
Reference Information: MB15F02SL .............................................................................................................................. 13
Typical Electrical Characteristics: MB15F03SL ...................................................................................................................... 14
Reference Information: MB15F03SL .............................................................................................................................. 17
Typical Electrical Characteristics: MB15F07SL ...................................................................................................................... 18
Reference Information: MB15F07SL .............................................................................................................................. 21
Typical Electrical Characteristics: MB15F08SL ...................................................................................................................... 22
Reference Information: MB15F08SL .............................................................................................................................. 25
Functional Descriptions ...................................................................................................................................................... 26
Serial Data Input ......................................................................................................................................................... 26
Table 1. Control Bits .................................................................................................................................................... 26
Shift Register Configuration for the Programmable Reference Counter.......................................................................... 26
Shift Register Configuration for the Programmable Counter........................................................................................ 27
Table 2. Binary 14-Bit Programmable Reference Counter Data Setting ................................................................................ 27
Table 3.Test Purpose Bit Setting .................................................................................................................................... 27
Table 4. Binary 11-Bit Programmable Counter Data Setting .............................................................................................. 28
Table 5. Binary 7-Bit Swallow Counter Data Setting......................................................................................................... 28
Table 6. Prescaler Data Setting for MB15F02SL, MB15F03SL .......................................................................................... 28
Prescaler Data Setting for MB15F07SL ................................................................................................................... 28
Prescaler Data Setting for MB15F08SL.................................................................................................................... 28
Table 7. Phase Comparator Phase Switching Data Setting.................................................................................................. 29
Table 8. LD/f
Output Select Data Setting................................................................................................................... 29
OUT
Table 9. Charge Pump Current Setting............................................................................................................................ 29
Power Saving Mode (Intermittent Mode Control Circuit) ........................................................................................................ 30
Table 10. Power-Save Pin Setting.................................................................................................................................... 30
Table 11. Power-Save Internal Shutdown Logic ................................................................................................................ 30
Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Serial Data InputTiming......................................................................................................................................................31
Table 12.Timing Parameters ..........................................................................................................................................31
Phase Detector Output Waveform ..........................................................................................................................................32
Table 13. LD Output LogicTable ....................................................................................................................................32
Application Example ...........................................................................................................................................................33
Useage Precautions..............................................................................................................................................................34
Ordering Information ..........................................................................................................................................................34
Package Dimensions ............................................................................................................................................................35
Fujitsu Microelectronics, Inc.
1
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Pin Descriptions: MB15F02SL, MB15F03SL
Pin No.
Pin Name
I/O
Descriptions
SSOP
BCC
16
1
1
2
3
GND
OSC
–
I
Ground for RF-PLL section
RF
Programmable reference divider input. TCXO should be connected via an AC coupling capacitor.
Ground for IF-PLL section
IN
2
GND
–
IF
Prescaler input pin for IF-PLL
Connection to an external VCO should be via AC coupling.
4
5
3
4
fin
I
IF
Vcc
–
Power supply voltage input pin for IF-PLL section
IF
Lock detect signal output (LD)/phase comparator monitoring output (f
Output signal is selected by LDS bit in the serial data.
LDS bit = “H” outputs fout signal. LDS bit = “L” ;outputs LD signal.
)
OUT
6
7
5
6
LD/f
O
I
OUT
Power-saving mode control for IF-PLL section. This pin must be set at “L” during Power-ON.
(Open is prohibited.)
PS
Do
IF
PS = “H” sets normal mode. PS = “L” sets power-saving mode.
IF
IF
Charge pump output for IF-PLL section
Phase characteristics of phase detector can be selected via programming of the FC-bit.
8
9
7
8
O
O
IF
Charge pump output for RF-PLL section
Phase characteristics of phase detector can be selected via programming of the FC-bit.
Do
PS
RF
Power-saving mode control for RF-PLL section. This pin must be set at “L” during Power-ON.
(Open is prohibited.)
10
9
I
RF
PS = “H” sets normal mode. PS = “L” sets power-saving mode.
RF
RF
Prescaler complementary input for RF-PLL section
Pin should be grounded via a capacitor.
11
12
13
10
11
12
Xfin
I
–
I
RF
Power supply voltage input pin for RF-PLL section, shift register and oscillator input buffer
When power is OFF, latched data of RF-PLL is lost.
Vcc
fin
RF
Prescaler input pin for RF-PLL
Connection to an external VCO should be via AC coupling.
RF
Load enable signal input (with a Schmitt trigger input buffer)
14
13
LE
I
When the LE bit is set “H”, data in shift register is transferred to corresponding latch according to control bit in the
serial data.
Serial data input (with a Schmitt trigger input buffer)
15
16
14
15
Data
I
I
Data is transferred to corresponding latch (IF-reference counter, IF-program counter, RF-reference counter, RF-program
counter) according to control bit in the serial data.
Clock input for the 23-bit shift register (with a Schmitt trigger input buffer)
One bit of data is shifted into shift register on a rising edge of the clock.
Clock
GNDRF Clock
16 15
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDRF
Clock
Data
LE
OSCIN
GNDIF
finIF
OSCIN
GNDIF
finIF
1
14
Data
LE
2
3
4
5
6
13
12
11
10
9
finRF
finRF
TOP
VIEW
TOP
VIEW
VCCIF
VCCRF
VCCIF
VCCRF
LD/fout
PSIF
XfinRF
PSRF
LD/fout
PSIF
XfinRF
PSRF
7
8
DOIF
DORF
DOIF DORF
LCC-16P-M04
FPT-16P-M05
2
Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Block Diagram: MB15F02SL, MB15F03SL
VCCIF GNDIF
5 (4) 3 (2)
Intermittent
mode control
(IF-PLL)
PSIF 7
3-bit latch
7-bit latch
11-bit latch
(6)
fpIF
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programmable
counter (IF-PLL)
Charge
pump
(IF-PLL)
Phase
comp.
(IF-PLL)
8
(7)
DoIF
Current
Switch
LDS SWIF FCIF
Lock
Det.
(IF-PLL)
Prescaler
(IF-PLL)
8/9, 16/17
finIF 4
(3)
1-bit latch
2-bit latch
T1 T2
14-bit latch
LDIF
Binary 14-bit
programmable ref.
counter (IF-PLL)
C/P setting
current CP
frIF
OSCIN 2
(1)
Selector
AND
frRF
LD
frIF
frRF
fpIF
fpRF
Binary 14-bit
C/P setting
current CP
programmable ref.
counter (RF-PLL)
T1 T2
6
(5)
LD/
fOUT
OR
2-bit latch
14-bit latch
1-bit latch
(12)
finRF 13
Prescaler
(RF-PLL)
Lock
Det.
(RF-PLL)
XfinRF 11
(10)
64/65, 128/129
Charge
Phase
comp.
(RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
9
(8)
Current
switch
DoRF
pump
LDS SWRF FCRF
Intermittent
mode control
(RF-PLL)
(RF-PLL)
PSRF 10
(9)
fpRF
3-bit latch
7-bit latch
11-bit latch
Schmitt
circuit
LE 14
(13)
Latch selector
(14)
Data 15
Schmitt
circuit
C
N
1
C
N
2
23-bit shift register
Schmitt
circuit
Clock 16
(15)
(11)
(16)
1
12
: SSOP
: BCC
)
GNDRF
VCCRF
(
Fujitsu Microelectronics, Inc.
3
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Pin Descriptions: MB15F07SL, MB15F08SL
Pin No.
Pin name
I/O
Descriptions
SSOP
BCC
16
1
1
2
3
GND
–
I
Ground for PLL2 section
2
OSC
Programmable reference divider input. TCXO should be connected via an AC coupling capacitor.
Ground for PLL1 section
IN
2
GND
–
1
Prescaler input pin for PLL1
Connection to an external VCO should be via AC coupling.
4
5
3
4
fin
I
1
V
–
Power supply voltage input pin for PLL1 section
CC1
Lock detect signal output (LD)/phase comparator monitoring output (f
Output signal is selected by LDS bit in the serial data.
)
OUT
6
7
5
6
LD/fout
O
I
LDS bit = “H” outputs f signal. LDS bit = “L” outputs LD signal.
OUT
Power-saving mode control for PLL1 section. This pin must be set at “L” during Power-ON.
(Open is prohibited.)
PS
1
PS = “H” sets normal mode. PS = “L” sets power-saving mode.
1
1
Charge pump output for PLL1 section
Phase characteristics of phase detector can be selected via programming of the FC-bit.
8
9
7
8
Do
Do
O
O
1
2
Charge pump output for PLL2 section
Phase characteristics of phase detector can be selected via programming of the FC-bit.
Power-saving mode control for PLL2 section. This pin must be set at “L” during Power-ON.
(Open is prohibited.)
10
9
PS
I
2
PS = “H” sets normal mode. PS = “L” sets power-saving mode.
2
2
Prescaler complementary input for PLL2 section
Pin should be grounded via a capacitor.
11
12
13
14
10
11
12
13
Xfin
I
–
I
2
Power supply voltage input pin for PLL 2 section, shift register and oscillator input buffer
When power is OFF, latched data of PLL2 is lost.
V
CC2
Prescaler input pin for PLL2
Connection to an external VCO should be via AC coupling.
fin
2
Load enable signal input (with a Schmitt trigger input buffer)
When LE bit is set “H”, data in shift register is transferred to corresponding latch according to control bit in serial data.
LE
I
Serial data input (with a Schmitt trigger input buffer)
15
16
14
15
Data
I
I
Data is transferred to corresponding latch (PLL1-reference counter, PLL1-program counter, PLL2-reference counter,
PLL2-program counter) according to control bit in the serial data.
Clock input for 23-bit shift register (with a Schmitt trigger input buffer)
One bit of data is shifted into shift register on a rising edge of the clock.
Clock
GND2 Clock
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
2
Clock
Data
LE
OSCIN
16 15
OSCIN
1
2
3
4
5
6
14
13
12
11
10
9
Data
LE
GND
1
1
GND
1
1
fin
fin2
fin
fin2
TOP
VIEW
TOP
VIEW
V
CC1
VCC2
V
CC1
VCC2
LD/fout
PS
Xfin
2
LD/fout
PS
Xfin
2
1
PS
2
7
8
1
PS
2
DO1
DO2
DO1 DO2
LCC-16P-M04
FPT-16P-M05
4
Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Block Diagram: MB15F07SL, MB15F08SL
VCCIF GNDIF
(4)
5
3 (2)
Intermittent
mode control
(IF-PLL)
PSIF 7
3-bit latch
7-bit latch
11-bit latch
(6)
fpIF
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programmable
counter (IF-PLL)
Charge
pump.
(IF-PLL)
Phase
8
(7)
DoIF
Current
Switch
LDS SWIF FCIF
comp.
(IF-PLL)
Lock
Det.
(IF-PLL)
Prescaler
(IF-PLL)
fin1/RXIN 4
(3)
F07: 64/65,
128/129
1-bit latch
2-bit latch
T1 T2
14-bit latch
F08: 16/17,
32/33
LDIF
Binary 14-bit
programmable ref.
counter (IF-PLL)
C/P setting
current
frIF
OSCIN 2
(1)
Selector
AND
frRF
LD
frIF
frRF
fpIF
fpRF
Binary 14-bit
C/P setting
current
programmable ref.
counter (RF-PLL)
T1 T2
6
(5)
LD/
fOUT
OR
2-bit latch
14-bit latch
1-bit latch
(12)
fin2/TXIN 13
Prescaler
(RF-PLL)
Lock
Det.
(RF-PLL)
XfinRF 11
(10)
F07: 64/65,
128/129
F08: 32/33,
64/65
Charge
Phase
comp.
(RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
9
(8)
Current
Switch
DoRF
pump.
LDS SWRF FCRF
3-bit latch
(RF-PLL)
Intermittent
mode control
(RF-PLL)
PSRF 10
(9)
fpRF
7-bit latch
11-bit latch
Schmitt
circuit
LE 14
(13)
Latch selector
(14)
Data 15
Schmitt
circuit
C
N
1
C
N
2
23-bit shift register
Schmitt
circuit
Clock 16
(15)
(16)
1
VCCRF GNDRF
(11)12
: SSOP
: BCC
)
(
Fujitsu Microelectronics, Inc.
5
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remark
Power supply voltage
Input voltage
V
V
V
–0.5 to +4.0
V
CC
I
–0.5 to V +0.5
V
CC
Output voltage
–0.5 to V
V
O
CC
I
I
–10 to +10
–25 to +25
–55 to +125
mA
mA
°C
Except D
O
O
Output Current
D output
O
DO
Storage temperature
T
STG
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these
ratings.
Recommended Operating Conditions
Value
Parameter
Symbol
Unit
Min.
2.7
Typ.
3.0
–
Max.
Power supply voltage
Input voltage
V
V
3.6
V
CC
I
GND
–40
V
V
CC
Operating temperature
Ta
–
+85
°C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these
ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in
device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed
conditions are advised to contact their Fujitsu representative beforehand.
Handling Precautions
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded.
Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
6
Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Electrical Characteristics
Device Specifications
V = 2.4 to 3.6V, Ta = –40 to +85°C
CC
MB15F02SL
Parameter
Symbol
MB15F03SL
Symbol
MB15F07SL
MB15F08SL
*1
*1
I
1.2 mA
1.8 mA
1.2 mA
2.3 mA
I
I
I
I
2.5 mA
2.5 mA
2.6 mA
4.4 mA
CCIF
CCPLL1
Power supply current
*1
*1
I
I
I
CCRF
CCPLL2
*2
*2
*2
*3
0.1µA
0.1µA
0.1µA
0.1µA
PSIF
PS
PSPLL1
PSPLL2
Power-saving current
Operating frequency
*2
0.1µA
0.1µA
0.1µA
0.1µA
RF
*3
fin
fin
50 - 500 MHz
0.1 - 1.2 GHz
3 - 40 MHz
50 - 600 MHz
0.1 - 1.75 GHz
3 - 40 MHz
fin
,
PLL1
Tx
0.1 - 1.1 GHz
0.1 - 1.1 GHz
3 - 40 MHz
0.1 - 1.1 GHz
0.4 - 2.5 GHz
3 - 40 MHz
IF
RF
fin , Rx
PLL2
*3
*3
OSCin
OSCin
General Specifications
Value
Typ.
Parameter
Symbol
Condition
Unit
Min.
Max.
*5,*6,*7,*8
–15
50Ω load system
fin
fin
Pfin
Pfin
–
–
+2
dBm
IF, PLL1, Tx
RF, PLL2, Rx
IF, PLL1, Tx
RF, PLL2, Rx
(Refer to measurement circuit)
(FO8-10)
Input sensitivity
50Ω load system
(Refer to measurement circuit)
*5,*6,*7,*8
–15
+2
dBm
Vp-p
OSC
V
V
V
0.5
× 0.7
–
–
–
–
–
–
–
–
–
–
–
V
IN
OSC
CC
–
–
–
–
–
–
V
CC
IH
IL
Data, Clock,
LE, PS, ZC
Input voltage
Input current
V
–
V
× 0.3
CC
*4
I
I
I
I
–1.0
–1.0
0
+1.0
+1.0
+100
0
IH
*4
Data, Clock,
LE, PS
µA
µA
V
IL
IH
*4
OSC
IN
–100
IL
V
V
V
V
V
= 3.0V, I = –1 mA
V
–0.4
CC
OH
CC
CC
CC
CC
OH
LD/f
OUT
VOL
= 3.0V, I = 1 mA
–
0.4
Output voltage
OL
V
V
= 3.0V, I = –1 mA
V
–0.4
CC
DOH
DOL
OH
Do
Do
V
= 3.0V, I = 1 mA
–
0.4
2.5
OL
V
V
= 3.0V
High impedance cutoff
current
CC
I
–
–
nA
OFF
= .5V to Vcc-0.5V
OFF
*4
V
V
= 3.0V
= 3.0V
= 3.0 ,
I
I
–1.0
–
–
–
–
1.0
–
mA
mA
mA
CC
CC
OH
LD/fout
OL
V
V
CS bit = “H”
CS bit = “L”
CS bit = “H”
CS bit = “L”
–
–6.0
CC
Output current
*4
I
I
= V /2,
DOH
DOH
CC
–
–
–
–1.5
6.0
–
–
–
mA
mA
mA
Ta = +25°C
Do
V
V
= 3.0V,
CC
= V /2,
DOL
DOL CC
1.5
Ta = +25°C
*9
V
= V /2
I
/I
I
I
–
–
3
–
–
%
%
DO
CC
DOL DOH
DOMT
*10
0.5V ≤ V ≤ V – 0.5V
Charge pump current
characteristics
vs V
10
DO
CC
DO
DOVD
*11
–40°C ≤ Ta ≤ +85°C,
= V /2
vs Ta
Note: See footnotes on the following page.
I
–
10
–
%
DOTA
V
DO
CC
Fujitsu Microelectronics, Inc.
7
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Electrical Characteristics
*1 Conditions; fosc = 12 MHz, Ta = +25°C, in locking state. V
= V
= 2.7 V
CCRF
CCIF
*2 V
= V
= 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode.
CCIF
CCRF
*3 AC coupling. 1000pF capacitor is connected under the condition of minimum operating frequency.
*4 The symbol “–” (minus) means direction of current flow.
*5 MB15F02SL IF Input Sensitivity:
Prescaler Divided Ratio
Charge Pump Current fin Operating Frequency
Pfin (min)
IF
IF
16/17
1.5mA mode
6.0mA mode
50MHz fin 500MHz
50MHz fin 300MHz
300MHz < fin 500MHz
50MHz fin 300MHz*
300MHz < fin 500MHz
50MHz fin 300MHz*
300MHz < fin 500MHz
–15dBm
–15dBm
–10dBm
–15dBm
–15dBm
–15dBm
–10dBm
8/9
1.5mA mode
6.0mA mode
* V = 2.7V to 3.6V at 500MHz
CC
V
= 2.4V to 3.6V, Ta = –40°C to +85°C at fin < 500MHz
CC
*6
MB15F03SL IF Input Sensitivity:
Prescaler Divided Ratio
16/17
Charge Pump Current fin Operating Frequency
Pfin (min)
IF
IF
1.5mA mode
6.0mA mode
50MHz fin 600MHz
50MHz fin 300MHz
300MHz < fin 600MHz
50MHz fin 300MHz
300MHz < fin 600MHz*
50MHz fin 300MHz
300MHz < fin 600MHz*
–15dBm
–15dBm
–10dBm
–15dBm
–15dBm
–15dBm
–10dBm
8/9
1.5mA mode
6.0mA mode
* V = 3.0V to 3.6V at 600MHz
CC
*7
MB15F07SL RF Input Sensitivity:
Pfin(min)
Prescaler Divided Ratio
Charge Pump Current
fin
–10dBm
–10dBm
–15dBm
–15dBm
1
64/65
1.5mA mode
6.0mA mode
1.5mA mode
6.0mA mode
128/129
–15dBm
–10dBm
–15dBm
–15dBm
64/65
1.5mA mode
6.0mA mode
1.5mA mode
6.0mA mode
fin
2
128/129
*8
MB15F08SL RF Input Sensitivity:
fin operating frequency
Pfin(min)
I1
I3
I2
IDOL
fin Tx 100MHz fin 1100MHz
–10dBm
fin Rx 400MHz fin 2200MHz
2200MHz fin 2500MHz
–15dBm
–10dBm
I4
I2
IDOH
I1
Charge Pump Characteristics (see diagram at right.)
0.5
Vcc/2
Vcc − 0.5 V Vcc
*9
*10
*11
V
V
V
= 3.0 V, Ta = +25°C (|I | – |I |)/[(|I | + |I |)/2] x 100(%)
3 4 3 4
CC
CC
CC
Charge Pump Output Voltage (V)
= 3.0 V, Ta = +25°C [(|I | – |I |)/2]/[(|I | + |I |)/2] x 100(%) (Applied to each I , I
)
2
1
1
2
DOL DOH
|/2] x 100(%) (Applied to each I , I
= 3.0 V, [|I
– I
|/2]/[|I
+ I
)
DO(85°C) DO(–40°C)
DO(85°C) DO(–40°C)
DOL DOH
8
Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Measurement Circuit (For Measuring Input Sensitivity of f and OSC )
IN
IN
fout
Oscilloscope
Vcc
1000 pF
0.1µF
Signal Generator
50Ω
1000 pF
Signal Generator
GND
8
9
7
6
5
3
2
1
4
50Ω
MB15FXXSL
10
11
12
13 14
15
16
Signal Generator
1000 pF
Controller (sets
the divide ratio)
50Ω
Vcc
1000 pF
0.1µF
Note: 16-PIN SSOP
Fujitsu Microelectronics, Inc.
9
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F02SL
Input Sensivity of f (RF) Versus Input Frequency
IN
RF-PLL input sensitivity − Input frequency
Ta = +25 °C
10
5
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
500
1000
1500
2000
Input frequency finRF (MHz)
Input Sensivity of f (IF) Versus Input Frequency
IN
IF-PLL input sensitivity − Input frequency
Ta = +25 °C
10
5
0
−5
SPEC
−10
−15
−20
−25
−30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
100
200
300
400
500
600
700
800
900
1000
Input frequency finIF (MHz)
Input Sensivity of OSC (IF) versus Input Frequency
IN
Input sensitivity − Input frequency
Ta = +25 °C
10
0
SPEC
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
20
40
60
80
100
120
140
160
180
200
220
240
Input frequency fOSC (MHz)
10 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Typical Electrical Characteristics: MB15F02SL
finRF input impedance
Input Impedance
1
2
3
:
:
:
351.03
−699.34
100 MHz
Ω
Ω
33.18
−208.83
400 MHz
Ω
Ω
12.895
−94.023
Ω
Ω
800 MHz
finIF Pin
4 :
10.543 Ω
−48.268 Ω
1200 MHz
1
2
4
3
START
100.000 000 MHz
STOP 1 200.000 000 MHz
finIF input impedance
1
2
3
:
859.06
Ω
Ω
−1.0314 k
50 MHz
92.656
−413.59
200 MHz
Ω
Ω
:
:
28.531
−204.21
Ω
Ω
400 MHz
finRF Pin
4 :
20.859 Ω
−159.23 Ω
500 MHz
1
2
4
3
START
50.000 000 MHz
STOP 500.000 000 MHz
OSCIN input impedance
1 : 9.0005 kΩ
−3.281 kΩ
3 MHz
3.9238 kΩ
2 :
−4.8648 kΩ
10 MHz
1.4543 kΩ
−3.45 kΩ
20 MHz
3 :
4
OSCIN Pin
3
2
4 :
1
395.5 Ω
−1.8983 kΩ
40 MHz
START
3.000 000 MHz
STOP
40.000 000 MHz
Fujitsu Microelectronics, Inc. 11
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F02SL
Conditions: Ta = +25°C
V
CC= 3.0V
Do ouput current: 1.5 mA mode
RF
IF
VDO − IDO
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
Ta = +25 °C
VCC = 3.0 V
10.00
10.00
2.000
/div
2.000
/div
IDOL
IDOL
0
0
IDOH
IDOH
−10.00
−10.00
0
4.800
0
4.800
.6000/div
Change pump output voltage VDO (V)
.6000/div
Change pump output voltage VDO (V)
Do output current: 6.0 mA mode
RF
IF
VDO − IDO
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
Ta = +25 °C
VCC = 3.0 V
10.00
10.00
IDOL
IDOL
2.000
/div
2.000
/div
0
0
IDOH
IDOH
−10.00
−10.00
0
4.800
0
4.800
.6000/div
Change pump output voltage VDO (V)
.6000/div
Change pump output voltage VDO (V)
12 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Reference Information: MB15F02SL
Test Circuit
f
K
VCO= 903MHz
= 61MHz/V
fr = 200kHz
OSC= 10MHz
LPF
V
CC= V
P = 3.0V
VVCO= 2.3V
Ta = +25°C
CP: 6mA mode
V
S.G
OSCIN
fin
f
LPF
Do
1.6kΩ
300Ω
0.22µF
.015µF
4700pF
Spectrum
Analyzer
VCO
Typical plots measured with the test circuit are shown below. The plots show lock up time, phase noise and reference leakage.
RF PLL Phase Noise
RF PLL Reference Leakage
@ max within loop band = -78.8 dBc/Hz
@ 200 kHz offset = -92.8 dBc
-92.8 dBc
RF PLL Lock Up Time = 437µs
RF PLL Lock Up Time = 456µs
890.000 MHz → 916.000 MHz, within ± 1kHz)
(916.000 MHz → 890.000 MHz, within ± 1kHz)
Fujitsu Microelectronics, Inc. 13
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F03SL
Input Sensivity of f (RF) Versus Input Frequency
IN
RF PLL input sensitivity − Input frequency
10
5
Ta = +25 °C
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
200
400
600
800
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800
Input frequency finRF (MHz)
Input Sensivity of f (IF) Versus Input Frequency
IN
IF PLL input sensitivity − Input frequency
10
5
Ta = +25 °C
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
200
400
600
800
1000
Input frequency finIF (MHz)
Input Sensivity of OSC Versus Input Frequency
IN
Input sensitivity − Input frequency
10
0
Ta = +25 °C
SPEC
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
20
40
60
80
100
120
140
160
180
200
220
240
Input frequency fOSC (MHz)
14 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Typical Electrical Characteristics: MB15F03SL
Input Impedance
finRF input impedance
1
2
3
:
23.281
Ω
Ω
−162.47
500 MHz
11.291
Ω
Ω
:
−59.674
1 GHz
16.957
Ω
Ω
:
−13.534
1.5 GHz
4
finIF Pin
4 : 22.478 Ω
−3.9443 Ω
1.8 GHz
3
1
2
START 100.000 000 MHz
STOP 1 800.000 000 MHz
finIF input impedance
1 : 897.31 Ω
−1.0259 kΩ
50 MHz
98.781 Ω
2 :
−429.3
Ω
200 MHz
29.75
−216.69 Ω
Ω
3 :
finRF Pin
400 MHz
1
4 : 16.781 Ω
−139.35 Ω
600 MHz
2
4
3
START 50.000 000 MHz
STOP 600.000 000 MHz
OSCIN input impedance
1 :
9.451 kΩ
−3.1875 kΩ
3 MHz
2 :4.7255 kΩ
−5.1685 kΩ
10 MHz
1.6918 kΩ
3 :
−3.8045 kΩ
20 MHz
OSCIN Pin
4
1
3
2
4 : 463.75 Ω
−2.1069 kΩ
40 MHz
START 3.000 000 MHz
STOP 40.000 000 MHz
Fujitsu Microelectronics, Inc. 15
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F03SL
Conditions: Ta = +25°C
VCC= 3.0V
Do output current: 1.5 mA mode
IF
RF
IDO − VDO
VDO − IDO
Ta = +25 °C
CC = 3.0 V
Ta = +25 °C
VCC = 3.0 V
10.00
10.00
V
2.000
/div
2.000
/div
IDOL
I
DOL
0
0
IDOH
I
DOH
−10.00
−10.00
0
4.800
.6000/div
0
4.800
.6000/div
Charge pump output voltage VDO (V)
Change pump output voltage VDO (V)
Do output current: 6.0 mA mode
IF
RF
VDO − IDO
IDO − VDO
Ta = +25 °C
CC = 3.0 V
Ta = +25 °C
VCC = 3.0 V
10.00
10.00
V
IDOL
I
DOL
2.000
/div
2.000
/div
0
0
IDOH
I
DOH
−10.00
−10.00
0
4.800
.6000/div
0
4.800
.6000/div
Change pump output voltage VDO (V)
Charge pump output voltage VDO (V)
16 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Reference Information: MB15F03SL
Test Circuit
f
VCO= 1775MHz
VCC= VP = 3.0V
VVCO= 2.3V
Ta = +25°C
CP: 6mA mode
K
V
= 21MHz/V
fr = 200kHz
OSC= 10MHz
LPF
S.G
OSCIN
fin
f
LPF
Do
10kΩ
2kΩ
0.033µF
2700pF
1000pF
Spectrum
Analyzer
VCO
Typical plots measured with test circuit are shown below. The plots show lock up time, phase noise and reference leakage.
RF PLL Phase Noise
RF PLL Reference Leakage
@ max within loop band = -73 dBc/Hz
@ 200 kHz offset = -85 dBc
-85 dBc
RF PLL Lock Up Time = 718µs
RF PLL Lock Up Time = 667µs
1750.000 MHz → 1800.000 MHz, within ± 1kHz)
(1800.000 MHz → 1750.000 MHz, within ± 1kHz)
Fujitsu Microelectronics, Inc. 17
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F07SL
Input Sensivity of f PLL1 Versus Input Frequency
IN
(Prescaler set at 64/65, CP in 6.0mA mode)
PLL1 input sensitivity − Input frequency
Ta = +25 °C
10
5
0
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC (SeePg. 12)
−5
−10
−15
−20
−25
−30
0
100
200
300
400
500
600 700
800
900 1000 1100 1200 1300 1400 1500
fin1 (MHz)
Input Sensivity of f PLL2 Versus Input Frequency
IN
(Prescaler set at 64/65, CP in 6.0mA mode)
PLL2 input sensitivity − Input frequency
Ta = +25 °C
10
5
0
SPEC (SeePg. 12)
−5
−10
−15
−20
−25
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
−30
−35
−40
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
fin2 (MHz)
Input Sensivity of OSC Versus Input Frequency
IN
Input sensitivity − Input frequency
Ta = +25 °C
10
0
SPEC
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
5
10
15
20
25
30
35
40
45
50
fOSCin (MHz)
18 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Typical Electrical Characteristics: MB15F07SL
Input Impedance
fin1 input impedance
1 : 360.88 Ω
−683.25 Ω
100 MHz
30.641 Ω
−206.18 Ω
400 MHz
2 :
3 :
4 :
10.805 Ω
−92.172 Ω
800 MHz
fin
Pin
PLL1
10.076 Ω
−54.955 Ω
1100 MHz
1
2
4
3
START
100.000 000 MHz
STOP
1
100.000 000 MHz
fin2 input impedance
1 : 299.88 Ω
−658.06 Ω
100 MHz
26.68 Ω
−184.5 Ω
400 MHz
2 :
3 :
4 :
11.949 Ω
−75.16 Ω
800 MHz
fin
Pin
PLL2
14.246 Ω
−36.49 Ω
1100 MHz
1
2
4
3
START
100.000 000 MHz
STOP 1 100.000 000 MHz
OSCIN input impedance
1 :
9.451 kΩ
−3.1875 kΩ
3 MHz
2 :4.7255 kΩ
−5.1685 kΩ
10 MHz
1.6918 kΩ
3 :
−3.8045 kΩ
20 MHz
4
OSC Pin
IN
1
3
2
4 : 463.75 Ω
−2.1069 kΩ
40 MHz
START 3.000 000 MHz
STOP 40.000 000 MHz
Fujitsu Microelectronics, Inc. 19
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F07SL
Conditions: Ta = +25°C
VCC= 3.0V
Do output current: 1.5 mA mode
PLL2
PLL1
VDO − IDO
VDO − IDO
Ta = +25 °C
VCC = 3 V
Ta = +25 °C
CC = 3 V
10.00
10.00
V
2.000
/div
2.000
/div
IDOL
I
DOL
0
0
IDOH
I
DOH
−10.00
0
4.800
−10.00
.6000/div
0
4.800
.6000/div
Change pump output voltage VDO (V)
Change pump output voltage VDO (V)
Do output current: 6.0 mA mode
PLL2
PLL1
VDO − IDO
VDO − IDO
Ta = +25 °C
VCC = 3 V
Ta = +25 °C
CC = 3 V
10.00
10.00
V
IDOL
I
DOL
2.000
/div
2.000
/div
0
0
IDOH
I
DOH
−10.00
0
4.800
−10.00
.6000/div
0
4.800
.6000/div
Change pump output voltage VDO (V)
Change pump output voltage VDO (V)
20 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Reference Information: MB15F07SL
Test Circuit
f
K
VCO= 988MHz
= 35MHz/V
fr = 200kHz
OSC= 10MHz
LPF
V
CC= V
P = 3.0V
VVCO= 5.0V
Ta = +25°C
CP: 6mA mode
V
S.G
OSCIN
fin
f
LPF
Do
6100Ω
1200Ω
0.033µF
3300pF
750pF
Spectrum
Analyzer
VCO
Typical plots measured with test circuit are shown below. The plots show lock up time, phase noise and reference leakage.
PLL1, PLL2 Reference Leakage
PLL1, PLL2 Phase Noise
@ max within loop band = -76.8 dBc/Hz
@ 200 kHz offset = -79.3 dBc
-79.29 dBc
RF PLL Lock Up Time = 360µs
RF PLL Lock Up Time = 380µs
(1001.000 MHz → 975.000 MHz, within ± 1kHz)
(975.000 MHz → 1001.000 MHz, within ± 1kHz)
Fujitsu Microelectronics, Inc. 21
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F08SL
Input Sensivity of f PLL2 Versus Input Frequency
IN
PLL2 input sensitivity - Input frequency
10
5
Ta = +25 °C
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
200
400
600
800
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800
Input frequency finRX (MHz)
Input Sensivity of f PLL1 Versus Input Frequency
IN
PLL1 input sensitivity - Input frequency
10
5
Ta = +25 °C
0
SPEC
−5
−10
−15
−20
−25
−30
−35
−40
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
200
400
600
800
1000
1200
1400
1600
Input frequency finTX (MHz)
Input Sensivity of OSC Versus Input Frequency
IN
Input sensitivity − Input frequency
10
0
Ta = +25 °C
SPEC
−10
−20
−30
−40
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
20
40
60
80
100
120
140
160
180
200
220
240
Input frequency fOSC (MHz)
22 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Typical Electrical Characteristics: MB15F08SL
Input Impedance
1
2
3
:
382.09
−720
100 MHz
Ω
Ω
:
32.828
−218.91
Ω
Ω
400 MHz
:
11.242
−97.672
Ω
Ω
800 MHz
fin
Pin
PLL2
4 : 9.4512 Ω
−50.598 Ω
1200 MHz
1
2
4
3
START 100.000 000 MHz
STOP 1 200.000 000 MHz
1
2
3
:
393.91
Ω
Ω
−714.91
100 MHz
:
9.5156
Ω
Ω
−69.926
1 GHz
:
27.894
Ω
Ω
−13.635
4
2 GHz
fin
Pin
PLL1
4 : 18.047 Ω
−1.2236 Ω
2.5 GHz
1
3
2
START 100.000 000 MHz
STOP 2 500.000 000 MHz
OSCIN input impedance
1 :
8.8755 kΩ
−2.52 kΩ
3 MHz
2 : 4.796 kΩ
−4.934 kΩ
10 MHz
1.7043 kΩ
3 :
−3.8729 kΩ
20 MHz
4
OSC Pin
IN
1
3
2
4 : 439.87 Ω
−2.1714 kΩ
40 MHz
START 3.000 000 MHz
STOP 40.000 000 MHz
Fujitsu Microelectronics, Inc. 23
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Typical Electrical Characteristics: MB15F08SL
Do output current: 1.5 mA
PLL2
PLL1
IDO − VDO
IDO − VDO
Ta = +25 °C
VCC = 3.0 V
Ta = +25 °C
VCC = 3.0 V
10.00
10.00
2.000
/div
2.000
/div
IDOL
IDOL
0
0
IDOH
IDOH
−10.00
−10.00
0
4.800
0
4.800
.6000/div
.6000/div
Charge pump output voltage VDO (V)
Charge pump output voltage VDO (V)
Do output current: 6.0 mA mode
PLL1
PLL2
IDO − VDO
IDO − VDO
Ta = +25 °C
VCC = 3.0 V
Ta = +25 °C
VCC = 3.0 V
10.00
10.00
IDOL
IDOL
2.000
/div
2.000
/div
0
0
IDOH
IDOH
−10.00
−10.00
0
4.800
0
4.800
.6000/div
Charge pump output voltage VDO (V)
.6000/div
Charge pump output voltage VDO (V)
24 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Reference Information: MB15F08SL
Test Circuit
f
VCO= 1733MHz
VCC= VP = 3.0V
VVCO= 3.5V
Ta = +25°C
CP: 6mA mode
K
V
= 44MHz/V
fr = 200kHz
OSC= 13MHz
LPF
S.G
OSCIN
fin
f
LPF
Do
27kΩ
1.9kΩ
0.022µF
2200pF
200pF
Spectrum
Analyzer
VCO
Typical plots measured with test circuit are shown below. The plots show lock up time, phase noise and reference leakage.
PLL2 Reference Leakage
@ 200 kHz offset = -79.8 dBc
PLL2 Phase Noise
@ max within loop band = -73.4 dBc/Hz
ATTEN 10 dB
RL 0 dBm
∆MKR −48.67 dB
14.25 kHz
ATTEN 10 dB
RL 0 dBm
∆MKR −79.83 dB
10 dBm/ 200 kHz
10 dB/
73.4 dBc/Hz
-79.8 dBc
15.5 kHz
CENTER 1.73300000 GHz
RBW 300 Hz VBW 300 Hz
SPAN 50.00 kHz
SWP 1.40 sec
CENTER 1.733000 GHz
RBW 3.0 kHz VBW 3.0 kHz
SPAN 1.000 MHz
SWP 280 ms
PLL2 Lock Up Time = 467 s
PLL2 Lock Up Time = 467 s
(1803.000 MHz → 1733.000 MHz, within ± 1kHz)
(1733.000 MHz → 1803.000 MHz, within ± 1kHz)
1.90300 GHz
1.83300 GHz
1.73300 GHz
1.80300 GHz
1.70300 GHz
1.63300 GHz
−678 µs
1.822 ms
4.322 ms
−678 µs
1.822 ms
4.322 ms
500.0 µs/div
500.0 µs/div
T1 400 µs
T2 867 µs
∆ 467 µs
T1 400 µs
T2 867 µs
∆ 467 µs
Fujitsu Microelectronics, Inc. 25
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Serial Data Input
Functional Descriptions
The serial data is entered using the Data, Clock and LE pins.The
TheVCO output frequency can be calculated using the following
serial data controls the programmable reference counters and the
equation:
programmable counters separately.
f
= {(M x N) + A} x f ÷ R (A < N)
VCO
OSC
The binary serial data is entered through the Data pin when the LE
pinisheldlow.Onebit of dataisshiftedintotheshift registeronthe
rising edge of the Clock.When the LE signal pin is taken high,
entered data is latched into the appropriate counters according to
the control bit settings as follows:
f
Output frequency of external voltage controlled ocillator (VCO)
Preset divideratioof dualmodulusprescaler(8, 16, 32, 64or
128 for IF PLL or PLL1) (32, 64 or 128 for RF PLL or PLL2)
Preset divide ratio of binary 11-bit programmable counter
(3 to 2,047)
VCO
M
N
A
Preset divide ratio of binary 7-bit swallow counter (0 ≤A ≤ 127)
Reference oscillation frequency
f
OSC
R
Preset divide ratio of binary 14-bit programmable reference
counter (3 to 16,383)
Table 1. Control Bits
Control bit
Destination of serial data
CN1
L
CN2
L
Programmable reference counter for IF-PLL or PLL1, Tx
H
L
Programmable reference counter for RF-PLL or PLL2, Rx
Programmable counter and swallow counter for IF-PLL or PLL1, Tx
Programmable counter and swallow counter for RF-PLL or PLL2, Rx
L
H
H
H
Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X
21
X
22
X
23
X
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
C
S
CNT1, 2
R1 to R14
T1, 2
CS
Control bits
[Table 1]
[Table 2]
[Table 3]
[Table. 9]
Divide ratio setting bits for the programmable reference counter (3 to 16,383)
Test purpose bits
Charge pump current select bit
X
Dummy bits(set “0” or “1”)
Note: Input Data with MSB first.
26 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Functional Descriptions
Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19
20
21 22 23
C
N
1
C
N
2
L
D
S
S
F
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
W
C
10 11
CNT1, 2
Control bits
[Table 1]
[Table 4]
[Table 5]
[Table 6]
N1 to N14
A1 to A7
Divide ratio setting bits for the programmable counter (3 to 2,047)
Divide ratio setting bits for the swallow counter (0 to 127)
MB15F02SL, MB15F03SL:
SW
Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
IF/RF
MB15F07SL:
SW
Divide ratio setting bit for the prescaler
(64/65 or 128/129 for PLL1 and PLL2)
PLL1/PLL2
MB15F08SL:
SW
Divide ratio setting bit for the prescaler
(16/17or 32/33 for PLL1, 32/33 or 64/65 for PLL2)
Tx/Rx
FC
LDS
Note: Input Data with MSB first.
Phase control bit for the phase detector (FC
, FC
)
RF/PLL2
[Table 7]
[Table 8]
IF/PLL1
LD/f signal select bit
OUT
Table 2. Binary 14-Bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
1
0
.
1
0
.
4
.
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
T
1
T
2
LD/f
Pin State
OUT
L
H
L
L
L
Outputs fr
Outputs fr
IF/PLL1/Tx
RF/PLL2/Rx
H
H
Outputs fp
Outputs fp
IF/PLL1/Tx
RF/PLL2/Rx
H
Fujitsu Microelectronics, Inc. 27
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Functional Descriptions
Table 4. Binary 11-Bit Programmable Counter Data Setting
Divide
Ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
1
0
.
1
0
.
4
.
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 5. Binary 7-Bit Swallow Counter Data Setting
Divide
Ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
.
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table 6. Prescaler Data Setting for MB15F02SL, MB15F03SL
Prescaler
Divide Ratio
SW = “H”
SW = “L”
8/9
16/17
IF-PLL
64/65
128/129
RF-PLL
Prescaler Data Setting for MB15F07SL
Prescaler
SW = “H”
SW = “L”
128/129
Divide Ratio
64/65
64/65
PLL1
PLL2
128/129
Prescaler Data Setting for MB15F08SL
Prescaler
SW = “H”
SW = “L”
32/33
Divide Ratio
16/17
32/33
PLL Tx
PLL Rx
64/65
28 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Functional Descriptions
Table 7. Phase Comparator Phase Switching Data Setting
FC
= H
FC
= L
IF/PLL1,RF/PLL2
IF/PLL1,RF/PLL2
(1)
Do
IF/PLL1,RF/PLL2
fr > fp
fr = fp
H
Z
L
Z
VCO output
frequency
fr < fp
L
H
VCO polarity
(1)
(2)
Notes: Z = High-impedance
FC bit should be set depending upon VCO and LPF polarity
(2)
VCO output voltage
Table 8. LD/fOUT Output Select Data Setting
LDS
LD/f
Output Signal
OUT
H
L
f
signals
OUT
LD signals
Table 9. Charge Pump Current Setting
CS
Current Value
H
L
6.0 mA
1.5 mA
Fujitsu Microelectronics, Inc. 29
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Power-Saving Mode (Intermittent Mode Control)
The Intermittent Mode Control circuit greatly reduces the PLL power consumption by shutting down various internal functions, as shown in
Table 11, depending upon the settings of the power-save (PS) pins. (See the Electrical Characteristics chart for the specific value of current
when in the power-saving mode.)
The phase detector output, Do, becomes high impedance.
The lock detector output, LD, is as shown inTable 13.
Setting the PS pin high releases the power-saving mode returning the selected PLL to normal operation.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation, at which time, the phase
comparator output signal is unpredictable due to the unknown relationship between the comparison frequency (fp) and the reference
frequency (fr).This can cause a major change in the comparator output, resulting in aVCO frequency jump and an increase in lock-up time.
To prevent a majorVCO frequency jump, the Intermittent Mode Control circuit limits the magnitude of the error signal from the phase
detector when it returns to normal operation.
Note: When power (V ) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
CC
Table 10. Power-Save Pin Setting
PS Pins
Status
H
L
Normal mode
Power-saving mode
Table 11. Power-Save Internal Shutdown Logic
PS
PS
IF (TX)-PLL counters
RF (RX)-PLL counters
OSC input buffer
IF
RF
L
L
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
H
L
L
H
H
OFF
ON
H
ON
Power-ON Timing
OFF
ON
VCC
≥
tV 1 µS
Clock
Data
LE
≥
tPS 100 nS
PS
(1)
(2)
(3)
(1) PS = L (power-saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (V > 2.2V).
CC
(3) Release power-saving mode (PS: L → H) 100 ns later after setting serial data.
30 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Serial Data Input Timing
1st data
2nd data
Control bit Invalid data
Data
MSB
LSB
Clock
t 1
t 2
t 5
t 4
t 7
LE
t 3
t 6
Table 12. Timing Parameters
Parameter
Min.
Typ.
Max.
Unit
Parameter
Min.
Typ.
Max.
Unit
t1
t2
t3
t4
20
20
30
30
–
–
–
–
–
–
–
–
ns
ns
ns
ns
t5
t6
t7
100
20
–
–
–
–
–
–
ns
ns
ns
100
Notes: 1) On the rising edge of the clock, one bit of the data is transferred into the shift register.
2) LE should be “L” when the data is transferred into the shift register.
Fujitsu Microelectronics, Inc. 31
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Phase Detector Output Waveform
fr
IF/RF, PLL1/PLL2
fp
IF/RF, PLL1/PLL2
t
t
WL
WU
LD
(FC bit = High)
H
Do
IF/RF, PLL1/PLL2
Z
Z
L
(FC bit = Low)
Do
IF/RF, PLL1/PLL2
Notes: 1) Phase error detection range: –2π to +2π
2) Pulses on Do signal during locked state are output to prevent dead zone.
3) LD output becomes low when phase is t or more. LD output becomes high when phase error is t or less and continues to be so for three cycles or more.
WU
WL
4)
t
and t depend on OSC input frequency.
WU WL IN
t
t
> 2/fosc (s) (e. g. t > 156.3ns, fosc = 12.8MHz)
WU
WU
< 4/fosc (s) (e. g. t < 312.5ns, fosc = 12.8MHz)
WU
WL
5) LD becomes high during the power-saving mode (PS = “L”).
Table 13. LD Output LogicTable
IF/PLL1 Section
RF/PLL2 Section
LD Output
Locked state / Power-saving state
Locked state / Power-saving state
Unlocked state
Locked state / Power-saving state
Unlocked state
H
L
L
L
Locked state / Power-saving state
Unlocked state
Unlocked state
32 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Application Example
OUTPUT
LPF
VCO
3V
from controller
1000 pF
0.1µF
1000 pF
Clock
16
Data
15
LE
fin
Vcc
Xfin
PS
Do
RF
RF
RF
RF
RF
14
13
12
11
10
9
MB15FxxSL*
5
1
2
3
4
6
7
8
GND
OSC
GND
fin
IF
Vcc
LD/fout
PS
Do
IF
RF
IN
IF
IF
IF
3V
Lock Det.
1000 pF
1000 pF
0.1µF
TCXO
OUTPUT
LPF
VCO
Notes:
1) Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation)
2) *MB15F07SL uses PLL designators PLL1 and PLL2 in place of IF and RF in the pin signal callouts. MB15F08SL uses
Tx and Rx in place of IF and RF.
3) Package type: 16-pin SSOP
Fujitsu Microelectronics, Inc. 33
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Usage Precautions
Vcc
must equalVcc
:
RF/PLL2
IF/PLL1
• Even if either the RF/PLL2 or IF/PLL1 is not used, power must be supplied to bothVcc
andVcc
to keep them
RF/PLL2
IF/PLL1
equal. It is recommended that the unused PLL be controlled by the power-saving function.
To protect against damage by electrostatic discharge, note the following handling precautions:
• Store and transport devices in conductive containers.
• Use properly grounded workstations, tools, and equipment.
• Turn off power before inserting or removing this device into or from a socket.
• Protect leads with conductive sheet when transporting a board mounted device.
Ordering Information
Part Number
Package
MB15FxxSLPFV1
MB15FxxSLPV1
16 pin, Plastic SSOP (FPT-16P-M05)
16 pin, Plastic BCC (LCC-16P-M04)
34 Fujitsu Microelectronics, Inc.
MB15FxxSL Series
Package Dimensions
1.25 –+00..1200
.049 +–..000048
*
5.00±0.10(.197±.004)
(Mounting height)
0.10(.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
0.22 –+00..0150
.009 +–..000024
0.15 –+00..0025
Details of "A" part
0.65±0.12
(.0256±.0047)
.006 +–..000012
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
Dimensions in mm (inches)
Note: 16-pin, Plastic SSOP (FPT-16P-M05)
* These dimensions do not include resin protrusion.
Fujitsu Microelectronics, Inc. 35
Dual PLL Frequency Synthesizers with On-Chip Prescalers
Package Dimensions
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.65(.026)
0.325±0.10
TYP
(.013±.004)
14
9
9
14
0.80(.031)
REF
INDEX AREA
3.40±0.10
(.134±.004)
2.45(.096)
TYP
1.55(.045)
REF
"B"
"A"
0.40±0.10
(.016±.004)
0.075±0.025
(.003±.001)
1.725(.068)
REF
1
6
6
1
(Stand off)
Details of "A" part
0.75±0.10
Details of "B" part
0.60±0.10
(.024±.004)
(.030±.004)
0.05(.002)
0.40±0.10
0.60±0.10
(.016±.004)
(.024±.004)
Dimensions in mm (inches)
Note: 16-pin, Plastic BCC (LCC-16P-M06)
36 Fujitsu Microelectronics, Inc.
©2001 Fujitsu Microelectronics, Inc. All rights reserved.
All company and product names are trademarks or registered
trademarks of their respective owners.
With respect to any information contained in this document,
Fujitsu makes no warranties, express, implied or otherwise,
including but not limited to warranty of merchantability or of
fitness for a particular purpose, or warranty that such
information shall be free from errors or that such errors shall
be corrected, or warranty that such information shall be free
from infringement or patents, patent applications, copyrights,
semiconductor chip protection rights, trade secrets and other
proprietary or legal rights of a third party. In no event will
Fujitsu be responsible for any incidental or consequential
damages arising out of use of this information.
The information in this document does not convey any license
under the copyrights, patent rights, or trademarks claimed and
owned by Fujitsu Limited, its subsidiaries, or Fujitsu
Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change
products or specifications without notice.
FUJITSU MICROELECTRONICS AMERICA, INC.
No part of this publication may be copied or reproduced in
any form, or by any means, or transferred to any third party
without prior written consent of Fujitsu Microelectronics, Inc.
Corporate Headquarters
1250 East Arques Avenue, Sunnyvale, California 94088-3470
Tel: (800) 866-8608 Fax: (408) 737-5999
Printed in U.S.A.
E-mail: inquiry@fma.fujitsu.com Web Site: http://www.fma.fujitsu.com
TC-DS-20788-07/2001
相关型号：
©2020 ICPDF网 联系我们和版权申明