MB15F03LPV [FUJITSU]
Dual Serial Input PLL Frequency Synthesizer; 双串行输入锁相环频率合成器
| 型号： | MB15F03LPV |
| 厂家： | 
FUJITSU |
| 描述： | Dual Serial Input PLL Frequency Synthesizer |
| 文件： | 总24页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21350-1E
ASSP
Dual Serial Input
PLL FrequencySynthesizer
MB15F03L
■ DESCRIPITON
The Fujitsu MB15F03L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1800MHz and
a 250MHz prescalers. A 64/65 or a 128/129 for the 1800MHz prescaler, and a 16/17 or a 32/33 for 250MHz
prescaler can be selected that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 5.0mA typ. at
a supply voltage of 3.0V.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As
a result of this, MB15F03L is ideally suitable for digital mobile communications, such as PHS(Personal Handy
Phone System), PCN (Personal Communication Network) and PCS(Personal Communication Service).
■ FEATURES
• High frequency operation RF synthesizer: 1800MHz max. / IF synthesizer: 250MHz max.
• Low power supply voltage: VCC = 2.7 to 3.6V
• Very Low power supply current : ICC = 5.0 mA typ. (Vcc = 3V)
• Power saving function : Supply current at power saving mode Typ.0.1µA (Vcc=3V), Max.10µA (IPS1=IPS2)
• Dual modulus prescaler : 1800MHz prescaler(64/65,128/129) , 250MHz prescaler(16/17,32/33)
• Serial input 14–bit programmable reference divider: R = 5 to 16,383
• Serial input 18–bit programmable divider consisting of:
- Binary 7–bit swallow counter: 0 to 127
- Binary 11–bit programmable counter: 5 to 2,047
• On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and
low phase noise
• On–chip phase control for phase comparator
• Wide operating temperature: Ta = -40 to 85°C
■ PACKAGE
16-pin, Plastic SSOP
16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M03)
MB15F03L
■ PIN ASSIGNMENT
SSOP-16-PIN
GNDRF
1
2
3
16
15
14
Clock
OSCin
GNDIF
finIF
Data
LE
4
5
6
7
13
12
11
10
TOP
VIEW
finRF
VccRF
XfinRF
VccIF
LD/fout
PSIF
PSRF
DoRF
DoIF
8
9
(FPT-16P-M05)
BCC-16-PIN
GNDRF Clock
16 15
OSCin
GNDIF
finIF
Data
LE
1
14
13
12
11
10
9
2
3
4
5
6
finRF
VCCRF
XinRF
PSRF
TOP VIEW
VCCIF
LD/fout
PSIF
7
8
DOIF DORF
(LCC-16P-M03)
2
MB15F03L
■ PIN DESCRIPTION
Pin No.
Pin
I/O
Descriptions
name
GNDRF
OSCin
GNDIF
SSOP-16 BCC-16
1
2
3
4
5
16
1
–
I
Ground for RF–PLL section.
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
2
–
I
Ground for the IF-PLL section.
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
3
finIF
4
VccIF
–
Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
6
7
5
6
LD/fout
PSIF
O
I
LDS bit = ”L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode
PSIF = ”L” ; Power saving mode
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
8
9
7
8
DoIF
O
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
DoRF
Power saving mode control for the RF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode
10
9
PSRF
I
PSRF = ”L” ; Power saving mode
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
11
12
13
10
11
12
XfinRF
VccRF
finRF
I
–
I
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RF-
PLL is cancelled.
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
When LE is ”H”, data in the shift register is transferred to the
corresponding
14
13
LE
I
latch according to the control bit in a serial data.
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
15
16
14
15
Data
I
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
Clock
3
MB15F03L
■ BLOCK DIAGRAM
VccIF GNDIF
3
5
7-bit latch
3-bit latch
11-bit latch
Intermittent
fpIF
mode
7
Binary 11-bit
programmable
counter(IF–PLL)
Binary 7-bit
swallow counter
(IF–PLL)
Phase
comp.
(IF–PLL)
control
Charge
pump
PSIF
Super
charger
SWIF FCIF
LDS
(IF–PLL)
DoIF
8
(IF–PLL)
Prescaler
(IF–PLL)
finIF
4
16/17,32/33
Lock
Det.
(IF–PLL)
2-bit latch
T1
14-bit latch
LDI
frIF
Binary 14–bit pro-
grammable ref.
T2
counter(IF–PLL)
2
OSCin
AND
Selector
LD
OR
frIF
frRF
frRF
LD/fout
Binary 14-bit pro-
grammable ref.
counter(RF–PLL)
6
fpIF
T1
T2
fpRF
LDRF
2-bit latch
14-bit latch
Lock
Det.
(RF–PLL)
Prescaler
finRF
(6R4F–/6PL5L,)
13
11
128/129
XfinRF
Binary 11-bit
programmable
counter(RF–PLL)
Binary 7-bit
swallow counter
(RF–PLL)
Phase
comp.
Charge
pump
Super
charger
SWRF FCRF
3-bit latch
LDS
DoRF
9
Intermittent
mode
(RF–PLL)
(RF–PLL)
fpRF
PSRF
LE
10
14
control
7-bit latch
11-bit latch
(RF–PLL)
Schmitt
circuit
Latch selector
Schmitt
circuit
C
C
N
15
16
Data
N
23-bit shift
register
2
1
Schmitt
circuit
Clock
12
1
VCCRF
GNDRF
Note: SSOP-16 pin
4
MB15F03L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Symbol
VCC
VI
Rating
–0.5 to +4.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–10 to +10
Unit
Remark
V
V
Output voltage
VO
V
IO
mA
mA
°C
Except Do
Do output
Output current
Ido
–25 to +25
Storage temperature
TSTG
–55 to +125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Note
Min
2.7
Typ
3.0
–
Max
3.6
Power supply voltage
Input voltage
VCC
Vi
V
V
VCCIF=VCCRF
GND
–40
VCC
+85
Operating temperature
Ta
–
°C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always yse semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with repect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
Handling Precautions
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workerbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15F03L
■ ELECTRICAL CHARACTERISTICS
(Vcc=2.7V to 3.6V, Ta=-40°C to 85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
finIF = 233.15MHz,
fosc = 12MHz
*1
—
1.5
—
ICCIF
Power supply current
mA
finRF = 1800MHz,
fosc = 12MHz
*2
—
—
—
3.5
—
10
10
ICCRF
VccIF current
at PSIF =”L”
0.1*3
0.1*3
IpsIF
Power saving current
µA
VccRF current
at PSIF/RF =”L”
IpsRF
*4
finIF
finRF
fOSC
IF–PLL
RF–PLL
—
50
100
3
—
—
—
250
1800
40
finIF
Operating
frequency
*4
MHz
dBm
finRF
OSCin
IF–PLL, 50Ω
termination
finIF
VfinIF
–10
—
+2
Input sensitivity
Input voltage
RF–PLL, 50Ω
termination
finRF
VfinRF
VOSC
VIH
–10
0.5
—
—
—
+2
VCC
—
dBm
Vp-p
OSCin
—
VCCx0.7+
0.4
Schmitt trigger input
Data,
Clock,
LE
V
V
VCCx0.3
–0.4
VIL
Schmitt trigger input
—
—
VIH
VIL
—
—
—
VCCx0.7
—
—
—
—
PSIF,
PSRF
VCCx0.3
+1.0
*5
Data,
Clock,
LE,
PSIF,
PSRF
–1.0
IIH
µA
*5
—
–1.0
—
+1.0
IIL
Input current
IIH
—
—
0
–100
VCC–0.4
—
—
—
—
—
—
—
+100
0
OSCin
LD/fout
µA
V
*5
IIL
VOH
VOL
IOH=–1.0mA
IOL= 1.0mA
—
0.4
—
Output voltage
VDOH
VDOL
IDOH =–1.0mA
VCC=3.0V, IDOL=1.0mA
VCC–0.4
—
DoIF,
DoRF
V
0.4
High impedance DoIF,
cutoff current
VCC=3.0V,
VOFF=GND to VCC
IOFF
—
—
3.0
nA
DoRF
(Continued)
6
MB15F03L
(Continued)
(Vcc=2.7V to 3.6V, Ta=-40°C to 85°C)
Value
Unit
Parameter
Symbol
Condition
Vcc = 3.0V
Min.
–1.0
—
Typ.
—
Max.
—
*5
IOH
LD/fout
mA
mA
IOL
Vcc = 3.0V
—
1.0
Vcc = 3.0V, VDOH =
2.0V , Ta=25°C
*5
Output current
–11
8
—
—
–6
15
IDOH
DoIF,
DoRF
Vcc = 3.0V, VDOL =
1.0V, Ta=25°C
IDOL
*1: Conditions ; VccIF = 3V, Ta = 25°C, in locking state.
*2: Conditions ; VccRF = 3V, Ta = 25°C, in locking state.
*3: fosc = 12.8 MHz , Vcc = 3.0V, Ta = 25°C
*4: AC coupling with a 1000pF capacitor connected.
*5: The symbol "-"(minus) means direction of current flow.
7
MB15F03L
■ FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(P x N) + A} x fOSC ÷ R (A < N)
fVCO: Output frequency of external voltage controlled oscillator (VCO)
P:
N:
A:
Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
fOSC: Reference oscillation frequency
R: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF–PLL
sections, programmable reference dividers of IF/RF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
L
CN2
L
The programmable reference counter for the IF-PLL.
H
L
The programmable reference counter for the RF-PLL.
L
H
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
H
H
Shift Register Configuration
Programmable Reference Counter
LSB
MSB
Data Flow
11 12
21
X
2
3
5
7
14 15 16 17 18
20
X
23
X
1
4
6
8
9
10
13
19
X
22
X
C
N
2
C
N
1
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
8
R
9
R
R
R
R
R
R
7
10 11 12 13 14
CN1, 2
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383) [Table. 2]
T1, 2
X
: Test purpose bit
[Table.3]
: Dummy bits(Set "0" or "1")
Note: Data input with MSB first.
8
MB15F03L
Programmable Counter
MSB
LSB
1
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
L
S
F
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
D
S
W
IF RF IF
/
C
10 11
RF
/
CN1, 2
: Control bit
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7
SWIF/RF
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
FCIF/RF
LDS
: Phase control bit for the phase detector
: LD/fout signal select bit
[Table. 7]
[Table. 8]
Note: Data input with MSB first.
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
1
0
•
6
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
LD/fout pin state
T
1
T
2
L
H
L
L
L
Outputs frIF.
Outputs frRF.
Outputs fpIF.
Outputs fpRF.
H
H
H
9
MB15F03L
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
N
(N)
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
11
5
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
1
0
•
6
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
•
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = ”H”
16/17
SW = ”L”
32/33
IF-PLL
Prescaler
divide ratio
RF-PLL
64/65
128/129
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF,RF = H
FCIF,RF = L
(1)
DoIF,RF
DoIF,RF
fr > fp
fr = fp
H
Z
L
Z
VCO Output
Frequency
fr < fp
L
H
VCO polarity
(1)
(2)
(2)
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
VCO Input Voltage
FC bit should be set.
Table. 8 LD/fout Output Select Data Setting
LD/fout output signal
LDS
H
fout (frIF/RF, fpIF/RF) signals
LD signal
L
10
MB15F03L
Serial Data Input Timing
1st. data
2nd. data
Control bit Invalid data
Data
MSB
LSB
Clock
t 1
t 2
t 5
t 4
t 7
LE
t 3
t 6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Parameter
Min
Typ
Max
Unit
Min
30
Typ
–
Max
Unit
20
20
30
20
–
–
–
–
–
–
–
–
–
–
–
t1
t2
t3
t4
ns
ns
ns
ns
t5
t6
t7
ns
ns
ns
100
100
–
–
11
MB15F03L
■ PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DoIF/RF
Z
L
(FC bit = Low)
DoIF/RF
Z
LD Output Logic Table
IF–PLL section
LD output
RF–PLL section
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Locking state / Power saving state
H
L
Unlocking state
Unlocking state
Locking state / Power saving state
Unlocking state
L
L
Note: •Phase error detection range = −2π to +2π
•Pulses on DoIF/RF signals are output to prevent dead zone.
•LD output becomes low when phase error is tWU or more.
•LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
•tWU and tWL depend on OSCin input frequency as follows.
tWU > 4/fosc: i.e. tWU > 312.5ns when foscin = 12.8 MHz
tWL < 8/fosc: i.e. tWL < 625.0ns when foscin = 12.8 MHz
12
MB15F03L
■ POWER SAVING MODE (INTERMITTENT MODE CONTROL CIRCUIT)
Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption
can be limited to 10µA (typ.). Setting PS pin to High, power saving mode is released so that the device works
normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode.
In general, the power consumption can be saved by the intermittent operation that powering down or waking up the
synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is
unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp)
and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up. Thus keeping the loop locked.
PS pin must be set “L” at Power-ON.
Allow 1 µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H)
Serial data can be entered during the power saving mode.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF’s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
PSIF
L
PSRF
IF-PLL counters
RF-PLL counters
OSC input buffer
L
L
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
H
L
H
H
OFF
ON
H
ON
ON
Vcc
Clock
Data
LE
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2)Set serial data after power supply remains stable.
(3)Release saving mode(PS : L → H) after setting serial data.
13
MB15F03L
■ TESTCIRCUIT(PRESCALERINPUT/PROGRAMMABLEREFERENCEDIVIDERINPUTSENSITIVITYTEST)
fout
Oscilloscope
VccIF
1000pF
0.1µF
S.G
50Ω
1000pF
S.G
GND
8
9
7
6
5
3
2
1
4
50Ω
MB15F03L
12
10
11
13 14
15
16
S.G
1000pF
Controller (divide
ratio setting)
50Ω
VccRF
0.1µF
1000pF
Note.:SSOP-16 pin.
14
MB15F03L
■ TYPICAL CHARACTERISITICS
1. fin Input Sensitivity
V fin RF vs. fin RF
10
5
Ta = +25°C
0
SPEC
–5
–10
–15
–20
–25
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
–30
–35
–40
0
1000
2000
3000
4000
fin RF (MHz)
V fin IF vs. fin IF
10
5
Ta = +25°C
0
SPEC
–5
–10
–15
–20
–25
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
–30
–35
–40
0
100
500
800
900 1000
200
300
600
400
700
fin IF (MHz)
2. OSCin Input Characteristics
V fosc vs. fosc
10
5
Ta = +25°C
SPEC
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
0
10
20
30
40
50
60
70
80
90 100
fOSC (MHz)
15
MB15F03L
3. DoRF Output Current
I DOH vs. V DOH
V CC = 3 V
Ta = +25°C
5.000
.0000
.0000
–25.00
“H” level output current I DOH (mA )
I DOL vs. V DOL
5.000
V CC = 3 V
Ta = +25°C
.0000
.0000
25.00
“L” level output current I DOL (mA)
16
MB15F03L
4. DoIF Output Current
I DOH vs. V DOH
V CC = 3 V
Ta = +25°C
5.000
.0000
.0000
–25.00
“H” level output current I DOH (mA)
I DOL vs. V DOL
V CC = 3 V
Ta = +25°C
5.000
.0000
.0000
25.00
“L” level output current I DOL (mA)
17
MB15F03L
5. Input Impedance.
fin RF Input Inpedance characteristic
1 :
21 Ω
–144.73 Ω
500 MHz
2 : 10.471 Ω
–59.998 Ω
1 GHz
3 : 10.063 Ω
–24.667 Ω
1.5 GHz
4
RF
4 : 11.614 Ω
–9.771 Ω
1.8 GHz
1
3
2
START 100.000 000 MHz
STOP 2 000.000 000 MHz
fin IF Input Inpedance characteristic
1 : 781.75 Ω
–918.94 Ω
50 MHz
2 : 57.344 Ω
–304.14 Ω
250 MHz
3 : 87.141 Ω
–377.39 Ω
200 MHz
IF
4 : 26.633 Ω
–188.91 Ω
400 MHz
START 50.000 000 MHz
STOP 500.000 000 MHz
(Continued)
18
MB15F03L
(Continued)
OSC IN Input Impedance characteristic
1 :
2 :
3 :
4 :
7.533 kΩ
–23.111 kΩ
3 MHz
333 Ω
–6.2538 kΩ
10 MHz
162.38 Ω
–2.9799 kΩ
20 MHz
4
3
OSCIN
1
2
78.13 Ω
–1.5573 kΩ
40 MHz
START 1.000 000 MHz
STOP 50.000 000 MHz
19
MB15F03L
■ APPLICATION EXAMPLE
Output
LPF
VCO
3 V
from controller
1000 pF
0.1mF
1000 pF
finRF
VccRF
XfinRF
11
PSRF
10
DoRF
9
Clock Data
16 15
LE
14
13
12
MB15F03L
5
1
2
3
4
6
7
8
GNDRF OSCIN GNDIF
finIF
VccIF
PSIF
DoIF
LD/fout
3 V
Lock Det.
1000 pF
1000 pF
0.1µF
TCXO
Output
LPF
VCO
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
Note.:SSOP-16 pin
20
MB15F03L
■ ORDERING INFORMATION
Part number
Package
Remarks
16pin, Plastic SSOP
(FPT-16P-M05)
MB15F03L PFV
16pin, Plastic BCC
(LCC-16P-M03)
MB15F03L PV
21
MB15F03L
■ PACKAGE DIMENSION
16 pins, Plastic SSOP
(FPT-16P-M05)
* : These dimensions do not include resin protrusion.
1.25+–00..1200
.049 +–..000048
0.10(.004)
*
5.00±0.10(.197±.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
0.22+–00..0150
0.15 +–00..0025
.006–+..000012
Details of "A" part
0.10±0.10(.004±.004)
0.65±0.12
(.0256±.0047)
.009+–..000024
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F16013S-2C-4
(Continued)
22
MB15F03L
(Continued)
16 pins, Plastic BCC
(LCC-16P-M03)
* : These dimensions do not include resin protrusion.
4.55±0.10
(.179±.004)
0.80(.032)MAX
(Mounting height)
3.40(.134)TYP
0.65(.026)TYP
14
9
9
14
0.40±0.10
(.016±.004)
3.25(.128)
TYP
4.20±0.10
(.165±.004)
1.55(.061)TYP
45˚
"A"
"B"
0.80(.032)
TYP
E-MARK
0.40(.016)
0.325±0.10
(.013±.004)
1.725(.068)
TYP
1
6
6
1
0.085±0.040
(.003±.002)
(STAND OFF)
Details of "A" part
Details of "B" part
0.75±0.10
(.030±.004)
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
C
1996 FUJITSU LIMITED C16014S-1C-1
23
MB15F03L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
Fax: (408) 432-9044/9045
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9705
FUJITSU LIMITED Printed in Japan
相关型号：
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