MB15F02 [FUJITSU]
Dual Serial Input PLL Frequency Synthesizer; 双串行输入锁相环频率合成器
| 型号： | MB15F02 |
| 厂家： | 
FUJITSU |
| 描述： | Dual Serial Input PLL Frequency Synthesizer |
| 文件： | 总24页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21341-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F02
■ DESCRIPTION
The Fujitsu MB15F02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz and a 500
MHz prescalers. A 64/65 or a 128/129 for the 1.2 GHz prescaler, and a 16/17 or a 32/33 for 500 MHz prescaler
can be selected that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 6.0 mA typ. at a
supply voltage of 3.0 V.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a
result of this, MB15F02 is ideally suitable for digital mobile communications, such as GSM (Global System for
Mobile Communications).
■ FEATURES
• High frequency operation
RF synthesizer : 1.2 GHz max.
IF synthesizer : 500 MHz max.
• Low power supply voltage: VCC = 2.7 to 3.6V
• Very Low power supply current : ICC = 6.0 mA typ. (VCC = 3 V)
• Power saving function : IPS1 = IPS2 = 0.1 µA typ.
• Serial input 14–bit programmable reference divider: R = 5 to 16,383
• Serial input 18–bit programmable divider consisting of:
- Binary 7–bit swallow counter: 0 to 127
- Binary 11–bit programmable counter: 5 to 2,047
• On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and
low phase noise
• Wide operating temperature: Ta = −40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pin BCC package (LCC-16P-M03)
■ PACKAGES
16-pin, Plastic SSOP
16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M03)
MB15F02
■ PIN ASSIGNMENTS
SSOP-16 pin
GNDRF
Clock
1
2
3
16
15
14
OSCin
Data
LE
GNDIF
finIF
4
5
6
7
13
12
11
10
TOP
VIEW
finRF
VccRF
XfinRF
VccIF
LD/fout
PSRF
DoRF
PSIF
DoIF
8
9
(FPT-16P-M05)
BCC-16 pin
GNDRF
16
Clock
15
OSCin
GNDIF
finIF
1
2
3
4
5
6
14 Data
13 LE
12
11
10
9
finRF
TOP
VIEW
VCCIF
VCCRF
XfinRF
PSRF
LD/fout
PSIF
7
8
DoIF
DoRF
(LCC-16P-M03)
2
MB15F02
■ PIN DESCRIPTIONS
Pin No.
Pin
I/O
Descriptions
name
SSOP
BCC
1
16
GNDRF
OSCin
GNDIF
finIF
–
I
Ground for RF–PLL section.
The programmable reference divider input. TCXO should be connected
with a coupling capacitor.
2
3
4
5
1
2
3
4
–
I
Ground for the IF-PLL section.
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
VccIF
–
Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
6
7
5
6
LD/fout
PSIF
O
I
LDS bit = ”L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode
PSIF = ”L” ; Power saving mode
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
8
9
7
8
DoIF
O
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
DoRF
Power saving mode control for the RF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode
10
9
PSRF
I
PSRF = ”L” ; Power saving mode
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
11
12
13
10
11
12
XfinRF
VccRF
finRF
I
–
I
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer.
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
When LE is ”H”, data in the shift register is transferred to the
corresponding
14
13
LE
I
latch according to the control bit in a serial data.
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-Prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
15
16
14
15
Data
I
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a riging edge of the
clock.
Clock
3
MB15F02
■ BLOCK DIAGRAM
VccIF
5
GNDIF
3
7-bit latch
3-bit latch
11-bit latch
Intermittent
fpIF
mode
7
Binary 11-bit
programmable
counter(IF–PLL)
Binary 7-bit
Phase
control
Charge
PSIF
Super
charger
SWIF FCIF
LDS
swallow counter
(IF–PLL)
comp.
pump
8
(IF–PLL)
DoIF
(IF–PLL)
(IF–PLL)
Prescaler
(IF–PLL)
finIF
4
16/17,32/33
Lock
Det.
(IF–PLL)
2-bit latch
14-bit latch
LDIF
Binary 14–bit pro-
grammable ref.
counter(IF–PLL)
frIF
T1
T2
2
OSCin
AND
Selector
LD
frIF
OR
frRF
frRF
fpIF
fpRF
LD/fout
6
Binary 14-bit pro-
grammable ref.
counter(RF–PLL)
T1
T2
LDRF
2-bit latch
14-bit latch
Lock
Det.
(RF–PLL)
Prescaler
finRF
13
11
(6R4F–/6PL5L,)
128/129
XfinRF
Binary 11-bit
programmable
counter(RF–PLL)
Binary 7-bit
Phase
Charge
Super
charger
LDS SWRF FCRF
3-bit latch
swallow counter
9
DoRF
comp.
pump
(RF–PLL)
(RF–PLL)
Intermittent
mode
(RF–PLL)
fpRF
PSRF
LE
10
14
control
7-bit latch
11-bit latch
(RF–PLL)
Schmitt
circuit
Latch selector
Schmitt
circuit
Data 15
C
N
1
C
N
2
23-bit shift
register
Schmitt
circuit
Clock 16
12
1
VCCRF
GNDRF
Note: SSOP-16 pin
4
MB15F02
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Symbol
VCC
Rating
Unit
V
Remark
–0.5 to +4.0
VI
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–55 to +125
V
Output voltage
VO
V
Storage temperature
TSTG
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Note
Min.
2.7
Typ.
3.0
–
Max.
3.6
Power supply voltage
Input voltage
VCC
Vi
V
V
GND
–40
VCC
Operating temperature
Ta
–
+85
°C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always yse semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with repect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
5
MB15F02
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
finIF = 500 MHz,
Min.
Typ.
Max.
*1
–
2.5
–
ICCIF
fosc = 12 MHz
Power supply current
mA
finRF = 1200 MHz,
fosc = 12 MHz
*2
–
3.5
–
ICCRF
0.1*3
0.1*3
–
IpsIF
VccIF current at PSIF =”L”
VccRF current at PSIF/RF =”L”
IF–PLL
–
–
10
10
Power saving current
finIF
µA
IpsRF
*4
50
100
3
500
1200
40
finIF
Operating
*4
MHz
dBm
finRF
RF–PLL
–
finRF
frequency
OSCin
fOSC
–
IF–PLL, 50 Ω load system
(Refer to the TEST CIRCUIT)
finIF
VfinIF
–10
–10
–
–
+2
Input sensitivity
Input voltage
RF–PLL, 50 Ω load system
(Refer to the TEST CIRCUIT)
finRF
VfinRF
+2
dBm
Vp-p
OSCin
VOSC
VIH
0.5
–
–
VCC
Data,
Clock,
LE
Schmitt trigger input
Schmitt trigger input
VCC×0.7+0.4
V
V
VIL
–
–
VCC×0.3–0.4
VIH
VIL
VCC×0.7
–
–
–
PSIF,
PSRF
VCC×0.3
*5
Data,
Clock,
LE,
PSIF,
PSRF
–1.0
+1.0
IIH
µA
*5
–1.0
–
+1.0
IIL
Input current
IIH
0
–100
VCC–0.4
–
–
–
–
–
–
–
+100
0
OSCin
LD/fout
µA
*5
IIL
VOH
VOL
Vcc = 3.0 V, IOH = –1 mA
Vcc = 3.0 V, IOL = 1 mA
Vcc = 3.0 V, IOH = –1 mA
Vcc = 3.0 V, IOL = 1 mA
V
0.4
Output voltage
VDOH
VDOL
VCC–0.4
–
DoIF,
DoRF
V
0.4
1.1
DoIF,
DoRF
Vcc = 3.0 V
VOFF = GND to Vcc
High impedance
cutoff current
IOFF
–
–
µA
mA
*5
Vcc = 3.0 V
Vcc = 3.0 V
–
–
–
–1.0
–
IOH
LD/fout
IOL
1.0
Vcc = 3.0 V,
VDOH = 2.0 V, Ta = 25°C
*5
Output current
–11
8
–
–
–6
15
IDOH
DoIF,
DoRF
mA
Vcc = 3.0 V,
VDOL = 1.0 V, Ta = 25°C
IDOL
*1: Conditions ; VccIF = 3.0 V, Ta = 25°C, in locking state.
*2: Conditions; VccRF = 3.0 V, Ta = 25°C, in locking state.
*3: Conditions ; Vcc = 3.0 V, fosc = 12.8 MHz (–2 dB), Ta = 25°C
*4: AC coupling. The minimum frequency is specified with a connecting coupling capacitor of 1000 pF.
*5: The symbol “–” means direction of current flow.
6
MB15F02
■ FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(M x N) + A} x fOSC ÷ R (A < N)
fVCO:
M:
N:
A:
fOSC:
R:
Output frequency of external voltage controlled ocillator (VCO)
Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF–PLL
sections, programmable reference dividers of IF/RF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
L
CN2
L
The programmable reference counter for the IF-PLL.
H
L
The programmable reference counter for the RF-PLL.
L
H
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
H
H
Shift Register Configuration
Programmable Reference Counter
MS
LS
Data
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
10 11 12 13 14
CNT1, 2
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383) [Table. 2]
T1, 2 : Test purpose bit [Table. 3]
NOTE: Start data input with MSB first.
7
MB15F02
Programmable Counter
MS
LS
1
Data
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
L
S
F
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
D
S
W
C
10 11
CNT1, 2
: Control bit
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
N1 to N14 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7
SW
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
FC
: Phase control bit for the phase detector
: LD/fout signal select bit
[Table. 7]
[Table. 8]
LDS
NOTE: Start data input with MSB first.
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
ratio
(R)
14
13
12
11
10
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
T
1
T
2
LD/fout pin state
L
H
L
L
L
Outputs frIF.
Outputs frRF.
Outputs fpIF.
Outputs fpRF.
H
H
H
8
MB15F02
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
N
N
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
11
10
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(A)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = ”H”
16/17
SW = ”L”
32/33
IF-PLL
Prescaler
divide ratio
RF-PLL
64/65
128/129
9
MB15F02
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF/RF = H
FCIF/RF = L
DoIF/RF
(1)
fr > fp
fr = fp
H
Z
L
Z
fr < fp
L
H
VCO Output
Frequency
VCO polarity
(1)
(2)
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
(2)
FC bit should be set.
VCO Input Voltage
Table. 8 LD/fout Output Select Data Setting
LD/fout output signal
fout (frIF/RF, fpIF/RF) signals
LD signal
LDS
H
L
Serial Data Input Timing
Data
MSB
LSB
Clock
LE
t3
t4
t5
t2
t1
t7
t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Parameter
Min.
Typ. Max.
Unit
Min.
100
20
Typ. Max.
Unit
t1
t2
t3
t4
ns
ns
ns
ns
t5
t6
t7
ns
ns
ns
20
20
30
30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
100
10
MB15F02
■ PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DoIF/RF
Z
L
(FC bit = Low)
DoIF/RF
Z
LD Output Logic Table
IF–PLL section
LD output
RF–PLL section
Locking state / Power saving state
Locking state / Power saving state
H
L
Locking state / Power saving state Unlocking state
Unlocking state
Unlocking state
Locking state / Power saving state
Unlocking state
L
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz
tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz
11
MB15F02
■ POWER SAVING MODE (INTERMITTENT MODE CONTROL CIRCUIT)
Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption can
be limited to 10µA (typ.). Setting PS pin to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode.
In general, the power consumption can be saved by the intermittent operation that powering down or waking up the
synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is
unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp)
and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up. Thus keeping the loop locked.
Allow 1 µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H)
Serial data can be entered during the power saving mode.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF’s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
Note: PS pin must be set “L” at Power-ON. The power saving mode should be released at 1 µs after the power
supply becomes stable.
PSIF
L
PSRF
L
IF-PLL counters
RF-PLL counters
OSC input buffer
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
H
L
L
H
OFF
ON
H
H
ON
ON
V CC
Clock
Data
LE
PS
i1 j
i2 j
i3 j
(1) PS = L (power saving mode) at Power-ON.
(2) Set serial data after power supply remains stable.
(3) Release saving mode (PS: LfiH) after setting serial data.
12
MB15F02
■ TYPICAL CHARACTERISTICS
Input sensivity of FIN (IF) vs. Input frequency
Main. counter div. ratio=1032
Swallow=“ON”, RF: Active
fosc=19.8 MHz (–2dB)
[Ta = +25°C]
x
+10
0
SPEC
x
x
–10
–20
–30
–40
x
x
x
x
x
x
x
VCC=2.7 V
x
x
VCC=3.0 V
VCC=3.6 V
1000
0
1500
2000
500
fin (MHz)
Input sensivity of FIN (RF) vs. Input frequency
Main. counter div. ratio=4104
Swallow=“ON”, IF: Active
[Ta = +25°C]
fosc=19.8 MHz (–2dB)
x
+10
0
SPEC
–10
x
x
x
x
VCC=2.7 V
–20
–30
–40
x
x
VCC=3.0 V
VCC=3.6 V
x
x
x
x
3000
0
1000
2000
fin (MHz)
(Continued)
13
MB15F02
(Continued)
Input sensivity of OSC (IF) vs. Input frequency
Ref. counter div. ratio=2048
RF: fin = 1005 MHz (VCO)
IF: fin = 270 MHz (VCO), Xfin = 1000 PF Pull DOWN
[Ta = +25°C]
x
+10
0
SPEC
x
x
x
–10
–20
–30
–40
–50
–60
x
x
x
x
VCC=2.7 V
VCC=3.0 V
VCC=3.6 V
x
x
x
100
fosc (MHz)
0
50
150
200
Input sensivity of OSC (RF) vs. Input frequency
Ref. counter div. ratio=2048
RF: fin = 1005 MHz (VCO)
[Ta = +25°C]
IF: fin = 270 MHz (VCO), Xfin = 1000 PF Pull DOWN
x
+10
SPEC
x
0
x
x
x
x
–10
–20
–30
–40
–50
–60
x
x
x
x
VCC=2.7 V
VCC=3.0 V
VCC=3.6 V
x
x
x
100
fosc (MHz)
0
50
150
200
14
MB15F02
(Continued)
Do output Current (IF)
Conditions: Ta = +25°C
VCC= 2.7, 3.0, 3.6 V
5.000
3.6 V
3.0 V
.5000
/div
VCC = 2.7 V
• DO = VCC = 1 V
• OSCin = 12.8 MHz (+10 dB)
• fin [IF/RF] = “H” (= VCC)
.0000
.0000
2.500/div
IOH (mA)
(mA)
–25.00
5.000
.5000
/div
3.6 V
3.0 V
VCC = 2.7 V
• DO = 1 V
• fin [IF] = 500 MHz (–10 dB)
• OSCin, fin [RF] = “H” (= VCC)
.0000
.0000
2.500/div
IOL (mA)
(mA)
25.00
(Continued)
15
MB15F02
(Continued)
Do output Current (RF)
Conditions: Ta = +25°C
VCC= 2.7, 3.0, 3.6 V
5.000
3.6 V
3.0 V
.5000
/div
VCC = 2.7 V
• DO = VCC = 1 V
• OSCin = 12.8 MHz (+10 dB)
• fin [IF/RF] = “H” (= VCC)
.0000
.0000
2.500/div
IOH (mA)
(mA)
–25.00
5.000
.5000
/div
3.6 V
3.0 V
VCC = 2.7 V
• DO = 1 V
• fin [RF] = 1.2 GHz (–10 dB)
• OSCin, fin [IF] = “H” (= VCC)
.0000
.0000
2.500/div
IOL (mA)
(mA)
25.00
16
MB15F02
(Continued)
Input Impedance
3: 26.805 Ω –178.48 Ω 2.2294 pF
400.000 000 MHz
1: 778.28 Ω
–824.12 Ω
50 MHz
2:
4:
87.25 Ω
–357.03 Ω
200 MHz
finIF Pin
19.305 Ω
–138.94 Ω
500 MHz
1
2
3
4
4: 11.686 Ω –40.426 Ω 3.2808 pF
1 200.000 000 MHz
1:
312.84 Ω
–627.28 Ω
100 MHz
2:
3:
30.344 Ω
–183.38 Ω
400 MHz
finRF Pin
12.746 Ω
–81 Ω
800 MHz
1
2
4
3
2: 316.75 Ω –5.9348 kΩ 2.6817 pF
10.000 000 MHz
1:
3:
4:
7.401 kΩ
–20.347 kΩ
3 MHz
116.75 Ω
–3.0649 kΩ
20 MHz
2
OSCin Pin
1
4
083.88 Ω
–1.5473 kΩ
40 MHz
3
17
MB15F02
■ REFERENCE INFORMATION
•
•
•
•
•
fvco = 1018 MHz
Kv = 20 MHz/v
fr = 200 kHz
fosc = 13 MHz
LPF:
Typical plots measured with the
test circuit are shown below.
Each plot shows lock up time,
phase noise and reference
Test Circuit
LPF
S.G
OSCin
Do
leakage.
fin
15 kΩ
2.2 kΩ
Spectrum
Analyzer
VCO
330 pF
2000 pF
20000 pF
PLL Lock Up Time = 440 µs
(1005.000 MHz → 1031.000 MHz, within ± 1kHz)
PLL Phase Noise
@ within loop band = 75.5 dBc/Hz
–10.0 dBm
∆ MKr x : 439.90929 µs
A evts N/A
REF
10dB/
ATT 10 dB
y : 25.99986 MHz
30.00300
MHz
RBW
300 Hz
1.000
kHz/div
SAMPLE
VBW
300 Hz
29.99800
MHz
SPAN 50.0 kHz CENTER 1.0180000 GH z
10.2449 µs
1.9902449 ms
PLL Lock Up Time = 440 µs
(1031.000 MHz → 1005.000 MHz, within ± 1kHz)
PLL Reference Leakage
@ 200 kHz offset = 71.4 dBc
∆ MKr x : 440.02236 µs
–10.0 dBm
REF
ATT 10 dB
y : –26.00006 MHz
10dB/
30.00300
MHz
RBW
10 kHz
SAMPLE
VBW
1.00
kHz/div
10 kHz
29.99800
MHz
SPAN 1.00 MHz CENTER 1.01800 GHz
1.9901378 ms
10.1378 µs
18
MB15F02
■ TEST CIRCUIT (PRESCALER INPUT/PROGRAMMABLE REFERENCE DIVIDER INPUT SENSITIVITY TEST)
fout
Oscilloscope
VccIF
1000pF
0.1µF
P. G
50Ω
1000pF
GND
P. G
8
9
7
6
5
MB15F02
12
3
2
1
4
50Ω
10
11
13 14
15
16
P. G
1000pF
Controller (divide
ratio setting)
50Ω
VccRF
1000pF
0.1µF
Note: SSOP-16 pin
19
MB15F02
■ APPLICATION EXAMPLE
OUTPUT
LPF
VCO
3 V
from controller
1000 pF
0.1µF
1000 pF
Clock Data
LE
finRF
VccRF
12
XfinRF
11
PSRF
10
DoRF
9
16
15
14
13
MB15F02
5
1
2
3
4
6
7
8
GNDRF OSCIN GNDIF finIF
VccIF LD/fout PSIF
DoIF
3 V
Lock Det.
1000 pF
1000 pF
0.1µF
TCXO
OUTPUT
LPF
VCO
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
Note: SSOP-16 pin
20
MB15F02
■ ORDERING INFORMATION
Part number
Package
Remarks
16 pin, Plastic SSOP
(FPT-16P-M05)
MB15F02 PFV
16 pin, Plastic BCC
(LCC-16P-M03)
MB15F02 PV
21
MB15F02
■ PACKAGE DIMENSIONS
* : These dimensions do not include resin protrusion.
16 pins, Plastic SSOP
(FPT-16P-M05)
+0.20
*
5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049–.004
0.10(.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
+0.05
0.22+–00..0150
.009+–..000024
0.15–0.02
Details of "A" part
0.10±0.10(.004±.004)
0.65±0.12
(.0256±.0047)
+.002
.006–.001
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
Dimensions in mm (inches)
(Continued)
C
1994 FUJITSU LIMITED F16013S-2C-4
22
MB15F02
16-pin, Plastic BCC
(LCC-16P-M03)
4.55±0.10
(.179±.004)
0.80(.032)MAX
(Mounting height)
3.40(.134)TYP
0.65(.026)TYP
14
9
9
14
0.40±0.10
(.016±.004)
3.25(.128)
TYP
4.20±0.10
(.165±.004)
1.55(.061)TYP
45˚
"A"
"B"
0.80(.032)
TYP
E-MARK
0.40(.016)
0.325±0.10
(.013±.004)
1.725(.068)
TYP
1
6
6
1
0.085±0.040
(.003±.002)
(STAND OFF)
Details of "A" part
Details of "B" part
0.75±0.10
(.030±.004)
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
C
1996 FUJITSU LIMITED C16014S-1C-1
23
MB15F02
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
Fax: (408) 432-9044/9045
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9704
FUJITSU LIMITED Printed in Japan
相关型号：
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