MB15F02L [FUJITSU]
Dual Serial Input PLL Frequency Synthesizer; 双串行输入锁相环频率合成器
| 型号： | MB15F02L |
| 厂家： | 
FUJITSU |
| 描述： | Dual Serial Input PLL Frequency Synthesizer |
| 文件： | 总24页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–21353–1E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F02L
■ DESCRIPTION
The Fujitsu MB15F02L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz and a 250
MHz prescalers. A 64/65 or a 128/129 for the 1.2 GHz prescaler, and a 16/17 or a 32/33 for 250 MHz prescaler can
be selected that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 4.0 mA typ. at a
supply voltage of 3.0 V.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result
of this, MB15F02L is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile
Communications).
■ FEATURES
• High frequency operation
RF synthesizer: 1.2 GHz max. / IF synthesizer: 250 MHz max.
• Low power supply voltage: VCC = 2.7 to 3.6 V
• Very Low power supply current : ICC = 4.0 mA typ. (VCC = 3 V)
• Power saving function : Supply current at power saving mode Typ.0.1 µA (VCC = 3 V), Max.10 µA (IPS1 = IPS2)
• Dual modulus prescaler : 1.2 GHz prescaler (64/65,128/129) , 250 MHz prescaler (16/17,32/33)
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047
• On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and low
phase noise
• On–chip phase control for phase comparator
• Wide operating temperature: Ta = –40 to 85°C
■ PACKAGES
16-pin, Plastic SSOP
16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M03)
1
MB15F02L
■ PIN ASSIGNMENTS
SSOP-16 pin
GNDRF
OSCin
Clock
1
2
3
16
15
14
Data
LE
GNDIF
finIF
4
5
6
7
13
12
11
10
finRF
TOP
VIEW
VccRF
XfinRF
VccIF
LD/fout
PSRF
DoRF
PSIF
DoIF
8
9
(FPT-16P-M05)
BCC-16 pin
GNDRF Clock
16
15
OSCin
Date
1
2
3
14
13
12
GNDIF
finIF
LE
finRF
view
Top
7
VCCIF
LD/fout
PSIF
4
5
6
11
10
9
VCCRF
XfinRF
PSRF
8
DoIF DoRF
(LCC-16P-M03)
2
MB15F02L
■ PIN DESCRIPTIONS
Pin no.
Pin name I/O
Descriptions
SSOP BCC
1
2
3
4
5
16
1
GNDRF
OSCin
GNDIF
finIF
–
I
Ground for RF-PLL section.
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
2
–
I
Ground for the IF-PLL section.
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
3
4
VCCIF
–
Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD) / phase comparator monitoring output (fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
6
7
5
6
LD/fout
PSIF
O
I
LDS bit = “L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
at “L” Power-ON. (Open is prohibited.)
PSIF = “H” ; Normal mode
PSIF = “L” ; Power saving mode
Charge pump output for the IF-PLL section.
8
9
7
8
DOIF
O
O
Phase characteristics of the phase detector can be reversed by FC-bit.
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
DORF
Power saving mode control for the RF-PLL section. This pin must be set
at “L” Power-ON. (Open is prohibited.)
10
9
PSRF
I
PSRF = “H” ; Normal mode
PSRF = “L” ; Power saving mode
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
11
12
13
14
10
11
12
13
XfinRF
VCCRF
finRF
LE
I
–
I
Power supply voltage input pin for the RF-PLL section, the shift register and
the oscillator input buffer. When power is OFF, latched data of RF-PLL is
cancelled.
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
When LE is “H”, data in the shift register is transferred to the corresponding
latch according to the control bit in a serial data.
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit in a
serial data.
15
16
14
15
Data
I
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
Clock
3
MB15F02L
■ BLOCK DIAGRAM
VCCIF GNDIF
3
5
7-bit latch
3-bit latch
11-bit latch
Intermittent
mode
fpIF
7
Binary 11-bit
programmable
counter(IF–PLL)
Binary 7-bit
swallow counter
(IF–PLL)
control
PSIF
Charge
pump
(IF–PLL)
Phase
SWIF FCIF
LDS
Super
charger
(IF–PLL)
comp.
8
DoIF
(IF–PLL)
Prescaler
(IF–PLL)
16/17,32/33
finIF
4
Lock
Det.
2-bit latch
14-bit latch
(IF–PLL)
LDIF
Binary 14–bit pro-
grammable ref.
counter(IF–PLL)
frIF
T1
T2
2
OSCin
AND
Selector
LD
frIF
frRF
fpIF
fpRF
OR
frRF
6
LD/fout
Binary 14-bit pro-
grammable ref.
counter(RF–PLL)
T1
T2
LDRF
2-bit latch
14-bit latch
Lock
Det.
Prescaler
(RF–PLL)
64/65,
128/129
finRF13
11
XfinRF
Binary 11-bit
Binary 7-bit
Phase
Charge
Super
charger
LDS SWRF FCRF
3-bit latch
programmable
counter(RF–PLL)
swallow counter
DoRF
9
comp.
pump
(RF–PLL)
Intermittent
mode
(RF–PLL)
(RF–PLL)
fpRF
PSRF
10
control
7-bit latch
11-bit latch
(RF–PLL)
Schmitt
circuit
Latch selector
LE14
Schmitt
circuit
Data
C
N
C
N
15
16
23-bit shift
register
Schmitt
circuit
1
2
Clock
12
1
VCCRF
GNDRF
Note : SSOP-16 pin
4
MB15F02L
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Rating
Parameter
Symbol
Unit
Remark
Min.
–0.5
–0.5
–0.5
–10
–25
–55
Max.
+4.0
Power supply voltage
Input voltage
VCC
VI
V
V
VCC +0.5
VCC +0.5
+10
Output voltage
VO
IO
V
mA
mA
°C
Except Do output
Do output
Output current
Ido
+25
Storage temperature
TSTG
+125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ.
3.0
–
Max.
3.6
Power supply voltage
Input voltage
VCC
VI
V
V
GND
–40
VCC
Operating temperature
Ta
–
+85
°C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
Handling Precautions
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15F02L
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
finIF = 250 MHz,
fosc = 12 MHz
*1
–
1.5
–
ICCIF
Power supply current
mA
finRF = 1200 MHz,
fosc = 12 MHz
*2
–
–
–
2.5
–
ICCRF
0.1*3
0.1*3
IpsIF
VCCIF current at PSIF = “L”
10
10
Power saving current
µA
VCCRF current at PSIF/RF =
“L”
IpsRF
*4
finIF
finRF
fOSC
IF-PLL
50
–
–
–
–
–
–
–
250
1200
40
finIF
Operating
frequency
*4
MHz
RF-PLL
100
finRF
OSCin
finIF
–
3
–10
VfinIF
VfinRF
VOSC
VIH
IF-PLL, 50 Ω termination
RF-PLL, 50 Ω termination
–
+2
dBm
dBm
Vp-p
Input sensitivity
Input voltage
finRF
–10
+2
OSCin
0.5
VCC
–
VCC × 0.7 + 0.4
Data,
Clock,
LE
Schmitt trigger input
V
V
VCC × 0.3 – 0.4
VIL
Schmitt trigger input
–
–
VIH
VIL
–
–
–
VCC × 0.7
–
–
–
–
PSIF,
PSRF
VCC × 0.3
+1.0
*5
Data,
Clock,
LE,
PSIF,
PSRF
–1.0
IIH
µA
*5
–
–1.0
–
+1.0
IIL
Input current
IIH
–
0
–100
VCC – 0.4
–
–
–
–
–
+100
0
OSCin
LD/fout
µA
*5
–
IIL
VOH
VCC = 3.0 V, IOH = –1.0 mA
VCC = 3.0 V, IOL = 1.0 mA
–
V
VOL
0.4
Output voltage
VCC = 3.0 V,
VDOH
VDOL
IOFF
VCC – 0.4
–
–
–
–
DoIF,
DoRF
IDOH = –1.0 mA
V
VCC = 3.0 V, IDOL = 1.0 mA
–
–
0.4
3.0
High impedance DoIF,
cutoff current
VCC = 3.0 V,
VOFF = GND to VCC
nA
DoRF
*5
VCC = 3.0 V
VCC = 3.0 V
–1.0
–
–
–
–
IOH
LD/fout
mA
IOL
1.0
VCC = 3.0 V, VDOH = 2.0 V,
*5
Output current
–11
8
–
–
–6
15
IDOH
Ta = 25°C
DoIF,
DoRF
mA
VCC = 3.0 V, VDOL = 1.0 V,
Ta = 25°C
IDOL
*1: Conditions ; VCCIF = 3 V, Ta = 25°C, in locking state.
*2: Conditions ; VCCRF = 3 V, Ta = 25°C, in locking state.
*3: fosc = 12.8 MHz , VCC = 3.0 V, Ta = 25°C
*4: AC coupling with a 1000 pF capacitor connected.
*5: The symbol “–” (minus) means direction of current flow.
6
MB15F02L
■ FUNCTIONAL DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = {(M × N) + A} × fOSC ÷ R (A < N)
fVCO:
M:
N:
A:
fOSC:
R:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
L
CN2
L
The programmable reference counter for the IF-PLL.
H
L
The programmable reference counter for the RF-PLL.
L
H
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
H
H
(1) Shift Register Configuration
• Programmable Reference Counter
MSB
LSB
1
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19 20 21 22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
X
X
X
X
X
10 11 12 13 14
CNT1, 2
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383) [Table. 2]
T1, 2
X
: Test purpose bit
[Table.3]
: Dummy bits(Set “0” or “1”)
Note: Data input with MSB first.
7
MB15F02L
• Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
L
S
F
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
D
S
W
IF/ IF/
RF RF
C
10 11
CNT1, 2
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SW IF/RF : Divide ratio setting bit for the prescaler
: Control bit
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
(16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
: Phase control bit for the phase detector
: LD/fout signal select bit
FC IF/RF
LDS
[Table. 7]
[Table. 8]
Note: Data input with MSB first.
(2) Data Setting
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 5 is prohibited.
Table3.Test Purpose Bit Setting
T
1
T
2
LD/fout pin state
L
H
L
L
L
Outputs frIF.
Outputs frRF.
Outputs fpIF.
Outputs fpRF.
H
H
H
8
MB15F02L
Table4. Binary 11-bit Programmable Counter Data Setting
Divide
N
N
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
11
10
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 5 is prohibited.
Table5. Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(A)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table6. Prescaler Data Setting
SW = “H”
SW = “L”
32/33
IF-PLL
16/17
64/65
Prescaler
divide ratio
RF-PLL
128/129
Table7. Phase Comparator Phase Switching Data Setting
FCIF,RF = H
FCIF,RF = L
(1)
DoIF,RF
fr > fp
fr = fp
H
Z
L
Z
VCO output
frequency
fr < fp
L
H
VCO polarity
(1)
(2)
Note: • Z = High-impedance
(2)
• Depending upon the VCO and LPF polarity,
FC bit should be set.
VCO output voltage
Table8. LD/fout Output Select Data Setting
LDS
H
LD/fout output signal
fout (frIF/RF, fpIF/RF) signals
L
LD signal
9
MB15F02L
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption can
be limited to 10 µA (typ.). Setting PS pin to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode.
In general, the power consumption can be saved by the intermittent operation that powering down or waking up the
synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is
unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp)
and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up. Thus keeping the loop locked.
PS pin must be set “L” at Power-ON.
Allow 1 µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H)
Serial data can be entered during the power saving mode.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF’s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
PSIF
L
PSRF
L
IF-PLL counters
RF-PLL counters
OSC input buffer
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
H
L
L
H
OFF
ON
H
H
ON
ON
VCC
Clock
Data
LE
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2)Set serial data after power supply remains stable.
(3)Release saving mode(PS : L → H) after setting serial data.
10
MB15F02L
4. Serial Data Input Timing
2nd. data
1st. data
Control bit Invalid data
Data
MSB
LSB
Clock
LE
t 1
t 2
t 5
t 4
t 7
t 3
t 6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Min.
Typ. Max.
Unit
ns
Parameter
Min.
Typ. Max.
Unit
ns
t1
t2
t3
t4
t5
t6
t7
20
20
30
20
–
–
–
–
–
–
–
–
30
100
100
–
–
–
–
–
–
ns
ns
ns
ns
ns
11
MB15F02L
■ PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DoIF/RF
Z
L
(FC bit = Low)
DoIF/RF
Z
LD Output Logic Table
LD output
IF-PLL section
RF-PLL section
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Locking state / Power saving state
H
L
Unlocking state
Unlocking state
Locking state / Power saving state
Unlocking state
L
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU ≥ 4/fosc: i.e. tWU ≥ 312.5 ns when foscin = 12.8 MHz
tWL ≤ 8/fosc: i.e. tWL ≤ 625.0 ns when foscin = 12.8 MHz
12
MB15F02L
■ TEST CIRCUIT (fin, OSCIN Input Sensitivity Test)
fout
Oscilloscope
VCCIF
1000 pF
50 Ω
0.1 µF
S.G
1000 pF
S.G
GND
8
9
7
6
5
3
2
1
4
50 Ω
MB15F02L
10
11
12
13 14
15
16
S.G
1000 pF
Controller (divide
ratio setting)
50 Ω
VCCRF
1000 pF
0.1 µF
Note : SSOP-16 pin
13
MB15F02L
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Input sensitivity of fIN (RF) vs. Input frequency
10
5
Ta = +25°C
0
SPEC
–5
–10
–15
–20
–25
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
–30
–35
–40
0
500
1000
1500
2000
fin RF (MHz)
Input sensitivity of fIN (IF) vs. Input frequency
10
5
Ta = +25°C
0
SPEC
–5
–10
–15
–20
–25
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
–30
–35
–40
0
250
500
750
1000
fin IF (MHz)
2. OSCin Input Sensitivity
Input sensitivity of OSCin vs. Input frequency
+10
Ta = +25°C
SPEC
0
–10
–20
–30
–40
V CC = 2.7 V
V CC = 3.0 V
V CC = 3.6 V
0
50
100 (MHz)
Input frequency f OSC
14
MB15F02L
3. DORF Output Current
I DOH vs. V DOH
5.000
V CC = 3.0 V
Ta = +25°C
0.0
0.0
–25.0
I DOH (mA)
I DOL vs. V DOL
5.000
V CC = 3.0 V
Ta = +25°C
.0000
.0000
25.00
I DOL (mA)
15
MB15F02L
4. DOIF Output Current
I DOH vs. V DOH
V CC = 3.0 V
Ta = +25°C
5.000
.0000
.0000
–25.00
I DOH (mA)
I DOL vs. V DOL
V CC = 3.0 V
Ta = +25°C
5.000
.0000
.0000
25.00
I DOL (mA)
16
MB15F02L
5. fin Input Impedance
fin
1 :
309 Ω
–640.13 Ω
100 MHz
2 : 29.773 Ω
–186.98 Ω
400 MHz
3 : 12.648 Ω
–83.883 Ω
800 MHz
fin RF
4 : 10.252 Ω
–43.703 Ω
1.2 GHz
1
2
4
3
START 100.000 000 MHz
STOP 1 200.000 000 MHz
fin
1 : 791.22 Ω
–907.56 Ω
50 MHz
2 : 89.189 Ω
–378.02 Ω
200 MHz
3 : 58.797 Ω
–304.36 Ω
250 MHz
fin IF
START 50.000 000 MHz
STOP 500.000 000 MHz
17
MB15F02L
6. OSCIN Input Impedance
OSC IN
1 :
2 :
7.138 kΩ
–23.837 kΩ
3 MHz
257 Ω
–6.214 kΩ
10 MHz
3 :
4 :
154 Ω
–2.9594 kΩ
20 MHz
4
OSC IN
83.88 Ω
–1.5472 kΩ
40 MHz
1
2
3
START 1.000 000 MHz
STOP 50.000 000 MHz
18
MB15F02L
■ REFERENCE INFORMATION (Lock Up Time, Phase Noise, Reference Leakage)
Test Circuit
OSCin
fin
f VCO = 810.45 MHz
K V = 17 MHz/V
fr = 25 kHz
S.G
f OSC = 14.4 MHz
LPF
Do
LPF
9.1 kΩ
2.7 kΩ
0.068 µF
6800 pF
1500 pF
Spectrum
analyzer
VCO
PLL phase noise
PLL reference leakage
∆ MKR –51.83 dB
∆ MKR –74.00 dB
–5.0 dBm
10 dB/
RL
1.67 kHz
–5.0 dBm
10 dB/
RL
25.0 kHz
C/N ~ 71.8 dBc/Hz
74.0 dBc
BW ~ 4.17 KHz
CENTER 810.45000 MHz
SPAN 20.00 kHz
SWP 3.00 sec
CENTER 810.4500 MHz
RBW 1.0 kHz
SPAN 200.0 kHz
SWP 1.00 sec
RBW 100 Hz
VBW 100 Hz
VBW 1.0 kHz
PLL lock up time
PLL lock up time
826.45 MHz→810.45 MHz
810.45 MHz→826.45 MHz±1 kHz
1.64 ms
1.32 ms
30.00500
MHz
30.00500
MHz
2.00
2.000
kHz/diu
kHz/diu
29.99500
MHz
29.99500
MHz
0
s
8.0000000 ms
0
s
8.0000000 ms
50.00000
MHz
50.00000
MHz
5.00000
MHz/diu
10.00000
MHz/diu
25.00000
MHz
0
Hz
0
s
8.0000000 ms
0
s
8.0000000 ms
19
MB15F02L
■ APPLICATION EXAMPLE
Output
LPF
VCO
3 V
From controller
1000 pF
0.1 µF
1000 pF
Clock Data
16 15
LE
14
finRF
VCCRF
XfinRF
PSRF
DoRF
13
12
11
10
9
MB15F02L
5
1
2
3
4
6
7
8
GNDRF OSCIN
GNDIF
finIF
VCCIF
LD/fout
PSIF
DoIF
3 V
Lock Det.
1000 pF
1000 pF
TCXO
0.1 µF
Output
LPF
VCO
Note : SSOP-16 pin
20
MB15F02L
■ ORDERING INFORMATION
Part number
Package
Remarks
16 pin, Plastic SSOP
(FPT-16P-M05)
MB15F02LPFV1
16 pin, Plastic BCC
(LCC-16P-M03)
MB15F02LPV
21
MB15F02L
■ PACKAGE DIMENSIONS
16 pins, Plastic SSOP
(FPT-16P-M05)
*: These dimensions do not include resin protrusion.
1.25–+00..1200
.049+–..000048
0.10(.004)
*
5.00±0.10(.197±.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
0.22–+00..0150
0.15+–00..0025
Details of "A" part
0.65±0.12
(.0256±.0047)
.009–+..000024
.006–+..000012
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
Dimensions in mm (inches).
(Continued)
C
1994 FUJITSU LIMITED F16013S-2C-4
22
MB15F02L
(Continued)
16 pins, Plastic BCC
(LCC-16P-M03)
4.55±0.10
(.179±.004)
0.80(.032)MAX
(Mounting height)
3.40(.134)TYP
0.65(.026)TYP
14
9
9
14
0.40±0.10
(.016±.004)
3.25(.128)
TYP
4.20±0.10
(.165±.004)
1.55(.061)TYP
45˚
"A"
"B"
0.80(.032)
TYP
E-MARK
0.40(.016)
0.325±0.10
(.013±.004)
1.725(.068)
TYP
1
6
6
1
0.085±0.040
(.003±.002)
(STAND OFF)
Details of "A" part
Details of "B" part
0.75±0.10
(.030±.004)
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
0.60±0.10
(.016±.004)
(.024±.004)
Dimensions in mm (inches).
C
1996 FUJITSU LIMITED C16014S-1C-1
23
MB15F02L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9706
FUJITSU LIMITED Printed in Japan
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