FMS2701QSC [FAIRCHILD]
Power Supply Support Circuit, Adjustable, 2 Channel, CMOS, PDSO16, QSOP-16;
| 型号： | FMS2701QSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Supply Support Circuit, Adjustable, 2 Channel, CMOS, PDSO16, QSOP-16 光电二极管 |
| 文件： | 总24页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FMS2701
Temperature and Power Supply Voltage Monitor
Features
Description
• Remote diode temperature sensing
• Ambient (on-chip) temperature sense
• Dual 3.3 volt supply monitoring
• SMBus interface to internal registers
• Status registers
The FMS2701 is a temperature- and voltage-monitoring
device that can be interrogated and controlled through an
SMBus serial interface. Outputs are an analog fan control
voltage, thermal alarm and interrupts.
• Thermal trip output
• Interrupt output
• Fan speed control output
• ACPI Thermal Management compliant
Remote (DIODE+ and DIODE-) and ambient diode temper-
ature sensor inputs are selected in sequence at a 1Hz rate by
a multiplexer that drives an A/D converter. Digitized diode
temperatures are stored in registers. Violation of a program-
mable limit or trip point will set an interrupt register bit and/
or assert a digital output.
Applications
Power supply voltages are monitored through two pins:
VCCAUX3 monitors the power to the FMC2701; VCC3 is a
separate 3.3 volt sense voltage input. AUXRST and RST out-
puts indicate the status of voltage monitoring.
• PCs and Servers, Workstations
• Office Equipment
• Test and Measurement Instruments
Analog output, FAN_SPD can be used as an input to a fan
speed control circuit while THERM, INT and FAN_OFF are
additional digital control outputs.
Power is derived from a +3.3V supply. Package is 16-lead
Quad Small Outline Pack (QSOP).
Block Diagram
VCC3AUX
Aux Reset
AUXRST
Oscillator
INTRST
VCC3
Main Reset
RST
Timing
and Control
MR
Current
Generators
D/A
Register
D/A
Converter
FAN_SPD
DIODE+
DIODE-
Low-pass
Filter
Interrupt
Status
Registers
A/D
Converter
Limit
Comparators
Mux
THERM
DSP
On-chip
Bias &
Diode
Interrupt
Mask
Register
Value & Limit
Registers
ADD
Mask
Gating
SDA
SCL
SMBus
Interface
INT
Internal Bus
GPI
Configuration
Register
FAN_OFF
Lit. No. 600402-001
Rev. 1.0.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
PRODUCT SPECIFICATION
FMS2701
Following the A/D converter is a DSP block which averages
digitized temperature over several samples.
Architectural Overview
Overall operation of the FMS2701 is controlled by the
SMBus which sets register values and interrupt masking.
Four sensing inputs are monitored:
Upper and lower temperature limits are loaded into the limit
registers. If a limit is violated, an interrupt is generated. Remote
diode open or short circuit fault condition is also sensed.
1. Remote temperature diode voltage
2. Ambient temperature sensing diode voltage
3. Remote 3.3 volt power supply voltage
4. Local 3.3 volt power supply
Power Supply Voltage Monitors
Two Voltage Monitors operating over a 1.0 to 3.8 volt
supply range, sense VCC3 and VCC3AUX voltages. If
input VCC3 < 2.93 volt or master reset input, MR = L, then
RST= L until 140 msec after sensing the fault condition.
Following comparisons against either preset or programma-
ble thresholds, the following hardware outputs are set:
1. Master reset
2. Auxiliary reset
3. Temperature trip point violated (THERM)
4. Interrupt (INT)
If the FMS2701 supply, VCC3AUX < 2.93 volt, AUXRST = L
until 140 msec. after sensing the fault condition, and the main
reset RST = L until 180 msec. after AUXRST is cleared.
When AUXRST = L, internal reset, INTRST =L. AUXRST
is bi-directional, accepting a hard reset input.
Also set are the following register bits:
1. GPI active (General Purpose Input)
2. Remote Temperature limit exceeded
3. THERM input asserted
SMBus Interface
FMS2701 Registers are accessed through the SMBus inter-
face located at the address 0x2C + n; where n = 0, 1, 2
depending upon the state of ADD, a tri-level input. Within
the FMS2701, registers are accessed through an 8-bit bus.
4. Remote diode fault
Fan Speed control voltage, FAN_SPD is set in the range
0–2.5V by loading the D/A Register through the SMBus.
External THERM = L forces FAN_SPD = 2.5V. A Master
Reset clears the D/A Register.
Addressable Memory
Within the FMS2701, there are three sections of addressable
memory which implement the following functions.
Temperature Channel
There are two temperature sense inputs: one for remote sens-
ing; the other for measuring ambient temperature. Both
inputs utilize the thermal variation of the voltage drop across
a diode, to derive the diode temperature.
Command Register (5 locations)
• Configuration
• Interrupt status
• Interrupt mask
• Interrupt status mirror
• Extended function
Instead of sensing the change in V at one current, which is
D
approximately –2mV/°C, V is sampled at two currents
D
(I
MAX
= 10 and I
= 100 µA) to cancel out common error
MIN
Read only RAM (2 locations)
voltages. Difference voltage between the two currents is
proportional to absolute temperature:
• Company ID
• Revision No.
nkT
q
IMAX
IMIN
∆VD =
ln
Value RAM (13 locations)
• Diode temperature, °C
Where:
• THERM temperature trip points, °C
• INT temperature limits, °C
• Analog output D/A converter
n = PN junction ideality factor, typically 1.0065 for the
Pentium II thermal diode. Nominal diode sensitivity is
199.7 µV/°C.
Write accessible locations have default values that may be
overridden by programming through the SMBus interface.
2
FMS2701
PRODUCT SPECIFICATION
Pin Assignment
1
2
3
4
5
6
7
8
FAN_OFF
MR
16
15
14
13
12
11
10
9
SDA
SCL
AUXRST
GND
INT
ADD/NTESTOUT
GPI
VCC3AUX
VCC3
THERM
DIODE(+)
DIODE(-)
RST
FAN_SPD/NTEST_IN
Pin Descriptions
Pin No.
Reset
7
Pin Name
Type/Value
Pin Function Description
RST
Output
Reset. Output pulse from Main Reset Generator, which
is tripped by either MR =L or Internal Reset or VCC3 <
2.93 V. When active, RST = L and register D
cleared.
is
7-0
3
2
AUXRST
MR
Bi-directional
Input
Auxiliary Reset Input/Output. As an output, AUXRST =
L pulse is triggered by VCC3AUX < 2.93 V. As an input,
AUXRST = L trips Internal Reset. NAND test input,
NTEST_IN is sampled by trailing edge of AUXRST pulse.
Manual Reset. Input to Master Reset Generator. If MR =
L, a master reset cycle is initiated. MR pin has a 20 kΩ
pull-up to VCC3AUX.
Analog I/O
10
DIODE+
Voltage input/
current source
Positive diode sense input. Current source to remote
temperature sensing diode anode and upper voltage
sense input.
9
DIODE-
Voltage input/
current sink
Negative diode sense input. Current sink from remote
temperature sensing diode cathode and lower voltage
sense input.
8
FAN_SPD/NTEST_IN Analog output/
digital input
Fan speed control voltage output/NAND Test Input.
Proportional to the value in register 0x19, output is
0–2.5V. External THERM = L forces a 2.5 volt output. If
NTEST_IN = H, the NAND tree test input is enabled for
ATE.
Serial Port
16
15
13
SDA
Bi-directional
Input
Data. SMBus data to/from FMS2701
Clock. SMBus clock into FMS2701
SCL
ADD/NTEST_OUT
Tri-level
SMBus Address Input/NAND Test Output. Lowest two
bits of serial port address with three states: 00, 01 and
10, corresponding to H, L and Z inputs. If NTEST_IN is
sampled HIGH, the NAND tree test output is enabled.
Digital I/O
11
THERM
I//O (Open drain)
Open drain
Thermal Overload. THERM = L indicates that a
temperature trip point has been exceeded. Input THERM
= L sets the THERM bit in the Interrupt Status Register.
14
INT
System interrupt. INT = L when a voltage, temperature
limit or temperature trip point is violated and bit 1 of the
Configuration Register is set H.
3
PRODUCT SPECIFICATION
FMS2701
Pin No.
Pin Name
Type/Value
Input
Pin Function Description
12
GPI
General Purpose Input. Sets a bit in the interrupt
registers. Assertion polarity is set by the GPI_INV bit.
(default is GPI = H causes interrupt)
1
FAN_OFF
Open Drain Output Fan off request. FAN_OFF reflects the state of the
Configuration Register FAN_OFF bit. FAN_OFF = L is a
request to shut the fan off.
Power and Ground
6
VCC3
+3.3 V Input
Voltage Monitor Input. Voltage monitor input to Main
Reset Generator. If VCC3 drops below 2.93V. a Main
Reset cycle is initiated.
4
5
GND
0 V
Ground. Return for 3.3 volt supply, VCC3AUX.
VCC3AUX
+3.3 V Power
Auxiliary 3.3 volt. Power source for FMS2701. If
VCC3AUX drops below 2.93 volt, an Auxiliary Reset
cycle is initiated.
Addressable Memory
Addressable memory is divided into two sections:
1. Command, consisting of five registers
2. Value RAM, consisting of thirteen locations, of which: eleven are used to store temperature data, limits and trip points;
two are used to store the company ID, version and revision number.
Table 1. Addressable Memory Map
Name
Address
0x40
0x41
0x43
0x4C
0x13
0x14
0x17
0x18
0x19
0x26
0x27
0x37
0x38
0x39
0x3A
0x3E
0x3F
Power-up Value, [7:0]
Configuration Register
Interrupt Status Register
Interrupt Mask Register
Interrupt Status Register Mirror
0x25
0x00
0x00
0x00
0x46
0x64
0x46
0x64
0x00
0x46
0x3C
0x50
0x3C
0x46
0x32
0xFC
0xCn
PTA
PTR
7-0
7-0
7-0
7-0
FTA
FTR
DAC
7-0
TR
TA
7-0
7-0
TRHI
7-0
TRLO
7-0
TAHI
7-0
TALO
7-0
Manufacturer ID
Version, Revision
Register Definitions
Configuration Register (0x40)
BIT#
Name
Type
Description
0
START
R/W
Start Temperature and Voltage Monitoring
0: Standby mode. (INT is not cleared)
1: Run (Power-up default). All limit and trip values should be entered into
FMS2701 registers prior to setting START = 1.
4
FMS2701
PRODUCT SPECIFICATION
BIT#
Name
Type
Description
1
INT_EN
R/W
Interrupt Enable
0: Disabled (Power-up default)
1: Enables the INT output.
2
3
INT_CLR
R/W
Interrupt Clear
0: INT output unaffected.
1: Clears the INT output. Contents of the Interrupt Status Register
preserved. (Power-up default = 1)
TRIP_LOCK
R/(W-once)
Temperature Trip Point Lock
0: THERM trip points set by fixed value registers FTA
7-0
and FTR .
7-0
Writes to programmable registers PTA
(Power-up default = 0)
and PTR are enabled.
7-0
7-0
1: THERM trip points set by values preserved in programmable registers
PTA and PTR , while RST = H.
7-0
7-0
4
5
SOFT_RST
FAN_OFF
R/W
R/W
R/W
Soft Reset
0: Power-up default restored by SOFT_RST cycle.
1: Restore power-up values to the Configuration, Interrupt Status,
Interrupt Status Mirror and Interrupt Mask registers.
Fan Off
0: Set output pin FAN_OFF = L. (fan-off)
1: Set output pin FAN_OFF = Z. (Power-up default, fan-on)
If pin THERM = L, then FAN_OFF = H.
6
7
GPI_INV
Reserved
GPI Polarity Invert
0: GPI input passed to Interrupt registers. (Power-up default)
1: Invert the GPI input passed to Interrupt registers
R/W
Reserved (Default=0)
1
Interrupt Status Register (0x41)
BIT#
Name
ATV
Type
Description
0
R
Ambient Temperature Violation
0: On-chip temperature within limits.
1: On-chip temperature limit violated
1
2
3
4
Reserved
Reserved
Reserved
GPI
R
R
R
R
Reserved for Remote Thermal Diode 2 temp error
Reserved for Remote Thermal Diode 2 fault
Undefined
General Purpose Input Status.
GPI is set according to the following truth table:
GPI pin
GPI_INV
GPI bit
0
1
0
1
0
0
1
1
0
1
1
0
Reading this register will not clear the GPI bit.
5
6
RTV
R
R
Remote Temperature Violation.
0: Remote temperature within limits.
1: Remote temperature limit violated
THERM
THERM input status.
0: THERM input negated. (THERM = H)
1: THERM input asserted. (THERM = L)
5
PRODUCT SPECIFICATION
FMS2701
BIT#
Name
FAULT
Type
Description
7
R
Remote Diode Fault.
0: Diode functional
1: Remote temperature sensing diode short or open circuit.
Note:
1.
Reading this register will clear ATV, RTV THERM and FAULT bits.
Interrupt Mask Register (0x43)
BIT#
Name
Type
Description
0
MSKATV
R/W Mask Ambient Temperature Violation bit.
0: Allow ATV bit to affect INT output.
1: Prohibit ATV bit from affecting the INT output.
1
2
3
4
Reserved
Reserved
Reserved
MSKGPI
R
R
R
Undefined
Undefined
Undefined
R/W Mask GPI bit
0: Allow GPI bit to affect INT output.
1: Prohibit GPI bit from affecting the INT output.
5
6
7
MSKRTV
R/W Mask Remote Temperature Violation bit.
0: Allow RTV bit to affect INT output.
1: Prohibit RTV bit from affecting the INT output.
MSKTHERM
MSKFAULT
R/W Mask THERM bit.
0: Allow THERM bit to affect INT output.
1: Prohibit THERM bit from affecting the INT output.
R/W Mask Remote Fault bit.
0: Allow FAULT bit to affect INT output.
1: Prohibit FAULT bit from affecting the INT output.
Note:
1.
An error that causes continuous interrupts to be generated may be masked using the mask register, until the error can be
alleviated.
1
Interrupt Status Mirror Register (0x4C)
BIT#
Name
MATV
Read/Write
Description
0
R
Mirrored Ambient Temperature Violation
0: On-chip temperature within limits.
1: On-chip temperature limit violated
1
2
3
4
Reserved
Reserved
Reserved
MGPI
R
R
R
R
Reserved for Remote Thermal Diode 2 temp error
Reserved for Remote Thermal Diode 2 fault
Undefined
Mirrored General Purpose Input Status.
MGPI is set according to the following ????? table:
GPI pin
GPI_INV
MGPI
0
1
0
1
0
0
1
1
0
1
1
0
Reading this register will not clear the GPI bit.
5
MRTV
R
Mirrored Remote Temperature Violation.
0: Remote temperature within limits.
1: Remote temperature limit violated
6
FMS2701
PRODUCT SPECIFICATION
BIT#
Name
Read/Write
Description
Mirrored THERM input status.
6
MTHERM
R
0: THERM input negated. (THERM = H)
1: THERM input asserted. (THERM = L)
7
MFAULT
R
Mirrored Remote Diode Fault.
0: Diode functional
1: Remote temperature sensing diode short or open circuit.
Note:
1. Reading this register will clear MATV, MRTV, MTHERM and MFAULT bits.
Extended Function Register (0x15)
BIT#
Name
Type
Description
0
MIT
R
Mask Internal THERM
0: Internally generated THERM affects INT output.
1: Internally generated THERM does not impact INT output.
7–1
-
N/A
Reserved
Value RAM (0x13–0x4A)
Unless stated otherwise, Power-on defaults are not defined,.
Address
Name
PTA
Type
Description
0x13
R/W Programmable Ambient Temperature Automatic Trip Point. If TA
> PTA
7-0
7-0
, then THERM = L. Write access is disabled if the TRIP_LOCK bit in the
7-
0
Configuration Register been set. (default: 46h (70°C)
0x14
PTR
R/W Programmable Remote Thermal Diode Automatic Trip Point. If TR > PTR
7-0
7-
, then THERM = L. Write access is disabled if the TRIP_LOCK bit in the
7-
0
Configuration Register been set. (default: 64h (100°C)
0x17
0x18
0x19
FTA
R
R
Fixed Ambient Temperature Automatic Trip Point. (default: 46h (70°C)
Fixed Remote Thermal Diode Automatic Trip Point. (default: 64h (100°C)
7-0
FTR
7-0
7-0
DAC
R/W D/A Converter Input. Value supplied to D/A converter to generate fan speed
control voltage. (default: 00h)
0x20
0x26
N/A Reserved
TR
R
Remote Thermal Diode Temperature. Temperature output derived from
7-0
remote thermal diode.
0x27
TA
R
Ambient Temperature. Temperature output derived from on-chip thermal
7-0
diode.
0x2B
0x2C
0x37
-
N/A Reserved
-
N/A Reserved
TRHI
R/W Remote Thermal Diode High Temperature Limit. TR
> TRHI will set
7-0
7-0
7-0
the RTV and MRTV bits in the Interrupt and Mirrored Interrupt registers.
0x38
0x39
0x3A
TRLO
R/W Remote Thermal Diode Low Temperature Limit. TR < TRLO will set
7-0
7-0
7-0 7-0
the RTV and MRTV bits in the Interrupt and Mirrored Interrupt registers.
TAHI
TALO
R/W Ambient Temperature High Temperature Limit. TA
7-0
> TAHI
7-0
will set the
ATV and MATV bits in the Interrupt and Mirrored Interrupt registers.
R/W Ambient Temperature Low Temperature Limit. TA < TALO
will set the
7-0
7-0 7-0
ATV and ARTV bits in the Interrupt and Mirrored Interrupt registers.
0x3E
0x3F
MFR
NUM
R
R
Manufacturer ID. Value is FC.
7-0
Version and Revision. NUM
= C, the FMS2701 version number. NUM =
3-0
7-0
7-4
revision number
0x44 – 0x4A
0x4D – 0x53
-
-
N/A Reserved
N/A Reserved
7
PRODUCT SPECIFICATION
FMS2701
Temperature Processor
Functional Description
Remote and ambient thermal diode voltages are processed
by the Temperature Processor which outputs values of
remote and ambient temperature alternately. Inputs are
derived from a remote diode that is connected by two wires
to the input of the processor; and the ambient diode, which is
located on-chip. Output is supplied to the Data Processor
Operation of the FMS2701 is divided into three sections:
• Temperature Processor
• Reset Generators
• Data Processor
which loads the TA and TR registers with the digitized
7-0 7-0
ambient and remote temperatures.
Current
Generators
Remote
PN
Junction
TEMP7-0
A/D
Converter
DSP
RMT_ERROR
Mux
Ambient
PN
Junction
29220
XDIODE
Figure 1. Temperature Processor Block Diagram
Table 2. Temperature/Data Conversion/Format
A multiplexer selects the thermal diode to be sensed. Voltage
of the diode is sensed at two currents:10 and 100 µA. During
the diode sampling interval, the A/D converter digitizes low
and high current samples. DSP averages and subtracts the
samples to output an 8-bit temperature that is updated a rate
greater than 1 Hz. Remote and Ambient diode temperatures
are outputted alternately on the TEMPR[7:0] bus which is
connected to the Data Processor.
Temperature
Digital Output
Binary
Hex
0x7D
0x19
0x01
0x00
0xFF
0xE7
0xC9
+125°C
+25°C
+1.0°C
0°C
0111 1101
0001 1001
0000 0001
0000 0000
1111 1111
1110 0111
1100 1001
Remote Diode fault sensing is included within the DSP
block. If the remote diode voltage indicates either a short or
an open circuit, the RMT_ERROR signal causes the
RMT_FAULT bit to be set in the Interrupt Status Register.
-1.0°C
-25°C
-55°C
Temperature data format is 8-bit, two’s complement with the
LSB equivalent to 1.0°C. Range and conversion between °C
and equivalent binary and hexadecimal data is exemplified in
Table 2.
8
FMS2701
PRODUCT SPECIFICATION
In Figure 2, VCC3AUX<2.93V represents the state of the
VCC3AUX power supply voltage.
Reset Generators
There are two reset generators:
1. Auxiliary Reset
2. Main Reset
AUXRST is a bi-directional pin. AUXRST(OUT) signifies
an outgoing signal. AUXRST(IN) signifies an incoming sig-
nal. Auxiliary Reset is triggered by either of two events:
Auxiliary Reset responds to the power supply voltage,
VCC3AUX applied to the FMS2701. Main Reset responds
to a separate power supply voltage level, VCC3. Threshold
level of both reset generators is 2.93 volt. If 1.0 V < VCC3AUX
< 2.93 both generators output an active L reset level.
1. VCC3AUX < 2.93 volt. After a VCC3AUX < 2.93
transition:
a) AUXRST(OUT) = L, continuing low for 140 msec.
after VCC3AUX > 2.93 volt.
b) INTRST = L, while AUXRST(OUT) = L.
Auxiliary Reset Generator
The Auxillary Reset Generator responds to either a low value
of VCC3AUX by outputting an AUXRST = L pulse and an
internal reset pulse, INTRST; or to an external AUXRST
input by emitting an internal reset. Internal reset restores
power-up register values (except DAC which is cleared by
7-0
RST) and initiates a Master Reset Cycle.
2. AUXRST(IN) = L. In response, INTRST = L,
continuing low until AUXRST(IN) = H
Internal reset, INTRST tracks AUXRST_OUT. To terminate a
reset cycle, VCC3AUX must rise above 2.93 volt. During
power-up, the AUXRST output remains low until the 2.93
volt threshold is reached.
140 mS
VCC3AUX<2.93V
AUXRST(IN)
tDAUXRST
tDVRST
AUXRST(OUT)
tDINTRST
INTRST
Figure 2. Timing Diagram, Auxiliary Reset
Main Reset
Depending upon the source of reset, the Main Reset
Generator outputs either a 140 or a 180 msec. pulse as shown
in Figure 3. VCC3 < 2.9 represents the state of the VCC3
power supply voltage. RST = L clears the D/A Converter
register.
tDMR
MR
tDVR
VCC3<2.9
INTRST
tDIR
140 mS
180 mS
180 mS
RST
Figure 3. Timing Diagram, Main Reset
9
PRODUCT SPECIFICATION
FMS2701
Internal Reset
Data Processor
Internal reset, INTRST originates from the Auxiliary Reset
Generator. When power is supplied to the FMS2701 via
VCC3AUX, output INTRST = L for 140 msec. after
VCC3AUX transitions >2.93 volt. INTRST = L instigates
four events:
Based upon setup commands via the SMBus, the Data Pro-
cessor gathers sensor inputs from the Temperature Processor
and Reset Generators. Temperature inputs are compared
against values stored in the Trip and Limit registers. Fault
conditions set flags in the interrupt registers and activate the
THERM and INT outputs. Temperature and interrupt status
are passed to the host via the SMBus interface. Host com-
mands set the FMS2701 configuration, interrupt masking
and the fan speed.
1. Configuration, Interrupt and Mask registers are reset to
default values.
2. THERM Temperature Trip Point registers: PTA
,
7-0
PTR , FTA , FTR are set to default values.
7-0 7-0 7-0
3. DAC register is set to 0x00.
7-0
4. Temperature Processor and Data Processor are reset.
Trip & Limit
Registers
DAC
7-0
D/A
Converter
Fan Speed
Register
FAN_SPD
THERM
RST
Ambient Error
Remote Error
Remote Fault
TR
TA
7-0
Temperature
Registers
Limit
Corporators
T
7-0
Interrupt
Status
7-0
Registers
Bypass/
Invert
Interrupt
Mask
GPI
Registers
NADD
Test Logic
NTEST_IN
Mask
Gating
Configuration
Registers
INT
INTEST_OUT
ADD/NTEST_OUT
FAN_OFF
ADD
Interface
Test
Registers
Pointer
Register
SCA
SCL
SMBus
Interface
Data Bus
Compare ID
and Version
Registers
MCLK
Master
Oscillator
Timing
and Control
Figure 4. Data Processor Block Diagram
10
FMS2701
PRODUCT SPECIFICATION
SMBus Interface
Two signals comprise the bus: clock (SCL) and bi-direc-
tional data (SDA). When receiving and transmitting data
through the serial interface, the FMS2701 acts as a slave,
responding only to commands by the SMBus master.
FMS2701 register access is via a 2-wire SMBus interface.
Base address is 0x2C + n, where n is an offset defined by the
state of the ADD pin: Z, H, L == 0, 1, 2. (see Table 3) State Z
corresponds to the ADD pin being open circuit.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
Table 3. Serial Port Slave Addresses
ADD
Address
2C
Z
H
L
2D
2E
SDA
SCL
tBUFF
tSTAH
tDHO
tDSU
tSTASU
tSTOSU
tDAL
tDAH
24469B
Figure 5. SMBus: Read/Write Timing
SDA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACK
SCL
24470B
Figure 6. SMBus: Typical Byte Transfer
SDA
SCL
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
Figure 7. SMBus: Slave Address with Read/Write Bit
11
PRODUCT SPECIFICATION
FMS2701
There are five steps within an SMBus cycle:
A repeated start signal occurs when the master device driv-
ing the serial interface generates a start signal without first
generating a stop signal to terminate the current communica-
tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
1. Start signal
2. Slave address byte
3. Pointer register address byte
4. Data byte to read or write
5. Stop signal
Serial Interface Read/Write Examples
When the SMBus interface is inactive (SCL = H and SDA = H)
communications are initiated by sending a start signal. The
start signal (Figure 5, left waveform) is a HIGH-to-LOW
transition on SDA while SCL is HIGH. This signal alerts all
slaved devices that a data transfer sequence is imminent.
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake ini-
tiates further SCL clock cycles from the master to transfer
the next data byte.
After a start signal, the first eight bits of data that are transferred,
comprise a seven bit slave address followed a single R/W bit
(Read = H, Write = L). As shown in Figure 6, the R/W bit
indicates the direction of data transfer: read from; or write to
the slave device. If the transmitted slave address matches the
address of the FMS2701 which set by the state of the ADD
pin, the FMS2701 acknowledges by pulling SDA LOW on
the 9th SCL pulse (see Figure 7) to send an acknowledge bit,
ACK. If the addresses do not match, the FMS2701 does not
acknowledge.
Write to one control register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Stop signal
Read from one control register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal
For each byte of data read or written, the MSB is the first bit
of the sequence.
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Stop signal
DATA TRANSFER
If a slave device such as the FMS2701 does not acknowledge
the master device during a write sequence, SDA remains HIGH
so that the master can generate a stop signal. During a read
sequence, if the master device does not acknowledge (ACK = L),
the FMS2701 interprets this as “end of data.” SDA remains
HIGH so the master can generate a stop signal.
Addressable Memory
Although the FMS2701 will respond to external inputs, con-
trol of the operation of the FMS2701 is through the internal
registers. Following power-up, registers are set to default
values. After a 140 msec. power up reset delay, the FMS2701
will begin checking sensor inputs to determine if the temper-
ature in voltages fall within default limits.
To write data to a specific FMS2701 control register, three
bytes are sent:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write to the control register indexed by the pointer.
These default values may be overridden by changing the val-
ues stored in the Value RAM. If the PTA and PTR val-
7-0 7-0
ues are changed, then the TRIP_LOCK (Temperature Trip
Point Lock) bit in the Configuration Register must be set to
enable temperature values to be compared against the pro-
grammable rather than the fixed trip point values. If the tem-
perature limit values are changed, then the changes are
effective immediately. Interrupt masking (register 0x43),
enabling (INT_EN bit) and clearing (INT_CLR bit) can be
used to disable interrupts during register setup.
Data is read from the control registers of the FMS2701 in a
similar manner, except that two data transfer operations are
required:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write the slave address byte with bit R/W = H
4. Read the control register indexed by the pointer.
Preceding each slave write, there must be a start cycle. Follow-
ing the pointer byte there should be a stop cycle. After the last
read, there must be a stop cycle comprising a LOW-to-HIGH
transition of SDA while SCL is HIGH. (see Figure 5, right
waveform)
There are four control registers and 21 Value RAM locations,
with functions and bit assignments defined in the Address-
able Memory section.
12
FMS2701
PRODUCT SPECIFICATION
D/A Converter
THERM Processing
An 8-bit D/A converter supplies a voltage to the FAN_SPD
pin which, can be used to control the speed of a fan. Input of
the D/A converter is connected to the DAC register.
7-0
THERM is a bi-directional pin with an open drain output.
When the THERM output is asserted L, the THERM input is
disabled. Figure 8 depicts the logical flow of the internal and
external THERM signals, showing the origins and destinations.
DAC value is loaded from the SMBus. In the event of a
7-0
THERM condition, the DAC output remains unchanged
7-0
but the D/A converter output is set full scale, equivalent to
DAC = 0xFF. RST = L clears DAC in the fan speed
7-0
7-0
register.
INTRSTb
Interrupt
Status
Register
Mirror
TEMPVALID
THERM
PTR
XTHERM
7-0
Programmable
Trip Point
PTA70-
Registers
FRY
7-0
ITHERM
THERM
HOT
7-0
FTR
FTA
7-0
7-0
Fixed Trip
Point
Interrupt
Status
Comparators
Other
Interrupts
Registers
Register
THERM
Interrupt
OR-gate
Mask
Interrupt
Mask
INT
ITHERM
Restore
MSKTHERM
Gating
Register
TRIPLOCK
TR[7:0]
TA[7:0]
Configuration
Register
FAN_OFF
DACFF==THERM
D/A
D/A
FAN_SPD
RST
Register
Converter
Figure 8. THERM I/O Structure/Detail
As an input, if THERM = L the following events occur:
3. If Configuration Register bit, TRIPLOCK = L and Fixed
Ambient Temperature Automatic Trip Point FTA is
7-0
exceeded.
1. If the mask bit, MSKTHERM = L, output pin, INT = L
2. Configuration Register bit, FAN_ON = H.
3. Output pin, FAN_SPD = 2.5 V for maximum fan speed
but register DAC is unchanged.
7-0
4. Interrupt Status Register bit, THERM = H.
4. If Configuration Register bit, TRIPLOCK = L and Fixed
Remote Temperature Automatic Trip Point
FTR is exceeded.
7-0
5. Interrupt Status Register Mirror bit, MTHERM = H.
TRIPLOCK is Temperature Trip Point Lock bit in the
Configuration Register.
As an output, ITHERM = H, causes THERM = L; ITHERM
= L, causes THERM = Z, open drain. ITHERM = H, if any
of the following conditions occur:
After a Trip Point has been exceeded, to restore the open
drain output, THERM = Z, the temperature must fall 5°C
below the trip point.
1. If Configuration Register bit, TRIPLOCK = H and
Programmable Ambient Temperature Automatic Trip
Point PTA is exceeded.
7-0
2. If Configuration Register bit, TRIPLOCK = H and
Programmable Remote Temperature Automatic Trip
Point PTR is exceeded.
7-0
13
PRODUCT SPECIFICATION
FMS2701
INT Processing
INT =L, if any bit in the Interrupt Register is active. Other-
wise INT = Z, open drain. Figure 9 depicts the logical flow
of the interrupt sources to the INT output.
INT is a hardware interrupt output. INT operation is con-
trolled by the Configuration Register bits: INT_EN and
INT_CLR bits, which enable and clear the open drain INT
output. Subject to the setting of the Interrupt Mask Register,
THERM
XTHERM
ITHERM
INT
Interrupt
Status
ATV, RTV
ITHERM
Register
Interrupt
Interrupt
OR-gate
Control
GPI, THERM,
RMT_FAULT
Interrupt
Status
Mask
Gating
Interrupt
Sources
Register
Interrupt
Mask
Interrupt
Status
Register
Register
Mirror
INT_EN
INT
INT_CLR
Configuration
Register
INT_RST
SOFT_RST
Figure 9. INT Output Structure
With Configuration Register bits INT_EN = 1 and INT_CLR
= 0, output pin INT = L, if any of the following bits are set in
the Interrupt Register:
5. RMT_FAULT: Remote diode is either open or short circuit.
Output pin INT = Z, clearing the interrupt output, if any of
the following events occur:
1. ATV: An ambient temperature limit is violated indicating
that the on-chip temperature falls outside the boundaries
1. Interrupt Status Register is read, causing this register to
be cleared to the default state.
established by TALO and TAHI
.
7-0 7-0
2. GPI: General Purpose Input, GPI is asserted. Polarity
of the GPI pin is determined by the setting of the
GPI_INVT bit in the Configuration Register.
3. RTV: A remote thermal diode temperature limit is vio-
lated, indicating that the temperature falls outside the
2. Configuration Register bit INT_CLR = 1, which is the
default condition following an internal reset.
3. Configuration Register bit INT_EN = 0, which is the
default condition following an internal reset.
boundaries established by TRLO and TRHI
4. THERM: Temperature exceeds an selected automatic
.
Status of the INT_CLR and INT_EN bits does not impact the
contents of the Interrupt Status or the Interrupt Status Mirror
Registers. Reading the Interrupt Status Registers clears only
that register. Reading the Interrupt Status Mirror Register,
clears only that register.
7-0 7-0
trip point (PTA , PTR , FTA , or FTR ) causing
7-0 7-0 7-0 7-0
output THERM = L or the THERM input = L even if the
THERM bit in the Interrupt Register is masked.
14
FMS2701
PRODUCT SPECIFICATION
Note that setting the INT output by exceeding a temperature
limit is an edge-driven event. Only when the temperature
actually crosses the limit boundary does INT\ transition LOW.
An example of interrupts caused by a series of temperature,
T transitions across temperature limits is shown in Figure 10.
Temperature limits are fixed for the first series of temperature
excursions. Then, for the second series, following the THI1
violation, the THI limit is raised from THI1 to THI2. If THI
is reprogrammed from a value above T to a value below THI,
then an interrupt is generated. INT is cleared by reading the
Interrupt Status Register (ISRread).
THI2
THI3
THI1
TLO1
TLO2
T
ISRread
INT
Figure 10. Profile of Temperature Driven Interrupts
ATV and RTV bits operate in conjunction with the INT
output and Interrupt status Register as follows:
that are stored in the Limit Registers. Out of range TA and
7-0
TR values set the INT bit in the Interrupt Status Register.
7-0
1. When the temperature exceeds a high limit, the corre-
sponding Interrupt Status Register bit, either ATV or
RTV is set.
TR and TA are also compared with the values in Trip
7-0 7-0
Point Registers, PTA and PTR if these registers have
7-0 7-0
been loaded or FTA and FTR , which contain power up
7-0 7-0
2. Reading the Interrupt Status Register clears ATV and RTV.
3. Once the high limit has been exceeded, a subsequent
transitions through the high level will not cause an
interrupt, unless:
default values. If a trip point is violated, two outputs are
asserted: THERM = L and FAN_SPD = H.
Mask Gating
a) The temperature passes through the low limit.
b) Or, the high temperature limit is changed.
4. If the high temperature limit is changed from a level
above the temperature to a level below, then the relevant
Interrupt Status Register bit, either ATV or RTV is set.
5. If the temperature falls below a low limit, the corre-
sponding Interrupt Status Register bit, either ATV or
RTV is set.
Setting the corresponding bit in the Interrupt Mask Register
can mask any bit in the Interrupt Status Register.
Timing and Control
Timing and Control logic generates a master clock and
orchestrates on-chip timing.
NAND Gate Test
6. Once the low limit has been exceeded, a subsequent
transitions through the low level will not cause an inter-
rupt, unless:
a) The temperature passes through the high limit.
b) Or, the low temperature limit is changed.
7. If the low temperature limit is changed from a level
below the ambient/remote temperature to a level above,
then the ATV/RTV bit is set.
A selectable NAND tree test is provided for Automated Test
Equipment (ATE) board level connectivity testing. NAND
tree test mode is enabled by setting the input pin, FAN_SPD
NTEST_IN = H, while the AUXRST output transitions L to H,
causing the output of a D flip-flop to:
1. Enable the NAND tree output, connecting it to the
ADD/NTEST_OUT pin.
2. Disable the D/A converter output to the FAN/SPD
NTEST_IN.
GPI—General Purpose Input
GPI is a General Purpose Input that can be used to trigger an
interrupt. Configuration Register bit GPI_INVT determines
the polarity of the GPI input. Interrupt Register bit, GPI = H
sets output INT = L if Mask Register bit MSK_GPI = L.
To perform a NAND tree test, NAND tree pins should be
driven high.
Each pin is toggled in turn to generate an output pattern with
values that can be verified against those shown in Table 4.
Limit and Trip Point Comparators
Temperature register outputs, TR and TA are compared
7-0 7-0
with the limit values TRHI , TRLO , TAHI and TALO
7-0 7-0 7-0 7-0
15
PRODUCT SPECIFICATION
FMS2701
NTEST_IN
NTEST_EN
INTRST
GPI
SCL
SDA
MR
NTEST_OUT
Figure 11. NAND Tree Test Logic
To implement the NAND-TREE test on a PWB, no pins
listed in the tree should be connected directly to power or
ground. Instead, pins should be biased through a low load
resistor with a value of 1.0 k to 100 k to allow ATE to drive
pins high/low.
Table 4. NAND Tree Truth Table
GPI
0
SCL
SDA
MR
0
ADD/NTESTOUT
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
16
FMS2701
PRODUCT SPECIFICATION
Equivalent Circuits
VCC3AUX
VDD
DIODE+
DIODE–
Digital
Input
GND
29233
GND
27014B
Figure 14. Equivalent Remote Diode Interface Circuit
Figure 12. Equivalent Digital Input Circuit
VDD
VDD
Digital
Output
p
n
Digital
Output
n
GND
29232
Figure 15. Equivalent Open Drain Output Circuit
GND
27011B
Figure 13. Equivalent Digital and D/A Output Circuit
17
PRODUCT SPECIFICATION
FMS2701
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
Power Supply Voltages
V
V
(Measured to GND)
(Measured to GND)
-0.5
3.3
3.3
5.75
V
V
CC3AUX
CC3AUX
Digital Inputs
3.3 V logic applied voltage (Measured to GND)2
Forced current3, 4
-0.3
-5.0
V
V
V
+ 0.3
+ 0.5
+ 0.5
V
CC3AUX
5.0
mA
Analog Inputs
Applied Voltage (Measured to GND)2
Forced current3, 4
-0.5
V
CC3AUX
10.0
-10.0
mA
Digital Outputs
3.3 V logic applied voltage (Measured to GND)2
Forced current3, 4
-0.5
V
DD3AUX
10.0
1
-10.0
mA
Short circuit duration (single output in HIGH state to ground)
Temperature
second
Operating, Ambient
-40
-65
125
150
300
220
150
±150
°C
°C
°C
°C
°C
V
Junction
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
Electrostatic Discharge5
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only
if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5. EIAJ test method.
Operating Conditions
Parameter
Min
Nom
Max
Units
V
V
Digital Power Supply Voltage
Ambient Temperature, Still Air
3.3
CC3AUX
TA
-40
125
°C
18
FMS2701
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Power Supply Currents
I
3.3 volt current
Operating
1
2
mA
mA
VCC3AUX
Standby
0.5
Digital Inputs/Outputs
C
C
Input Capacitance
5
10
+1
pF
pF
µA
µA
µA
V
I
Output Capacitance
Input Current, HIGH
Input Current, LOW
10
O
I
I
I
-1
0.005
0.005
200
IH
IL
Input Current, LOW, Master Reset
Input Voltage
MR = L
ILR
V
2.0
IH
IL
V
Input Voltage
0.8
100
-2
V
I
I
I
Output Current, HIGH, open drain
Output Current, HIGH
Output Current, LOW
Output Voltage, HIGH
Output Voltage, LOW
-0.1
µA
mA
mA
V
OZH
OH
OL
Other / FAN_OFF
3 / 6
V
OH
V
OL
I
I
= max.
= max.
2.4
2.1
OH
OL
0.4
V
SMBus I/O
V
V
V
Input Voltage, HIGH
Input Voltage, LOW
Output Voltage, LOW
Output Current, HIGH
Output Voltage, LOW
V
V
SMIH
SMIL
0.8
0.4
-100
4
I
= max.
V
SMOL
SMOH
SMOL
SMOL
I
I
-0.1
µA
mA
Diode Inputs
I
I
Source Current, High
Source Current, Low
80
8
100
10
120
12
µA
µA
DH
DL
Analog Output
V
V
Output Voltage, high
Output Voltage, low
Output Current , source
Output Current , sink
DAC
DAC
= 0xFF
2.5
0
V
V
AH
AL
7-0
= 0xOO
7-0
I
I
2
mA
mA
AH
AL
1
Switching Characteristics
Parameter
Conditions Min Typ1 Max Unit
Digital Inputs
t
t
t
Delay, GPI input to register
DGPI
Delay THERM input to register
Delay, NAND input to NTEST_OUT
THERM
NAND
Reset Generators
t
t
t
Delay, V
CC3AUX
< 2.93 V to AUXRST output
ns
DVA
Pulsewidth, AUXRST after V
> 2.93 V
< 2.93 V to RST\ output
140
500
ms
ns
WVA
DVAR
CC3AUX
Delay, V
CC3AUX
19
PRODUCT SPECIFICATION
FMS2701
Parameter
Conditions Min Typ1 Max Unit
t
t
t
t
t
t
Delay, input AUXRST ↓ to RST\ output
ns
DAR
WAR
DR
Pulsewidth, RST after V
> 2.93 V or AUXRST ↓
180
180
140
500
500
500
ms
ns
CC3AUX
Delay, MR ↓ to RST = L
Pulsewidth, MR ↑ to RST = H
Delay, V < 2.93 V to RST output
ms
ns
WR
DVR
DVW
CC3
Pulsewidth, RST after V
> 2.93 V
ms
CC3
SMBus Interface
t
t
t
t
t
t
t
t
SCL Pulse Width, LOW
SCL Pulse Width, HIGH
SDA Start Hold Time
4.7
4.0
4.0
4.0
4.7
4.7
250
300
µs
µs
µs
µs
µs
µs
ns
ns
DAL
DAH
STAH
STASU
STOSU
BUFF
DSU
SCL to SDA Setup Time (Stop)
SCL to SDA Setup Time (Start)
SDA Stop Hold Time Setup
SDA to SCL Data Setup Time
SDA to SCL Data Hold Time
DHO
Notes:
1. ↓ is a H to L transition.
2. ↑ is a L to H transition.
System Performance Characteristics
Parameter
Conditions
Min
Typ1
Max
Unit
Temperature Channel
Remote Accuracy
-40°C ≤ T ≤ +125°C
±5
±3
±5
±3
°C
°C
°C
°C
A
+60°C ≤ T ≤ +100°C
A
Ambient Accuracy
0°C ≤ T ≤ +85°C
A
20°C ≤ T ≤ +50°C
A
A/D Converter
E
E
Error, Total Unadjusted
Differential Linearity Error
Power Supply Sensitivity
Total Monitoring Cycle Time
±1
±1
±1
1.0
%
TUADC
LDADC
LSB
%/V
Sec.
PSS
t
Remote and Ambient samples
1.4
C
D/A Converter Output
E
E
V
Error, Total Unadjusted
Differential Linearity Error
Threshold Voltage
-3
-1
+3
+1
%
LSB
V
TUDAC
LDDAC
RES
2.93
Notes:
1. Values shown in Typ column are typical for V
= 3.3V and T = 25°C.
A
cc3AUX5
20
FMS2701
PRODUCT SPECIFICATION
Input pin MR and bi-directional pins AUXRST and THERM,
Application Information
should be biased to V
CC3AUX
through a pull-up resistor to
Since the FMS2701 is intended to be embedded on a Pen-
tium motherboard, external connections cannot be specifi-
cally defined. Although in Figure 16, only the schematic
symbol and power supply connections are shown, there are
several guidelines that should be adopted.
prevent spurious triggering.
If unused, GPI shold be connected to ground through a pull-
down resistor, unless the bit: GPI_INV = H, in which case GPI
should be connected to V
CC3AUX
through a pull-up resistor.
Power is supplied to the V
CC3AUX
pin which should be de-
The FAN_SPD/INTESTOUT pin should be biased to ground
through a pull-down resistor to ensure that the NAND Test is
not inadvertently enabled.
coupled to ground through a local 0.1 µF chip capacitor. To
minimize the effects of noise, locate the FMS2701 over a
ground plane.
SMBus pins SCL SDA require pull-up resistors along the bus
which are not necessarily local to the FMS2701. ADD must
be set H, L or open to match the FMS2701 address to the
assigned SMBus address.
Cleanly route the DIODE± analog traces as a pair over the
ground plane. Segregate DIODE± traces from digital traces
and areas of noise. Sensitivity to noise is approiximately
1°C/200µV.
V
must be maintained at 3.3 volts to avoid tripping the
CC3
Main Reset Generator. If V
is not used, connect it to
CC3
V
.
CC3AUX
VCC3AUX
JP1
C1
0.1
R1
10K 10K
R2
R3
10K
U1
R4
R5
10K
10K
2
6
1
FAN_OFFb
MRb
VCC3
MR
VCC3
FAN_OFF
3
7
AUXRSTb
RSTb
AUXRST
RST
9
10
CATHODE
ANODE
REMOTE_DIODE–
REMOTE_DIODE+
8
FAN_SDP
FAN_SPD
12
GPI
GPI
11
14
THERM
INT
THERMb
INTb
13
15
16
ADD
SCL
SDA
SCL
SDA
10K
JP2
FMS2701
Figure 16. FMS2701 Reference Schematic
21
PRODUCT SPECIFICATION
FMS2701
Pin Assignments
16-lead QSOP Package
Inches
Millimeters
Symbol
Notes
Min.
Max.
Min.
Max.
A
.061
.004
.008
.007
.189
.150
.068
.010
.012
.010
.196
.157
1.55
0.10
0.20
0.18
4.80
3.81
1.73
0.25
0.30
0.25
4.98
3.99
A1
B
C
D
E
e
.025 BSC
0.63 BSC
H
K
.230
–
.244
–
5.84
–
6.19
–
L
φ
.016
0°
.035
8°
0.41
0°
0.89
8°
16
9
C
L
E
H
1
8
φ
D
K
A
e
B
A1
22
FMS2701
PRODUCT SPECIFICATION
Notes
23
PRODUCT SPECIFICATION
FMS2701
Ordering Information
Product Number
Temperature Range
-40°C to 125°C
Screening
Package
Package Marking
FMS2701QSC
Commercial
16 Lead QSOP
2701QS
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
7/8/99 0.0m 003
Stock#DS30002701
1998 Fairchild Semiconductor Corporation
相关型号：
FMS2AT148
Small Signal Bipolar Transistor, 0.15A I(C), 50V V(BR)CEO, 2-Element, PNP, Silicon, SC-74A, 5 PIN
ROHM
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