FMS3110 [FAIRCHILD]
Triple Video D/A Converters 3 x 10 bit, 150 Ms/s; 三路视频D / A转换器3× 10位， 150 MS / s的
| 型号： | FMS3110 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Triple Video D/A Converters 3 x 10 bit, 150 Ms/s |
| 文件： | 总11页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FMS3110/3115
Triple Video D/A Converters
3 x 10 bit, 150 Ms/s
Features
Description
• 10-bit resolution
• 150 megapixels per second
• ± 0.1% linearity error
FMS3110/3115 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:
• Sync and blank controls
FMS3110
FMS3115
100 Ms/s
150 Ms/s
• 1.0V p-p video into 37.5Ω or 75Ω load
• Internal bandgap voltage reference
• Double-buffered data for low distortion
• TTL-compatible inputs
• Low glitch energy
• Single +5 Volt power supply
TTL-level inputs are converted to analog current outputs that
can drive 25–37.5Ω loads corresponding to doubly-terminated
50–75Ω loads. A sync current following SYNC input timing
is added to the I
output. BLANK will override RGB
OG
inputs, setting I , I and I currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
OG OB OR
Applications
• Video signal conversion
– RGB
the V
input.
REF
– YC C
B R
– Composite, Y, C
Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.
• Multimedia systems
• Image processing
• True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
Block Diagram
SYNC
SYNC
BLANK
10
10 bit D/A
IO
IO
IO
G
G
B
R
9-0
Converter
10
10 bit D/A
Converter
B
9-0
10
10 bit D/A
Converter
R
9-0
CLOCK
COMP
R
REF
REF
+1.235V
Ref
V
Rev. 1.05 12/21/00
FMS3110/3115
PRODUCT SPECIFICATION
D/A Outputs
Functional Description
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
Within the FMS3110/3115 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB are overridden by the BLANK input. SYNC
7-0
between R
and GND.
REF
= H activates, sync current from I for sync-on-green video
OS
signals.
Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes t
edge of CLK.
after the rising
DO
The FMS3110/3115 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.
R
should be doubled.
REF
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3KΩ source resistance. An external
voltage reference may be connected to the V
overriding the internal voltage reference.
pin,
REF
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
A 0.1µF capacitor must be connected between the COMP
pin and V to stabilize internal bias circuitry and ensure
low-noise operation.
DD
Power and Ground
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be connected
data: 660 mV max.
to V
pins with 0.1 and 0.01 µF decoupling capacitors
pin or pin pair.
DD
placed adjacent to each V
DD
pedestal: 54 mV
sync: 286 mV
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic
distortion or reduced signal-to-noise performance. All
ground pins should be connected to a common solid ground
plane for best performance.
Figure 1. Nominal Output Levels
2
REV. 1.05 12/21/00
PRODUCT SPECIFICATION
FMS3110/3115
Table 1. Output Voltage Versus Input Code, SYNC and BLANK
V
= 1.235 V, R = 590 Ω, R = 37.5 Ω
REF L
REF
Blue and Red D/As
Green D/A
RGB
9-0
(MSB…LSB)
SYNC
BLANK
V
OUT
SYNC
BLANK
V
OUT
11 1111 1111
11 1111 1111
11 1111 1110
11 1111 1101
X
X
X
X
1
1
1
1
0.7140
0.7140
0.7134
0.7127
1
0
1
1
1
1
1
1
1.0000
0.7140
0.9994
0.9987
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 0000 0000
01 1111 1111
X
X
1
1
0.3843
0.3837
1
1
1
1
0.6703
0.6697
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010
00 0000 0001
00 0000 0000
XX XXXX XXXX
XX XXXX XXXX
X
X
X
X
X
1
1
1
0
0
0.0553
0.0546
0.0540
0.0000
0.0000
1
1
1
1
0
1
1
1
0
0
0.3413
0.3406
0.3400
0.2860
0.0000
Pin Assignments
36
R
G
G
1
2
3
4
REF
1
2
35
34
33
32
31
30
29
28
V
REF
G
G
G
G
G
G
G
COMP
3
4
5
6
7
8
9
IO
R
IO
G
5
LQFP
FMS3110/3115
6
OV
DD
7
V
DD
8
IO
B
9
GND
GND
CLOCK
NC
BLANK
SYNC
10
11
12
27
26
V
25
DD
REV. 1.05 12/21/00
3
FMS3110/3115
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name
Clock and Pixel I/O
CLK 26
Pin Number
Value
Description
TTL
Clock Input. The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
R
47-37
48, 9–1
23–14
TTL
TTL
TTL
Red Pixel Data Inputs. TTL-compatible Red Data Inputs are
registered on the rising edge of CLK.
9-0
G
Green Pixel Data Inputs. TTL-compatible Green Data Inputs are
registered on the rising edge of CLK.
9-0
9-0
B
Blue Pixel Data Inputs. TTL-compatible Blue Data Inputs are
registered on the rising edge of CLK.
Controls
SYNC
11
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on the Green D/A converter
output. SYNC is registered on the rising edge of CLK with the same
pipeline latency as BLANK and pixel data. SYNC does not override
any other data and should be used only during the blanking interval.
Since this is a single-supply D/A and all signals are positive-going,
sync is added to the bottom of the Green D/A range. So turning SYNC
OFF means turning the current source ON. When a sync pulse is
desired, the current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC should be
connected to GND.
BLANK
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored and
the D/A converter outputs fall to the blanking level. BLANK is
registered on the rising edge of CLK and has the same pipeline
latency as SYNC.
Video Outputs
IO
33
32
0.714 V
Red Current Output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
R
p-p
IO
1 V
p-p
Green Current Output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines. Sync pulses may be
added to the Green D/A output.
G
IO
29
0.714 V
Blue Current Output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
B
p-p
4
REV. 1.05 12/21/00
PRODUCT SPECIFICATION
FMS3110/3115
Pin Descriptions (continued)
Pin Name
Pin Number
Value
Description
Voltage Reference
V
35
36
+1.235 V Voltage Reference Output/Input. An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt reference
may be applied here which overrides the internal reference.
REF
Decoupling V
to GND with a 0.1µF ceramic capacitor is required.
REF
R
560 Ω
Current-Setting Resistor. Full-scale output current of each D/A
REF
converter is determined by the value of the resistor connected
between R
and GND. Nominal value of R is found from:
REF
REF
R
REF
= 9.1 (V )
/I
REF FS
where I is the full-scale (white) output current (in amps) from the
FS
D/A converter (without sync). Sync is 0.4 * I
.
FS
D/A full-scale (white) current may also be calculated from:
I
= V /R
FS
FS
L
Where V is the white voltage level and R is the total resistive load
FS
L
(in ohms) on each D/A converter. V is the blank to full-scale
FS
voltage.
COMP
34
0.1 µF
Compensation Capacitor. A 0.1 µF ceramic capacitor must be
connected between COMP and V
to stabilize internal bias circuitry.
DD
Power and Ground
V
12, 30, 31
27, 28
+5 V
0.0V
Power Supply.
Ground.
DD
GND
Equivalent Circuits
V
V
DD
DD
p
Digital
Input
n
p
V
DD
n
OUT
GND
GND
Figure 3. Equivalent Analog Output Circuit
Figure 2. Equivalent Digital Input Circuit
REV. 1.05 12/21/00
5
FMS3110/3115
PRODUCT SPECIFICATION
Equivalent Circuits (continued)
V
DD
p
p
R
REF
V
REF
GND
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Typ
Max
Unit
Power Supply Voltage
V
DD
(Measured to GND)
-0.5
7.0
V
Inputs
Applied Voltage (measured to GND)2
Forced Current3,4
-0.5
V
V
+ 0.5
V
DD
-10.0
10.0
mA
Outputs
Applied Voltage (measured to GND)2
-0.5
+ 0.5
V
DD
Forced Current3,4
-60.0
60.0
mA
Short Circuit Duration (single output in HIGH state to ground)
Infinite
second
Temperature
Operating, Ambient
Junction
-20
110
150
300
220
150
°C
°C
°C
°C
°C
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
-65
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
REV. 1.05 12/21/00
PRODUCT SPECIFICATION
FMS3110/3115
Operating Conditions
Parameter
Min
Nom
Max
5.25
100
150
Units
V
V
Power Supply Voltage
Conversion Rate
4.75
5.0
DD
f
t
t
t
FMS3110
FMS3115
FMS3110
FMS3115
FMS3110
FMS3115
FMS3110
FMS3115
Msps
Msps
ns
S
CLK Pulsewidth, HIGH
CLK Pulsewidth, LOW
CLK Pulsewidth
3.1
2.5
3.1
2.5
10
6.6
1.7
0
PWH
PWL
W
ns
ns
ns
ns
ns
t
t
t
t
Input Data Setup Time
Input Date Hold Time
ns
S
ns
h
CLK Pulsewidth, HIGH
CLK Pulsewidth, LOW
Reference Voltage, External
Compensation Capacitor
Output Load
2
ns
PWH
PWL
2
ns
V
1.0
1.235
0.1
1.5
V
REF
C
R
µF
Ω
C
37.5
L
V
V
Input Voltage, Logic HIGH
Input Voltage, Logic LOW
Ambient Temperature, Still Air
2.0
GND
0
V
V
IH
IL
A
DD
0.8
70
V
T
°C
Electrical Characteristics
Parameter
Conditions3
Min
Typ1
Max
Units
Power Supply Current2
I
V
V
= Max
= Max
125
655
mA
DD
DD
DD
Total Power Dissipation2
Output Resistance
PD
mW
R
C
100
kΩ
pF
µA
µA
µA
V
O
Output Capacitance
Input Current, HIGH
Input Current, LOW
I
= 0mA
30
-5
O
OUT
I
I
I
V
V
= Max, V = 2.4V
IN
IH
DD
= Max, V = 0.4V
IN
5
IL
DD
V
Input Bias Current
REF
0
1.235
0
±100
REF
V
V
Reference Voltage Output
Output Compliance
REF
OC
Referred to V
DD
-0.4
+1.5
10
V
C
Digital Input Capacitance
4
pF
DI
Notes:
1. Values shown in Typ column are typical for V
= +5V and T = 25°C.
DD
A
2. Minimum/Maximum values with V
DD
= Max and T = Min.
A
3. V
= 1.235V, R
LOAD
= 37.5Ω, R = 540Ω
REF
REF
REV. 1.05 12/21/00
7
FMS3110/3115
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions2
= Min
Min
Typ1
10
Max
15
2
Units
ns
t
t
t
t
Clock to Output Delay
Output Skew
V
DD
D
1
ns
SKEW
Output Risetime
Output Falltime
10% to 90% of Full Scale
90% to 10% of Full Scale
3
ns
R
F
3
ns
Notes:
1. Values shown in Typ column are typical for V
= +5V and T = 25°C.
A
DD
2. V
= 1.235V, R
LOAD
= 37.5Ω, R
REF
= 590Ω.
REF
System Performance Characteristics
Parameter
Conditions2
Min
Typ1
Max
Units
%/FS
%/FS
%
E
E
E
Integral Linearity Error
V
V
V
, V
= Nom
= Nom
= Nom
±0.1
±0.1
3
±0.25
±0.25
10
LI
DD REF
Differential Linearity Error
DAC to DAC Matching
, V
DD REF
LD
DM
, V
DD REF
PSR
Power Supply Rejection Ratio
0.05
%/%
Notes:
1. Values shown in Typ column are typical for V
DD
= +5V and T = 25°C.
A
2. V
= 1.235V, R
LOAD
= 37.5Ω, R
= 590Ω.
REF
REF
Timing Diagram
1/fS
tPWL
tPWH
CLK
tH
tS
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
10%
tD
tSET
tF
tR
OUTPUT
50%
8
REV. 1.05 12/21/00
PRODUCT SPECIFICATION
FMS3110/3115
2. Power plane for the FMS3110/3115 should be separate
from that which supplies the digital circuitry. A single
Applications Discussion
Figure 5 illustrates a typical FMS3110/3115 interface cir-
cuit. In this example, an optional 1.2 Volt bandgap reference
is
power plane should be used for all of the V
pins. If
DD
the power supply for the FMS3110/3115 is the same as
that of the system's
digital circuitry, power to the FMS3110/3115 should be
decoupled with 0.1µF and 0.01µF capacitors and iso-
lated with a ferrite bead.
connected to the V
output, overriding the internal volt-
REF
age reference source.
Grounding
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
It is important that the FMS3110/3115 power supply is well-
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video sig-
nals at the output of the circuit. The FMS3110/3115 has sep-
arate analog and digital circuits. To keep digital system noise
from the D/A converter, it is recommended that power supply
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3110/3115,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer to
the FMS3110/3115 and its related analog circuitry can
have an adverse effect on performance.
voltages (V ) come from the system analog power source
DD
and all ground connections (GND) be made to the analog
ground plane. Power supply pins should be individually
decoupled at the pin.
5. CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following sug-
gestions when doing the layout:
Related Products
• FMS38XX Triple 8-bit 150 Msps D/A Converters
• FMS9884A 3 x 8-bit 140 Ms/s A/D Converter
1. Keep the critical analog traces (V , COMP,
, I
IO , IO , IO ) as short as possible and as far as possi-
REF REF
S
R
G
ble from all digital signals. The FMS3110/3115 should
be located near the board edge, close to the analog out-
put connectors.
+5V
10µF
0.1µF
Red
VDD
GND
ZO=75Ω
75Ω
75Ω
75Ω
IOR
IOG
IOB
RED PIXEL
INPUT
Green w/Sync
R9-0
G9-0
B9-0
75Ω
75Ω
75Ω
ZO=75Ω
Blue
ZO=75Ω
GREEN PIXEL
INPUT
FMS31XX
Triple 10-bit
BLUE PIXEL
INPUT
D/A Converter
+5V
COMP
CLOCK
SYNC
BLANK
CLK
SYNC
BLANK
0.1µF
560Ω
3.3kΩ (not required without
external reference)
VREF
RREF
0.1µF
LM185-1.2
(Optional)
Figure 5. Typical Interface Circuit
REV. 1.05 12/21/00
9
FMS3110/3115
PRODUCT SPECIFICATION
Mechanical Dimensions
48-Lead LQFP Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
A
.055
.001
.053
.006
.346
.268
.063
.005
1.40
.05
1.60
.15
A1
A2
B
1.35
.17
8.8
.057
.010
.362
.284
1.45
.27
9.2
7.2
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
D/E
D1/E1
e
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
6.8
.019 BSC
.50 BSC
7. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
L
.017
.029
.45
.75
6
4
5
N
48
12
48
12
ND
α
ccc
0°
7°
0°
7°
.004
0.08
8.
To be determined at seating place —C—
D
D1
e
PIN 1
IDENTIFIER
E
E1
C
α
L
0.063" Ref (1.60mm)
See Lead Detail
Base Plane
A2
A
B
-C-
Seating Plane
LEAD COPLANARITY
ccc
A1
C
10
REV. 1.05 12/21/00
FMS3110/3115
PRODUCT SPECIFICATION
Ordering Information
Conversion
Package
Product Number
FMS3110KRC
FMS3115KRC
Rate
Temperature Range
T = 0°C to 70°C
Screening
Commercial
Commercial
Package
Marking
3110KRC
3115KRC
100 Ms/s
150 Ms/s
48-Lead LQFP
48-Lead LQFP
A
T = 0°C to 70°C
A
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
12/21/00 0.0m 003
Stock#DS30003110
2000 Fairchild Semiconductor Corporation
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