SI5311-BM [ETC]
PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC; 精密高速时钟乘法器/再生器IC
| 型号： | SI5311-BM |
| 厂家： | 
ETC |
| 描述： | PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC |
| 文件： | 总24页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5311
PRELIMINARY DATA SHEET
PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC
Features
Complete precision high speed clock multiplier and regenerator device:
! Performs Clock Multiplication to
One of Four Frequency Ranges:
150–167 MHz, 600–668 MHz,
1.2–1.33 GHz, or 2.4–2.67 GHz
! Regenerates a “Clean”, Jitter-
Attenuated Version of Input
Clock
! DSPLL™ Technology Provides
! Jitter Generation as low as
Superior Jitter Performance
! Small Footprint: 4 mm x 4 mm
! Low Power: 310 mW typical
0.5 psRMS for 622 MHz Output
! Accepts Input Clock from
9.4–668 MHz
Ordering Information:
See page 22.
Applications
Pin Assignments
Si5311
! SONET/SDH Systems
! Terabit Routers
! Digital Cross Connects
! Optical Transceiver Modules
! Gigabit Ethernet Systems
! Hybrid VCO Modules
Description
20 19 18 17
16
REXT
VDD
PWRDN/CAL
VDD
1
2
3
4
5
15
14
The Si5311 is a fully integrated high-speed clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. When the clock multiplier is operating in
either the 150–167 MHz range or the 600–668 MHz range, the clock
regenerator operates simultaneously. The clock regenerator creates a
“clean” version of the input clock by using the clock synthesis phase-
locked loop (PLL) to remove unwanted jitter and square up the input
clock’s rising and falling edges. The Si5311 uses Silicon Laboratories
patented DSPLL™ architecture to achieve superior jitter performance while
eliminating the analog loop filter found in traditional PLL designs.
GND
GND
13 CLKOUT+
Pad
12
11
REFCLK+
REFCLK–
CLKOUT–
VDD
6
7
8
9
10
Top View
The Si5311 represents a new standard in low jitter, small size, low power,
and ease-of-use for high speed clock devices. It operates from a single
2.5 V supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
2
CLKO UT+
Regeneration
BUF
BUF
CLKO UT–
Calibration
PW RDN/CAL
DSPLLTM
Phase-Locked
Loop
2
CLKIN+
CLKIN–
2
M ULTO UT+
M ULTO UT–
BUF
LO L
Bias Gen
2
2
REXT
REFCLK+
REFCLK–
M ULTSEL1–0
Preliminary Rev. 0.6 6/01
Copyright © 2001 by Silicon Laboratories
Si5311-DS06
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5311
2
Preliminary Rev. 0.6
Si5311
TABLE OF CONTENTS
Section
Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Descriptions: Si5311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Preliminary Rev. 0.6
3
Si5311
Detailed Block Diagram
CLKOUT+
CLKOUT–
Regen
c
CLKIN+
MULTOUT+
MULTOUT–
Phase
Detector
CLK
A/D
VCO
DSP
c
Divider
CLKIN–
n
REFCLK+
REFCLK–
Lock
Detector
LOL
2
/
MULTSEL 1- 0
REXT
PWRDN/CAL
Calibration
Bias
Generation
Figure 1. Detailed Block Diagram
4
Preliminary Rev. 0.6
Si5311
Electrical Specifications
Table 1. Recommended Operating Conditions
Min1
–40
Max1
85
Parameter
Symbol
Test Condition
Typ
Unit
Ambient Temperature
Si5311 Supply Voltage2
Notes:
TA
25
°C
V
VDD
2.375
2.5
2.625
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
2. The Si5311 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 13.
V
SIGNAL +
Differential
I/Os
VIS
VICM, VOCM
SIGNAL –
(SIGNAL +) – (SIGNAL –)
Differential Peak-to-Peak Voltage
t
VID,VOD
Differential
Voltage Swing
Figure 2. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT)
CLKIN
1/fMULT
MULTOUT
tCI-M
tM-CO
CLKOUT
Figure 3. CLKIN to CLKOUT, MULTOUT Phase Relationship
CLKIN,
80%
20%
REFCLK,
CLKOUT,
MULTOUT
tF
tR
Figure 4. Clock Input and Output Rise/Fall Times
Preliminary Rev. 0.6
5
Si5311
Table 2. DC Characteristics, V = 2.5 V
DD
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Supply Current
IDD
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
—
—
—
—
108
113
117
124
118
123
127
134
mA
Power Dissipation
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
PD
—
—
—
—
270
283
293
310
310
323
333
352
mW
"
Common Mode Input Voltage
VICM
VIS
See Figure 2
See Figure 2
See Figure 2
Line-to-Line
—
.80 VDD
—
V
(CLKIN, REFCLK)
Input Voltage Range*
—
—
—
750
1500
mV
(CLKIN+, CLKIN–, REFCLK+, REFCLK–)
Differential Input Voltage Swing*
VID
200
mV
(CLKIN, REFCLK)
(pk-pk)
Input Impedance (CLKIN, REFCLK)
Differential Output Voltage Swing
(CLKOUT)
RIN
VOD
84
TBD
100
940
116
TBD
Ω
100 Ω Load
Line-to-Line
mV
(pk-pk)
Differential Output Voltage Swing
(MULTOUT)
Output Common Mode Voltage
(CLKOUT, MULTOUT)
VOD
100 Ω Load
TBD
—
900
TBD
—
mV
(pk-pk)
Line-to-Line
VOCM
100 Ω Load
Line-to-Line
VDD – 0.7
V
Output Impedance (CLKOUT, MULTOUT)
Output Short to GND (CLKOUT, MULTOUT)
Output Short to VDD (CLKOUT, MULTOUT)
Input Voltage Low (LVTTL Inputs)
ROUT
ISC(–)
ISC(+)
VIL
Single-ended
84
—
TBD
—
100
25
–15
—
116
TBD
—
Ω
mA
mA
V
.8
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
Input Impedance (LVTTL Inputs)
VIH
IIL
IIH
VOL
VOH
RIN
2.0
—
—
—
—
V
25
25
—
—
—
TBD
TBD
0.4
—
—
TBD
µA
µA
V
V
kΩ
µA
IO = 2 mA
IO = 2 mA
—
2.0
100
TBD
PWRDN/CAL Internal Pulldown Current
IPWRDN
V
PWRDN ≥ 0.8 V
25
*Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the
positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this
range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN–, REFCLK+, or REFCLK–) must not
exceed the specified maximum Input Voltage Range (VIS max).
6
Preliminary Rev. 0.6
Si5311
Table 3. AC Characteristics
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
9.375
TBD
9.375
40
Typ
—
—
—
50
—
Max
Unit
MHz
%
MHz
%
CLKIN Frequency Range*
CLKIN Duty Cycle
REFCLK Range*
REFCLK Duty Cycle
668
TBD
167
60
CDUTY
CTOL
REFCLK Frequency
Tolerance
–100
100
ppm
MULTOUT Clock Rate
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
fMULT
2400
1200
600
—
—
—
—
2672
1336
668
MHz
150
167
Output Rise Time
tR
tF
Figure 4
Figure 4
Figure 4
Figure 4
Figure 3
—
—
—
—
100
100
—
TBD
TBD
TBD
TBD
ps
ps
ps
ps
(CLKOUT, MULTOUT)
Output Fall Time
(CLKOUT, MULTOUT)
Input Rise Time
tR
(CLKIN, REFCLK)
Input Fall Time
tF
—
(CLKIN, REFCLK)
CLKIN to MULTOUT Delay
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
tCI-M
TBD
TBD
TBD
TBD
0
TBD
TBD
TBD
TBD
ps
ps
ps
ns
120
150
3.4
MULTOUT to CLKOUT Delay
MULTSEL[1:0] = 00
MULTSEL[1:0] = 01
MULTSEL[1:0] = 10
MULTSEL[1:0] = 11
tM-CO
Figure 3
—
—
TBD
TBD
—
—
—
—
TBD
TBD
1/fMULT + 160
960
ps
ps
Input Return Loss
100 kHz–2.5 GHz
2.5 GHz–4.0 GHz
18.7
TBD
—
—
—
—
dB
*Note: See Table 11.
Preliminary Rev. 0.6
7
Si5311
Table 4. AC Characteristics (PLL Performance Characteristics)
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
JTOL(PP)
See Table 5
See Table 6
See Table 7
See Table 8
(MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)
Jitter Tolerance
JTOL(PP)
JTOL(PP)
JTOL(PP)
(MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)
Jitter Tolerance
(MULTSEL[1:0] = 10,
MULTOUT = 600 to 668 MHz)
Jitter Tolerance
(MULTSEL[1:0] = 11,
MULTOUT = 150 to 167 MHz)
Jitter Generation (MULTOUT)
JGEN(rms) Clock Input (MHz) =
600.000 to 668.000
—
TBD
TBD
psRMS
(MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)*
Jitter Generation (MULTOUT)
JGEN(rms Clock Input (MHz) =
300.000 to 334.000
—
—
—
—
—
—
—
—
—
—
—
—
—
TBD
TBD
1.9
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
kHz
(MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)*
Clock Input (MHz) =
600.000 to 668.000
Jitter Generation (MULTOUT, CLKOUT) JGEN(rms) Clock Input (MHz) =
(MULTSEL[1:0] = 10,
37.500 to 41.750
MULTOUT = 600 to 668 MHz)*
Clock Input (MHz) =
1.2
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
0.9
Clock Input (MHz) =
0.5
300.000 to 334.000
Clock Input (MHz) =
600.000 to 668.000
0.5
Jitter Generation (MULTOUT, CLKOUT) JGEN(rms) Clock Input (MHz) =
5.8
(MULTSEL[1:0] = 11,
9.375 to 10.438
MULTOUT = 150 to 167 MHz)*
Clock Input (MHz) =
3.2
18.750 to 20.875
Clock Input (MHz) =
37.500 to 41.750
2.2
Clock Input (MHz) =
1.4
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
1.3
Jitter Transfer Bandwidth
(MULTSEL[1:0] = 00,
JBW
Clock Input (MHz) =
1360
600.000 to 668.000
MULTOUT = 2400 to 2672 MHz)*
*Note: See PLL Performance section of this document for test descriptions.
8
Preliminary Rev. 0.6
Si5311
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Transfer Bandwidth
JBW
Clock Input (MHz) =
—
680
TBD
kHz
300.000 to 334.000
(MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)*
Clock Input (MHz) =
600.000 to 668.000
—
—
—
—
—
—
—
—
—
—
—
—
1360
85
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
Jitter Transfer Bandwidth
(MULTSEL[1:0] = 10,
JBW
Clock Input (MHz) =
37.500 to 41.750
MULTOUT = 600 to 668 MHz)*
Clock Input (MHz) =
75.000 to 83.500
170
340
680
1360
21
Clock Input (MHz) =
150.000 to 167.000
Clock Input (MHz) =
300.000 to 334.000
Clock Input (MHz) =
600.000 to 668.000
Jitter Transfer Bandwidth
(MULTSEL[1:0] = 11,
JBW
Clock Input (MHz) =
9.375 to 10.438
MULTOUT = 150 to 167 MHz)*
Clock Input (MHz) =
43
18.750 to 20.875
Clock Input (MHz) =
37.500 to 41.750
85
Clock Input (MHz) =
170
340
0.03
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
Jitter Transfer Peaking
JP
JP
Clock Input (MHz) =
600.000 to 668.000
(MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)*
Jitter Transfer Peaking
Clock Input (MHz) =
300.000 to 334.000
—
—
—
—
—
—
—
0.03
0.02
0.12
0.06
0.03
0.02
0.01
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dB
dB
dB
dB
dB
dB
dB
(MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)*
Clock Input (MHz) =
600.000 to 668.000
Jitter Transfer Peaking
(MULTSEL[1:0] = 10,
JP
Clock Input (MHz) =
37.500 to 41.750
MULTOUT = 600 to 668 MHz)*
Clock Input (MHz) =
75.000 to 83.500
Clock Input (MHz) =
150.000 to 167.000
Clock Input (MHz) =
300.000 to 334.000
Clock Input (MHz) =
600.000 to 668.000
*Note: See PLL Performance section of this document for test descriptions.
Preliminary Rev. 0.6
9
Si5311
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Transfer Peaking
JP
Clock Input (MHz) =
—
0.12
TBD
dB
9.375 to 10.438
(MULTSEL[1:0] = 11,
MULTOUT = 150 to 167 MHz)*
Clock Input (MHz) =
18.750 to 20.875
—
—
0.06
0.03
0.02
0.01
1.5
TBD
TBD
TBD
TBD
1.7
dB
dB
Clock Input (MHz) =
37.500 to 41.750
Clock Input (MHz) =
75.000 to 83.500
—
dB
Clock Input (MHz) =
—
dB
150.000 to 167.000
Acquisition Time
TAQ
After falling edge of
PWRDN/CAL
1.45
40
ms
µs
From the return of valid
60
150
CLKIN
Frequency Difference at which PLL goes
out of Lock (REFCLK compared to the
divided down VCO clock)
LOL
TBD
600
TBD
ppm
Frequency Difference at which PLL goes
into Lock (REFCLK compared to the
divided down VCO clock)
LOCK
TBD
300
TBD
ppm
*Note: See PLL Performance section of this document for test descriptions.
10
Preliminary Rev. 0.6
Si5311
Table 5. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 00,
MULTOUT = 2400 to 2672 MHz)
Frequency (Hz)
600-668 MHz
Clock Input
< TBD
TBD
TBD
TBD
TBD
TBD
TBD
> TBD
*Note: Measured using sinusoidal jitter at stated
Test Condition frequency.
Table 6. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 01,
MULTOUT = 1200 to 1336 MHz)
Frequency (Hz)
300-334 MHz
Clock Input
600-668 MHz
Clock Input
< TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
> TBD
*Note: Measured using sinusoidal jitter at stated Test
Condition frequency.
Table 7. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 10,
MULTOUT = 600 to 668 MHz)
Frequency
(Hz)
37.5–
75–83.5 MHz 150-167 MHz 300–334 MHz 600-668 MHz
41.75 MHz
Clock Input
Clock Input
Clock Input
Clock Input
Clock Input
< 300
25K
25.0
2.33
0.67
0.50
25.0
4.67
0.83
0.58
25.0
9.33
1.17
0.67
25.0
16.7
2.17
0.67
TBD
TBD
TBD
TBD
250K
> 1M
*Note: Measured using sinusoidal jitter at stated Test Condition frequency.
Preliminary Rev. 0.6
11
Si5311
Table 8. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 11,
MULTOUT = 150 to 167 MHz)
Frequency (Hz)
9.375–
18.75–
37.5–41.75 MHz
Clock Input
75–83.5 MHz
Clock Input
150-167 MHz
Clock Input
10.438 MHz
Clock Input
20.875 MHz
Clock Input
< 300
6.5K
65K
TBD
TBD
TBD
TBD
TBD
66.7
18.0
3.33
2.67
2.00
66.7
36.7
4.67
2.67
2.33
100
66.7
8.00
3.33
2.67
TBD
TBD
TBD
TBD
TBD
325K
> 1M
*Note: Measured using sinusoidal jitter at stated Test Condition frequency.
Table 9. Absolute Maximum Ratings
Parameter
Symbol
VDD
Value
Unit
V
DC Supply Voltage
–0.5 to 2.8
–0.3 to 3.6
–0.3 to (VDD+ 0.3)
±50
LVTTL Input Voltage
VDIG
V
Differential Input Voltages
Maximum Current any output PIN
Operating Junction Temperature
Storage Temperature Range
Lead Temperature (soldering 10 seconds)
VDIF
V
mA
°C
°C
°C
TJCT
TSTG
–55 to 150
–55 to 150
300
ESD HBM Tolerance (100 pf, 1.5 kΩ)
CLKIN+, CLKIN–, REFCLK+, REFCLK–,
All other pins
—
—
1
1.5
kV
kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 10. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
ϕJA
Still Air
38
°C/W
12
Preliminary Rev. 0.6
Si5311
LVTTL
Loss-of-Lock
Indicator
Control Inputs
2
CLKIN+
CLKOUT+
CLKOUT–
Regenerated
Clock
Clock Input
CLKIN–
Si5311
System
Reference
Clock
REFCLK+
REFCLK–
MULTOUT+
MULTOUT–
Multiplied
Clock
0.1 µF
10 k
Ω
(1%)
VDD
2200 pF
20 pF
Figure 5. Si5311 Typical Application Circuit
Preliminary Rev. 0.6
13
Si5311
Functional Description
The Si5311 is an integrated high speed clock multiplier output is not characterized for the MULTOUT ranges of
and clock regenerator device based on Silicon 1.2–1.33 GHz or 2.4–2.67 GHz.
Laboratories DSPLL™ technology. The DSPLL phase
locks to the clock input signal (CLKIN) and generates a
phase-locked output clock (MULTOUT) at a multiple of
the input clock frequency. The MULTOUT output is
configured to operate in the 150–167 MHz, the 600–
668 MHz, the 1.2–1.33 GHz, or the 2.4–2.67 GHz
frequency range using the MULTSEL0 and MULTSEL1
control inputs.
A reference clock input signal (REFCLK) is used by the
DSPLL as a reference for determination of the PLL lock
status. For convenience, REFCLK can be provided at
any one of five frequencies, each a multiple of the
CLKIN frequency. The REFCLK rate is automatically
detected, so no control inputs are needed for
configuration. The REFCLK input can be synchronous
or asynchronous with respect to the CLKIN input. The
When the device is configured for a MULTOUT output operating ranges for the CLKIN, CLKOUT, MULTOUT,
frequency range of 150–167 MHz or 600–668 MHz, the and REFCLK signals are indicated in Table 11. Values
DSPLL is also employed to regenerate an output clock for typical applications are given in Table 12.
(CLKOUT) that is a jitter-attenuated version of the input
clock with clean rising and falling edges. The CLKOUT
Table 11. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
REFCLK = 2n x CLKIN
±100 ppm
MULTSEL [1:0]
CLKIN
Range (MHz)
CLKOUT
MULTOUT
(see Note 2)
00
600.00–668.00
n = –6, –5, –4, –3, or –2 See Note 1(a)
4xCLKIN
(MULTOUT = 2.4–2.7 GHz)
01
300.00–334.00
600.00–668.00
37.500–41.750
75.000–83.500
150.000–167.000
n = –5, –4, –3, –2, or –1 See Note 1(a)
n = –6, –5, –4, –3, or –2 See Note 1(a)
4xCLKIN
2xCLKIN
16xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN
16xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN
(MULTOUT = 1.2–1.33 GHz)
n = –2, –1, 0, 1, or 2
n = –3, –2, –1, 0, or 1
n = –4, –3, –2, –1, or 0
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
10
(MULTOUT = 600–668 MHz)
300.000–334.000 n = –5, –4, –3, –2, or –1
600.000–668.000 n = –6, –5, –4, –3, or –2 See Note 1(b)
9.375–10.438
18.750–20.875
37.500–41.750
75.000–83.500
150.000–167.000
n = 0, 1, 2, 3, or 4
n = –1, 0, 1, 2, or 3
n = –2, –1, 0, 1, or 2
n = –3, –2, –1, 0, or 1
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
11
(MULTOUT = 150–167 MHz)
n = –4, –3, –2, –1, or 0 See Note 1(b)
Note:
1. The CLKOUT output is not valid for (a) MULTSEL[1:0] = 00 or MULTOUT[1:0] = 01
(b) MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple.
14
Preliminary Rev. 0.6
Si5311
Table 12. Clock Values for Typical Applications
CLKIN (MHz)
REFCLK Input (MHz) MULTSEL
CLKOUT
MULTOUT output
(MHz)
[1:0]
(MHz)
9.72
19.44
38.88
38.88
77.76
77.76
155.52
—
SONET/SDH
9.72
19.44
38.88
9.72
19.44
38.88
11
11
10
11
10
11
10
11
01
10
00
01
10
11
11
10
11
10
11
10
11
01
10
00
01
10
11
11
10
11
10
11
10
11
01
10
00
01
10
155.52
155.52
622.08
155.52
622.08
155.52
622.08
155.52
1244.16
622.08
2488.32
1244.16
622.08
156.25
156.25
625
77.76
155.52
311.04
622.08
77.76
155.52
9.72, 19.44, 38.88,
77.76, or 155.52
—
311.04
—
—
—
9.77
19.53
39.06
39.06
78.125
78.125
156.25
—
—
312.5
—
—
—
10.41
20.83
41.66
41.66
83.31
83.31
166.63
—
9.72, 19.44, 38.88,
77.76, or 155.52
9.77
19.53
39.06
9.77
19.53
39.06
Gigabit Ethernet
156.25
625
156.25
625
78.125
156.25
312.5
625
78.125
156.25
156.25
1250
9.77, 19.53, 39.06,
78.125, or 156.25
625
9.77, 19.53, 39.06,
2500
78.125, or 156.25
1250
625
SONET/SDH FEC
(15/14)
10.41
20.83
41.66
10.41
20.83
41.66
166.63
166.63
666.51
166.63
666.51
166.63
666.51
166.63
1333.03
666.51
2666.06
1333.03
666.51
83.31
166.63
333.26
666.51
83.31
166.63
10.41, 20.83, 41.66,
83.31, or 166.63
—
333.26
—
10.41, 20.83, 41.66,
83.31, or 166.63
—
—
Preliminary Rev. 0.6
15
Si5311
DSPLL™
a jitter-attenuated version of the CLKIN input, resulting
in a “clean” CLKOUT output with sharp rising and falling
edges. The CLKOUT output is a resampled version of
the CLKIN input with all CLKOUT transitions occurring
synchronously with the rising edges of the MULTOUT
output. The rising edges of CLKOUT are insensitive to
the location of the falling edges of the CLKIN input.
Thus the period of CLKOUT, measured rising edge to
rising edge, is not affected by the CLKIN duty cycle or
by jitter on the falling edge of CLKIN.
The falling edges of CLKOUT may be affected by the
location of the CLKIN falling edges as follows: If the
duty cycle error of CLKIN is significant relative to the
period of MULTOUT, then
1. The CLKOUT duty cycle may deviate from 50% (the falling
edge of CLKOUT will be time quantized to the nearest
rising edge of MULTOUT.)
2. Jitter on the falling edges of CLKIN may result in a
CLKOUT duty cycle that alternates between two discrete
values.
The PLL structure (shown in Figure 1 on page 4) utilizes
Silicon Laboratories' DSPLL technology to produce
superior jitter performance while eliminating the need
for external loop filter components found in traditional
PLL implementations. This is achieved by using a digital
signal processing (DSP) algorithm to replace the loop
filter commonly found in analog PLL designs. This
algorithm processes the phase detector error term and
generates a digital control value to adjust the frequency
of the voltage controlled oscillator (VCO). The
technology produces clocks with less jitter than is
generated using traditional methods. In addition,
because external loop filter components are not
required, sensitive noise entry points are eliminated,
thus making the DSPLL less susceptible to board-level
noise sources.
Clock Multiplier
The DSPLL phase locks to the clock input signal
(CLKIN) and generates an output clock (MULTOUT) at
a multiple of the input clock frequency. The MULTOUT
output is configured to operate in the 150–167 MHz, the
600–668 MHz, the 1.2–1.33 GHz, or the 2.4–2.67 GHz
frequency range using the MULTSEL0 and MULTSEL1
control inputs as indicated in Table 11. Values for typical
applications are given in Table 12.
Note: When the Si5310 is configured as a 1:1 multiplier, the
CLKOUT output is not valid.
Reference Clock
The reference clock input (REFCLK) is used to center
the DSPLL and also to act as a reference for
determination of the PLL lock status. REFCLK is a
multiple of the CLKIN frequency, and can be provided in
any one of five frequency ranges (9.375–10.438 MHz,
The amount of jitter present in the MULTOUT output is a
function of the DSPLL jitter transfer function and jitter
generation characteristic. Details are provided in the
PLL Performance section of this document. (See
Figures 6, 7, 8, and 9.) The amount of jitter that the
DSPLL can tolerate on the CLKIN input is specified in
Tables 5, 6, 7, and 8.
The DSPLL implementation in the Si5311 is insensitive
to the duty cycle of the CLKIN input. The MULTOUT
output will continue to exhibit a very good duty cycle
characteristic even when the CLKIN input duty cycle is
degraded.
18.78–20.875 MHz,
37.500–41.750 MHz,
75.00–
83.50 MHz, or 150–167.00 MHz). The REFCLK rate is
automatically detected by the Si5311, so no control
inputs are needed for REFCLK frequency selection. The
REFCLK input may be synchronous or asynchronous
with respect to the CLKIN input. The frequency
relationship between REFCLK and CLKIN is indicated
in Table 11. In many applications, it may be desirable to
tie REFCLK and CLKIN together and drive them from
the same clock source. The Si5311 is insensitive to the
phase relationship between CLKIN and REFCLK, so
these differential inputs may be driven in phase or 180°
out of phase if this simplifies board layout. Values for
typical applications are given in Table 12.
1x Multiplication
The Si5311 Clock Multiplier function may also be
utilized as a 1x multiplier in order to provide jitter
attenuation and duty cycle correction without
multiplication of the input clock frequency.
DSPLL Lock Detection (Loss-of-Lock)
The Si5311 provides lock-detect circuitry that indicates
whether the DSPLL has frequency locked with the
incoming CLKIN signal. The circuit compares the
frequency of a divided down version of the multiplier
output with the frequency of the supplied reference
clock. If the divided multiplier output frequency deviates
from that of the reference clock by the amount specified
in Table 4 on page 8, the PLL is declared out of lock,
and the loss-of-lock (LOL) pin is asserted.
Note: When the Si5311 is configured as a 1:1 multiplier, the
CLKOUT output is not valid.
Clock Regeneration
When the MULTOUT output is configured to operate in
either the 150–167 MHz or the 600–667 MHz range, the
Si5311 clock regeneration (CLKOUT output) is also
provided. In this case, the DSPLL is used to regenerate
While out of lock, the DSPLL will try to reacquire lock
16
Preliminary Rev. 0.6
Si5311
with the input clock. During reacquisition, the multiplier the multiplier ratio desired, the larger the jitter
output (MULTOUT) will drift over
a
range of generation. Table 4 gives the jitter generation values for
approximately 1% relative to the supplied reference specified MULTSEL0/1 settings and input clock rates.
clock. The LOL output will remain asserted until the
divided multiplier output frequency differs from the
PLL Jitter Transfer Functions (MULTSEL[1:0]=00) (dB)
REFCLK frequency by less than the amount specified in
0
CLKIN=622MHz
Table 4.
−1
Note: LOL is not asserted during PWRDN/CAL.
−2
PLL Performance
−3
The Si5311 DSPLL circuitry is designed to provide low
−4
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking. Each
−5
of these key performance parameters is described more
−6
fully in the following sections.
−7
Jitter Tolerance
−8
Jitter tolerance for the Si5311 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
−9
103
104
105
106
added to the incoming clock before the PLL exceeds its
allowable operating range and loses lock. The tolerance
is a function of the jitter frequency, the incoming clock
rate, and the MULTSEL0/1 settings.
Figure 6. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 00
(MULTOUT = 2400–2672 MHz)
The jitter tolerance for specified jitter frequencies and
input clock rates is given in Tables 5, 6, 7, and 8.
Jitter Transfer
PLL Jitter Transfer Functions (MULTSEL[1:0]=01) (dB)
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that will be passed on to the Si5311
CLKOUT and MULTOUT outputs. The DSPLL
technology used in the Si5311 provides a tightly
controlled jitter transfer curve because many of the PLL
gain parameters are determined by digital signal
processing algorithms which do not vary over supply
voltage, process, and temperature. In a system
application, a well-controlled transfer curve minimizes
the output clock jitter variation from board to board,
providing more consistent system level jitter
performance.
0
CLKIN=622MHz
−1
−2
−3
−4
CLKIN=311MHz
−5
−6
−7
−8
−9
103
104
105
106
The jitter transfer characteristic is a function of the
MULTSEL0/1 settings and the input clock rate. Higher
input clock rates produce higher bandwidth transfer
functions with lower jitter peaking. Table 4 gives the
3 dB bandwidth and peaking values for specified input
clock rates and MULTSEL0/1 settings. Figures 6, 7, 8,
and 9 show a family of jitter transfer curves for different
input clock rates.
Figure 7. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 01
(MULTOUT = 1200–1336 MHz)
Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
a function of MULTSEL0/1 settings and input clock
frequency. For clock multiplier applications, the higher
Preliminary Rev. 0.6
17
Si5311
and will begin to lock to the incoming clock.
PLL Jitter Transfer Functions (MULTSEL[1:0]=10) (dB)
PLL Self-Calibration
0
−1
−2
−3
−4
−5
−6
−7
−8
CLKIN=622MHz
Si5311 device provides an internal self-calibration
function that optimizes the loop gain parameters within
the internal DSPLL. Self-calibration is initiated by a
high-to-low transition of the PWRDN/CAL signal while a
valid reference clock is supplied to the REFCLK input.
CLKIN=39MHz
For optimal jitter performance, the supply voltage
should be stable at 2.5 V ±10% when calibration is
initiated. The PWRDN/CAL signal should be held high
for at least 1 µS after the supply has stabilized before
transitioning low to initiate self-calibration. See Silicon
Laboratories application note AN42 for suggested
methods of generating the PWRDN/CAL signal for
initiation of self-calibration.
−9
103
104
105
106
Figure 8. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 10
Device Grounding
The Si5311 uses the GND pad on the bottom of the 20-
pin micro leaded package (MLP) for device ground. This
pad should be connected directly to the analog supply
ground. See Figures 12 and 13 for the ground (GND)
pad location.
(MULTOUT = 600–668 MHz)
PLL Jitter Transfer Functions (MULTSEL[1:0]=11) (dB)
0
CLKIN=155MHz
−1
Bias Generation Circuitry
−2
−3
The Si5311 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption compared with traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
−4
CLKIN=9.7MHz
−5
−6
−7
−8
−9
Differential Input Circuitry
The Si5311 provides differential inputs for both the input
clock (CLKIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 10. In applications where direct dc
coupling is possible, the 0.1 µF capacitors may be
omitted. The CLKIN and REFCLK input amplifiers
require input signals with minimum differential peak-to-
peak voltages as specified in Table 2 on page 6.
103
104
105
106
Figure 9. PLL Jitter Transfer Functions,
MULTSEL[1:0] = 11
(MULTOUT = 150–167 MHz)
Device Power-Down
The Si5311 PWRDN/CAL input can be used to hold the
device in a power-down state when not in use. When
the PWRDN/CAL input is asserted (set high), the
CLKOUT and MULTOUT output drivers are disabled
and the positive and negative terminals of the CLKOUT
and MULTOUT outputs are each tied to VDD through
100 Ω on-chip resistors. This feature is useful in
reducing power consumption in applications that
employ redundant clock sources. When PWRDN/CAL is
released (set to low) the digital logic is reset to a known
initial condition and the DSPLL circuitry is recalibrated
Differential Output Circuitry
The Si5311 utilizes a current mode logic (CML)
architecture to output both the regenerated clock
(CLKOUT) and the multiplied clock (MULTOUT). An
example of output termination with ac coupling is shown
in Figure 11. For applications in which direct dc coupling
is possible, the 0.1 µF capacitors may be omitted. The
differential peak-to-peak voltage swing of the CML is
listed in Table 2 on page 6.
18
Preliminary Rev. 0.6
Si5311
Clock source
Si5311
VDD
2.5 kΩ
CLKIN +,
RFCLK +
0.1 µ F
0.1 µ F
Zo = 50 Ω
Zo = 50 Ω
10 kΩ
2.5 kΩ
102Ω
CLKIN –,
RFCLK –
10 kΩ
GND
Figure 10. Input Termination for CLKIN and REFCLK (AC Coupled)
Si5311
VDD
VDD
50 Ω
100 Ω
CLKOUT+,
MULTOUT+
0.1 µ F
0.1 µ F
Zo = 50 Ω
Zo = 50 Ω
CLKOUT–,
MULTOUT–
100 Ω
VDD
50 Ω
VDD
Figure 11. Output Termination for CLKOUT and MULTOUT (AC Coupled)
Preliminary Rev. 0.6
19
Si5311
Pin Descriptions: Si5311
20 19 18 17
16
10
PWRDN
VDD
REXT
VDD
1
2
3
4
5
15
14
13
GND
CLKOUT+
GND
Pad
12 CLKOUT–
11
REFCLK+
REFCLK–
VDD
6
7
8
9
Top View
Figure 12. Si5311 Pin Configuration
Table 13. Si5311 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
External Bias Resistor.
1
REXT
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 kΩ (1%) resis-
tor.
Supply Voltage.
2, 7, 11, 14
VDD
GND
2.5 V
GND
Nominally 2.5 V.
Supply Ground.
3, 8, 18, and
GND Pad
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 13)
must be connected directly to supply ground.
Differential Reference Clock.
4, 5
REFCLK+,
REFCLK–
I
See Table 2
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock regener-
ation and multiplication. Additionally, the reference
clock is used as a reference in generation of the
LOL output and to bound the frequency drift of
MULTOUT when CLKIN is not present.
Loss of Lock.
6
LOL
O
I
LVTTL
This output is driven high when a divided version of
the clock multiplier output deviates from the refer-
ence clock frequency by the amount specified in
Table 4 on page 8.
Differential Clock Input.
9, 10
CLKIN+,
CLKIN–
See Table 2
Differential input clock from which MULTOUT is
derived.
20
Preliminary Rev. 0.6
Si5311
Table 13. Si5311 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Differential Clock Output.
12, 13
CLKOUT–,
CLKOUT+
O
CML
The clock output signal is a regenerated version of
the input clock signal present on CLKIN. It is phase
aligned with MULTOUT and is updated on the rising
edge of MULTOUT.
Notes:The CLKOUT output is not valid for MULTSEL[1:0]
= 00 or MULTSEL[1:0] = 01. The CLKOUT output
is also not valid for MULTOUT:CLKIN ratios of 1:1
(MULTOUT = 1x CLKIN).
Connection of an improperly terminated
transmission line to the CLKOUT output can
cause reflections that may adversely affect the
performance of the MULTOUT output. If the
CLKOUT output is not used, these pins should be
either tied to VDD (recommended), left
unconnected, or connected to a properly
terminated transmission line.
15
PWRDN/CAL
I
LVTTL
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-
to-low transition on this pin. (See "PLL Self-Calibra-
tion‚" on page 18.)
Note: This input has a weak internal pulldown.
Differential Multiplier Output.
16, 17
MULTOUT–,
MULTOUT+
O
CML
The multiplier output is generated from the signal
present on CLKIN. In the absence of CLKIN, the
REFCLK is used to bound the frequency of MUL-
TOUT according to Table 4 on page 8.
Note: Connection of an improperly terminated
transmission line to the MULTOUT output can
cause reflections that may adversely affect the
CLKOUT output. If the MULTOUT output is not
used, these pins should be either tied to VDD
(recommended), left unconnected, or connected
to a properly terminated transmission line.
Multiplier Rate Select.
19
20
MULTSEL1,
MULTSEL0
I
LVTTL
These pins configure the onboard PLL-based clock
multiplier for clock generation at one of four user
selectable clock rates.
Note: These inputs have weak internal pulldowns.
No Connect.
This pin should be tied to ground.
NC
Preliminary Rev. 0.6
21
Si5311
Ordering Guide
Table 14. Ordering Guide
Part Number
Si5311-BM
Package
Temperature
–40°C to 85°C
20-pin MLP
22
Preliminary Rev. 0.6
Si5311
Package Outline
Figure 13 illustrates the package details for the Si5311. Table 15 lists the values for the dimensions shown in the
illustration.
2X
TOP VIEW
0.25
C
A
BOTTOM VIEW
4
A
D
10
D/2
0.05
C
4X
P
M
D1
b
0.10
C
A
B
A
R
A1
D2
D1/2
A2
D2/2
2X
A3
8.
N
0.25
C
B
N
4X
P
5
6
E1/2
E/2
1
2
3
1
2
3
0.50 DIA.
(Ne-1)Xe
REF.
4X
Q
E1
E
B
E2
E2/2
L
0.20
C
B
0
2X
e
C
0.20
C
A
SEATING
PLANE
(Nd-1)Xe
REF.
2X
11
A1
b
4
NOTES:
1.
2.
C
C
DIE THICKNESS ALLOW ABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM)
DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. - 1994.
C
C
L
L
SECTION "C-C"
SCALE: NONE
N IS THE NUMBER OF TERMINALS.
Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION &
Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION.
3.
e
e
4.
5.
DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETW EEN 0.20 AND 0.25mm FROM TERMINAL TIP.
TERMINAL TIP
THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURFACE OF THE
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF PACKAGE BODY.
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
6.
7.
8.
9.
EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
ALL DIMENSIONS ARE IN MILLIMETERS.
THE SHAPE SHOW N ON FOUR CORNERS ARE NOT ACTUAL I/O.
PACKAGE W ARPAGE MAX 0.05mm.
10. APPLIED FOR EXPOSED PAD AND TERMINALS.
EXCLUDE EMBEDDING PART OF EXPOSED
PAD FROM MEASURING.
11. APPLIED ONLY FOR TERMINALS.
Figure 13. 20-pin Micro Leaded Package (MLP)
Table 15. Package Diagram Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
—
0.00
—
Nom
0.85
Max
1.00
0.05
0.80
Min
Nom
3.75 BSC
2.10
20
Max
A
A1
A2
A3
b
E1
E2
N
0.01
1.95
2.25
0.65
0.20 REF
—
4.00 BSC
3.75 BSC
2.10
0.50 BSC
4.00 BSC
Nd
Ne
L
5
0.18
0.30
5
D
0.50
0.24
0.30
0.13
—
0.60
0.42
0.40
0.17
—
0.75
0.60
0.65
0.23
12°
D1
D2
e
P
1.95
2.25
Q
R
E
θ
Preliminary Rev. 0.6
23
Si5311
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
24
Preliminary Rev. 0.6
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