SI53112-A00AGMR_技术文档

Si53112

DB1200ZL 12-OUTPUT PCI

E

GEN 3 BUFFER

Features

 Twelve 0.7 V low-power, push-  PLL or bypass mode

pull, HCSL-compatible

PCIe Gen 3 outputs

 Spread spectrum tolerable

 1.05 to 3.3 V I/O supply voltage

 50 ps output-to-output skew

 50 ps cyc-cyc jitter (PLL mode)

 Individual OE HW pins for each

output clock

 100 MHz /133 MHz PLL

operation, supports PCIe and

QPI

 Low phase jitter (Intel QPI, PCIe

Gen 1/2/3/4 common clock

compliant)

 PLL bandwidth SW SMBUS

programming overrides the latch

value from HW pin

 Gen 3 SRNS Compliant

 100 ps input-to-output delay

Ordering Information:

 Extended Temperature:

See page 30.

 9 selectable SMBUS addresses

–40 to 85 °C

 SMBus address configurable to

allow multiple buffers in a single

control network 3.3 V supply

voltage operation

 Package: 64-pin QFN

Patents pending

 For higher output devices or

variations of this device, contact

Silicon Labs

Applications

 Server

 Datacenter

 Storage

 Enterprise Switches and Routers

Description

The Si53112 is a low-power, 12-output, differential clock buffer that meets

all of the performance requirements of the Intel DB1200ZL specification.

®

The device is optimized for distributing reference clocks for Intel

QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,

SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)

applications. The VCO of the device is optimized to support 100 MHz and

133 MHz operation. Each differential output has a dedicated hardware

output enable pin for maximum flexibility and power savings. Measuring

PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter

Tool. Download it for free at www.silabs.com/pcie-learningcenter.

Rev. 1.1 12/15

Si53112

Functional Block Diagram

OE_[11:0]

12

FB_OUT

SSC Compatible

PLL

DIF_[11:0]

CLK_IN

100M_133

HBW_BYPASS_LBW

SA_0

SA_1

Control

Logic

PWRGD / PWRDN

SDA

SCL

2

Rev. 1.1

Si53112

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2. OE and Output Enables (Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5. PWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.8. Buffer Power-Up State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6. Pin Descriptions: 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Rev. 1.1

3

Si53112

1. Electrical Specifications

Table 1. DC Operating Characteristics

V_{DD_A}= 3.3 V±5%, V_DD= 3.3 V±5%

Parameter

Symbol

Test Condition

3.3 V ±5%

Min

3.135

0.9975

2.0

Max

3.465

VDD+0.3

0.8

Unit

V

3.3 V Core Supply Voltage

VDD/VDD_A

VDD_IO

1

3.3 V I/O Supply Voltage

1.05 V to 3.3 V ±5%

VDD

V

3.3 V Input High Voltage

3.3 V Input Low Voltage

V

IH

V

VSS-0.3

–5

V

IL

2

Input Leakage Current

I

0 < VIN < VDD

VDD

+5

µA

V

IL

3

3.3 V Input High Voltage

V

0.7

VDD+0.3

0.35

0.8

IH_FS

3

3.3 V Input Low Voltage

V

VSS–0.3

0

V

IL_FS

3.3 V Input Low Voltage

3.3 V Input Med Voltage

3.3 V Input High Voltage

V

IL_Tri

V

1.2

1.8

V

IM_Tri

V

2.2

VDD

—

V

IH_Tri

4

3.3 V Output High Voltage

V

I

= –1 mA

= 1 mA

OL

2.4

V

OH

4

3.3 V Output Low Voltage

V

I

—

0.4

V

OL

5

Input Capacitance

C

2.5

4.5

pF

nH

°C

IN

5

Output Capacitance

C

2.5

4.5

OUT

Pin Inductance

Ambient Temperature

Notes:

L

—

7

T

No Airflow

–40

85

A

1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.

2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state

current requirements.

3. Internal voltage reference is to be used to guarantee V_IH_FS and V_IL_FS thresholds levels over full operating range.

4. Signal edge is required to be monotonic when transitioning through this region.

5. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.

Table 2. Current Consumption

T_A= –40 to 85 °C; supply voltage V_DD= 3.3 V ±5%

Parameter

Symbol

Test Condition

133 MHz, VDD Rail

Min

—

Typ

18

17

85

0.4

2

Max

25

20

110

1

Unit

mA

Operating Current

IDD

VDD

IDD

133 MHz, VDDA + VDDR, PLL Mode

133 MHz, CL = Full Load, VDD IO Rail

Power Down, VDD Rail

—

VDDA

—

VDDIO

VDDPD

VDDAPD

VDDIOPD

Power Down Current IDD

—

IDD

Power Down, VDDA Rail

—

5

Power Down, VDD_IO Rail

—

0.2

0.5

4

Rev. 1.1

Si53112

Table 3. Output Skew, PLL Bandwidth and Peaking

T_A= –40 to 85 °C; supply voltage V_DD= 3.3 V ±5%

Parameter

Test Condition

Min

TYP

Max

Unit

CLK_IN, DIF[x:0]

Input-to-Output Delay in PLL Mode

Nominal Value

–100

27

100

ps

1,2,3,4

CLK_IN, DIF[x:0]

DIF[11:0]

Input-to-Output Delay in Bypass Mode

\Nominal Value

2.5

–100

–250

0

3.3

39

4.5

100

250

50

ns

ps

2,4,5

Input-to-Output Delay Variation in PLL mode

2,4,5

Over voltage and temperature

Input-to-Output Delay Variation in Bypass Mode

3.7

20

2,4,5

Over voltage and temperature

Output-to-Output Skew across all 12 Outputs

1,2,3,4,5

(Common to Bypass and PLL Mode)

6

PLL Jitter Peaking

PLL Bandwidth

(HBW_BYPASS_LBW = 0)

—

0.4

0.1

0.7

2

2.0

2.5

1.4

4

dB

6

(HBW_BYPASS_LBW = 1)

7

(HBW_BYPASS_LBW = 0)

MHz

7

PLL Bandwidth

(HBW_BYPASS_LBW = 1)

Notes:

1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the

corresponding input.

2. Measured from differential cross-point to differential cross-point.

3. This parameter is deterministic for a given device.

4. Measured with scope averaging on to find mean value.

5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created

by it.

6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL

jitter peaking.

7. Measured at 3 db down or half power point.

Rev. 1.1

5

Si53112

Table 4. Phase Jitter

Parameter

Test Condition

Min

Typ

Max

Unit

1,2,3

Phase Jitter

PLL Mode

PCIe Gen 1, Common Clock

—

29

86

ps

PCIe Gen2 Low Band, Common Clock

—

2.0

1.9

3.0

3.1

1.0

0.71

1.0

0.5

0.3

0.2

ps

(RMS)

1,3,4,5

F < 1.5 MHz

PCIe Gen2 High Band, Common Clock

ps

(RMS)

1,3,4,5

1.5 MHz < F < Nyquist

PCIe Gen 3, Common Clock

(PLL BW 2–4 MHz, CDR = 10 MHz)

0.45

0.32

0.45

0.21

0.13

0.11

ps

(RMS)

1,3,4,5

PCIe Gen 3 Separate Reference No Spread, SRNS

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)

ps

(RMS)

1,3,4,5

PCIe Gen 4, Common Clock

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)

ps

(RMS)

1,4,5,8

®

Intel QPI & Intel SMI

ps

(RMS)

1,6,7

(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)

Intel QPI & Intel SMI

(8 Gb/s, 100 MHz, 12 UI)

ps

(RMS)

1,6

Intel QPI & Intel SMI

(9.6 Gb/s, 100 MHz, 12 UI)

ps

(RMS)

1,6

Notes:

1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a

smaller sample size have to be extrapolated to this BER target.

2. ζ = 0.54 implies a jitter peaking of 3 dB.

3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest

specification.

4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be

extrapolated to this BER target.

8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

6

Rev. 1.1

Si53112

Table 4. Phase Jitter (Continued)

1,2,3

Additive Phase Jitter

Bypass Mode

PCIe Gen 1

—

10

—

ps

PCIe Gen2 Low Band

1.2

ps

(RMS)

1,3,4,5

F < 1.5 MHz

PCIe Gen2 High Band

1.5 MHz < F < Nyquist

—

1.3

0.25

0.12

0.1

—

ps

(RMS)

1,3,4,5

PCIe Gen3

(PLL BW 2–4 MHz, CDR = 10 MHz)

ps

(RMS)

1,3,4,5

PCIe Gen 4, Common Clock

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)

ps

(RMS)

1,4,5,8

Intel QPI & Intel® SMI

ps

(RMS)

1,6,7

(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)

Intel QPI & Intel® SMI

ps

(RMS)

1,6

(8 Gb/s, 100 MHz, 12 UI)

Intel QPI & Intel® SMI

(9.6 Gb/s, 100 MHz, 12 UI)

0.09

ps

(RMS)

1,6

Notes:

1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a

smaller sample size have to be extrapolated to this BER target.

2. ζ = 0.54 implies a jitter peaking of 3 dB.

3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest

specification.

4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be

extrapolated to this BER target.

8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

Rev. 1.1

7

Si53112

Table 5. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)¹

Parameter

Symbol

CLK 100 MHz, 133 MHz

Unit

Notes

Min

Typ

Max

2

Clock Stabilization Time

Long Term Accuracy

T

—

1.5

1.8

100

ms

ppm

ns

STAB

3 4 5

L

, ,

ACC

3 4 6

Absolute Host CLK Period (100MHz)

Absolute Host CLK Period (133MHz)

Edge Rate

T

9.94900

7.44925

1.0

10.05100

7.55075

4.0

, ,

ABS

3 4 6

T

ns

, ,

ABS

3 4 7

Edge_rate

∆ Trise

V/ns

ps

, ,

3 8 9

Rise Time Variation

—

125

, ,

3 8 9

Fall Time Variation

∆ Tfall

—

125

ps

, ,

3 8 10 11

Rise/Fall Matching

T

/

—

20

%

, , ,

RISE_MAT

T

FALL_MAT

3 8 12

Voltage High (typ 0.7 V)

Voltage Low (typ 0.7 V)

Maximum Voltage

V

660

–150

—

850

150

mV

, ,

HIGH

3 8 13

V

, ,

LOW

8

V

1150

550

MAX

3 8 14 15

Absolute Crossing Point Voltages

Vox

250

, , , ,

ABS

REL

16

3 8 16 17

Relative Crossing Point Voltages

Vox

, , ,

3 8 18

Total Variation of Vcross Over All

Edges

Total ∆

Vox

—

140

55

mV

, ,

3 4

Duty Cycle

DC

45

—

%

V

,

3 8 19

Maximum Voltage (Overshoot)

Maximum Voltage (Undershoot)

V

+ 0.3

– 0.3

, ,

ovs

High

3 8 20

V

, ,

uds

Low

8

Rev. 1.1

Si53112

Table 5. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)¹(Continued)

Parameter

Symbol

CLK 100 MHz, 133 MHz

Min Typ Max

0.2 N/A

Unit

Notes

3 8

Ringback Voltage

Notes:

V

,

rb

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the time

that stable clocks are output from the buffer chip (PLL locked).

3. Test configuration is Rs = 33.2 , Rp = 49.9, 2 pF for 100  transmission line; Rs = 27 , Rp = 42.2, 2 pF for 85 

transmission line.

4. Measurement taken from differential waveform.

5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are

99,750,00 Hz, 133,000,000 Hz.

6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum

specified period.

7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from

–150 mV to +150 mV on the differential waveform . Scope is set to average because the scope sample clock is making

most of the dynamic wiggles along the clock edge Only valid for Rising clock and Falling CLOCK. Signal must be

monotonic through the Vol to Voh region for Trise and Tfall.

8. Measurement taken from single-ended waveform.

9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the

falling edge rate (average) of CLOCK.

11. Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).

12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.

13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.

14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of

CLK.

15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing.

16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)

Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figures 3-4 for further clarification).

18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the

maximum allowed variance in Vcross for any particular system.

19. Overshoot is defined as the absolute value of the maximum voltage.

20. Undershoot is defined as the absolute value of the minimum voltage.

Rev. 1.1

9

Si53112

Table 6. Clock Periods Differential Clock Outputs with SSC Disabled

SSC ON

Measurement Window

Units

Center

Freq, MHz

1 Clock

1 µs

0.1 s

1 µs

1 Clock

-C-C Jitter

-SSC

-ppm

Long

0 ppm

Period

+ppm

Long

+SSC

Short

+C-C

Jitter

AbsPer

Max

AbsPer

Min

Short

Term AVG

Min

Term AVG Nominal Term AVG Term AVG

Min

Max

100.00

133.33

9.94900

7.44925

9.99900

7.49925

10.00000 10.00100

10.05100

7.55075

ns

7.50000

7.50075

Table 7. Clock Periods Differential Clock Outputs with SSC Enabled

SSC ON

Measurement Window

Units

Center

Freq, MHz

1 Clock

1 µs

0.1 s

1 µs

1 Clock

-C-C Jitter

-SSC

-ppm

Long

0 ppm

Period

+ppm

Long

+SSC

Short

+C-C

Jitter

AbsPer

Max

AbsPer

Min

Short

Term AVG

Min

Term AVG Nominal Term AVG Term AVG

Min Max Max

99.75

9.94900

7.44925

9.99900

7.49925

10.02406 10.02506 10.02607 10.05126 10.10126

ns

133.33

7.51805

7.51880

7.51955

7.53845

7.58845

Table 8. Absolute Maximum Ratings

Parameter

Symbol

Min

Max

4.6

—

Unit

1

3.3 V Core Supply Voltage

VDD/VDD_A

VDD_IO

VIH

—

V

1

3.3 V I/O Supply Voltage

1,2

3.3 V Input High Voltage

—

V

1

3.3 V Input Low Voltage

VIL

−0.5

–65

2000

V

1

Storage Temperature

t

150

—

°C

V

s

3

Input ESD protection

ESD

Notes:

1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.

2. Maximum VIH is not to exceed maximum V_DD

.

3. Human body model.

10

Rev. 1.1

Si53112

2. Functional Description

2.1. CLK_IN, CLK_IN

The differential input clock is expected to be sourced from a clock synthesizer, e.g. CK420BQ, CK509B, or CK410B+.

2.2. OE and Output Enables (Control Registers)

Each output can be individually enabled or disabled by SMBus control register bits. Additionally, each output of the

DIF[11:0] has a dedicated OE pin. The OE pins are asynchronous, asserted-low signals. The Output Enable bits in

the SMBus registers are active high and are set to enable by default. The disabled state for the DB1200ZL NMOS

push-pull output is Low/Low. Please note that the logic level for assertion or deassertion is different in software

than it is on hardware. This follows hardware default nomenclature for communication channels (e.g., output is

enabled if the OE# pin is pulled low) and still maintains software programming logic (e.g., output is enabled if OE

register is true). Table 9 is a truth table depicting enabling and disabling of outputs via hardware and software. Note

that, for the output to be active, the control register bit must be a 1 and the OE pin must be a 0.

Note: The assertion and deassertion of this signal is absolutely asynchronous.

Table 9. Si53112 Output Management

Inputs

OE Hardware Pins and Control Register Bits

Outputs

PLL State

PWRGD/

PWRDN

CLK_IN/

CLK_IN

SMBUS

Enable Bit

OE Pin

DIF/DIF[11:0]

FB_OUT/

FB_OUT

0

x

0

1

x

0

1

Low/Low

Running

Low/Low

Running

OFF

ON

1

Running

2.2.1. OE Assertion (Transition from 1 to 0)

All differential outputs that were disabled are to resume normal operation in a glitch-free manner. The latency from

the assertion to active outputs is 4 to 12 DIF clock periods.

2.2.2. OE De-Assertion (Transition from 0 to 1)

The impact of deasserting OE is that each corresponding output will transition from normal operation to disabled in

a glitch-free manner. A minimum of four valid clocks will be provided after the deassertion of OE. The maximum

latency from the deassertion to disabled outputs is 12 DIF clock periods.

2.3. 100M_133M—Frequency Selection

The Si53112 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.

100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.

Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53112 is operated in 1:1

mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-down

resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 10.

Table 10. Frequency Program Table

100M_133M

Optimized Frequency (CLK_IN = CLK_OUT)

0

1

133.33 MHz

100.00 MHz

Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner.

Rev. 1.1

11

Si53112

2.4. SA_0, SA_1—Address Selection

SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53112. The two tri-

level input pins that can configure the device to nine different addresses.

Table 11. SMBUS Address Table

SA_1

L

SA_0

L

SMBUS Address

D8

DA

DE

C2

C4

C6

CA

CC

CE

L

M

H

L

M

H

L

M

H

L

H

M

H

2.5. PWRGD/PWRDN

PWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to

indicating a power-down condition. PWRGD (assertion) is used by the Si53112 to sample initial configurations,

such as frequency select condition and SA selections. After PWRGD has been asserted high for the first time, the

pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to

invoke power-saving mode. PWRDN is a completely asynchronous active low input. When entering power-saving

mode, PWRDN should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down

in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior to turning off the VCO. When

PWRDN is deasserted high, all clocks will start and stop without any abnormal behavior and will meet all ac and dc

parameters.

Note: The assertion and deassertion of PWRDN is absolutely asynchronous.

Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended.

Operation in this mode may result in glitches, excessive frequency shifting, etc.

Table 12. PWRGD/PWRDN Functionality

PWRGD/

PWRDN

DIF

0

1

Low

Normal

12

Rev. 1.1

Si53112

2.5.1. PWRDN Assertion

When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/

LOW on the next DIF high-to-low transition.

PWRDWN

DIF

Figure 1. PWRDN Assertion

2.5.2. PWRGD Assertion

The power-up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion

of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs

stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN

deassertion to a voltage greater than 200 mV.

Tstable

<1.8 ms

PWRDWN

DIF

Tdrive_Pwrdn#

<300 µs; > 200 mV

Figure 2. PWRDG Assertion (Pwrdown—Deassertion)

Rev. 1.1

13

Si53112

2.6. HBW_BYPASS_LBW

The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 13 for VIL_Tri, VIM_Tri, and VIH_Tri

signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In

PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive

cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In the case of PLL mode, the input clock is

passed through a PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be

selected by asserting the HBW_BYPASS_LBW input pin to the appropriate level described in Table 13.

Table 13. PLL Bandwidth and Readback Table

HBW_BYPASS_LBW Pin

Mode

LBW

Byte 0, Bit 7

Byte 0, Bit 6

L

M

H

0

1

0

1

BYPASS

HBW

The Si53112 has the ability to override the latch value of the PLL operating mode from hardware strap pin 5 via the

use of Byte 0 and bits 2 and 1. Byte 0 bit 3 must be set to 1 to allow the user to change Bits 2 and 1, affecting the

PLL. Bits 7 and 6 will always read back the original latched value. A warm reset of the system will have to be

accomplished if the user changes these bits.

2.7. Miscellaneous Requirements

Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps)

functionality is optional.

Logic Levels: SMBus logic levels are based on a percentage of V

for the controller and other devices on the

DD

bus. Assume all devices are based on a 3.3 V supply.

Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock

stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than

this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all

data transfers can be completed as specified without the use of clock/data stretching.

General Call: It is assumed that the clock buffer will not have to respond to the “general call.”

Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in

Section 3 of the SMBus 2.0 specification.

Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual

data sheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board

designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k range.

Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock

driver plus one/two more SMBus devices on the platform for capacitive loading purposes.

Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock

buffer is specified as a standard mode device and is not required to support this feature. However, it is considered

a good design practice to include the filters.

PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the

device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and

in the data sheet.

14

Rev. 1.1

Si53112

2.8. Buffer Power-Up State Machine

Table 14. Buffer Power-Up State Machine

State

Description

3.3 V buffer power is off.

0

1

After 3.3 V supply is detected to rise above 1.8–2.0 V, the

buffer enters State 1 and initiates a 0.1–0.3 ms delay.

2

3

Buffer waits for a valid clock on the CLK input and PWRDN

de-assertion.

Once the PLL is locked to the CLK_IN input clock, the buffer

enters state 3 and enables outputs for normal operation.

Notes:

1. The total power-up latency from power-on to all outputs active must be less

than 1.8 ms (assuming a valid clock is present on CLK_IN input).

2. If power is valid and power-down is deasserted but no input clocks are

present on the CLK_IN input, DIF clocks must remain disabled. Only after

valid input clocks are detected, valid power, PWRDN deasserted with the

PLL locked/stable are the DIF outputs enabled.

No input clock

S1

S2

Wait for input

clock and

powerdown

deassertion

Delay

0.1 ms – 0.3 ms

Powerdown Asserted

S3

S0

Normal

Operation

Power Off

Figure 3. Buffer Power-Up State Diagram

Rev. 1.1

15

Si53112

3. Test and Measurement Setup

3.1. Input Edge

Input edge rate is based on single-ended measurement. This is the minimum input edge rate at which the Si53112

is guaranteed to meet all performance specifications.

Table 15. Input Edge Rate

Frequency

100 MHz

133 MHz

Min

0.35

Max

N/A

Unit

V/ns

3.1.1. Measurement Points for Differential

Slew_fall

Slew_rise

+150 mV

-150 mV

0.0 V

V_swing

0.0 V

-150 mV

Diff

Figure 4. Measurement Points for Rise Time and Fall Time

Vovs

VHigh

Vrb

VLow

Vuds

Figure 5. Single-Ended Measurement Points for V_ovs, V_uds, V_rb

16

Rev. 1.1

Si53112

TPeriod

Low Duty Cycle %

High Duty Cycle %

Skew measurement

point

0.000 V

Figure 6. Differential (CLOCK–CLOCK) Measurement Points (T_period, Duty Cycle, Jitter)

3.2. Termination of Differential Outputs

All differential outputs are to be tested into a 100  or 85  differential impedance transmission line. Source

terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be

supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC

clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond

200 MHz, trace lengths must be restricted to avoid signal integrity problems.

Table 16.

Clock

Board Trace Impedance

Rs

Rp

N/A

Unit



DIFF Clocks—50  configuration

DIFF Clocks—43  configuration

100

85

33+5%

27+5%



3.2.1. Termination of Differential NMOS Push-Pull Type Outputs

Rs

Clock

T-Line

10" Typical

Receiver

2 pF

Source Terminated

Rs

2 pF

Clock #

T-Line

10" Typical

Figure 7. 0.7 V Configuration Test Load Board Termination for NMOS Push-Pull

Rev. 1.1

17

Si53112

4. Control Registers

4.1. Byte Read/Write

Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register

number.

4.1.1. Byte Read

The standard byte read is as shown in Figure 8. It is an extension of the byte write. The write start condition is

repeated; then, the slave device starts sending data, and the master acknowledges it until the last byte is sent. The

master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the

command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte

must be the byte transfer count.

1

7

1 1

8

1 1

7

1 1

8

1 1

r

Rd

Data Byte 0

Wr

A

N

P

T Slave

Command

A

Slave

Register # to

read

2 x 7 bit = 1

Not ack

Command

starT

Condition

Byte Read Protocol

repeat starT

Acknowledge

stoP

Condition

Master to

Slave to

Figure 8. Byte Read Protocol

4.1.2. Byte Write

Figure 9 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set.

For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count.

The count can be between 1 and 32. It is not allowed to be zero or to exceed 32.

1

7

1 1

8

1

8

1 1

Wr

A

P

A

T Slave

Command

A Data Byte 0

Register # to

write

2 x 7 bit = 1

Command

starT Condition

stoP Condition

Acknowledge

Master to

Slave to

Byte Write Protocol

Figure 9. Byte Write Protocol

18

Rev. 1.1

Si53112

4.2. Block Read/Write

4.2.1. Block Read

After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The

slave acknowledges the register index in the command byte. The master sends a repeat start function. After the

slave acknowledges this, the slave sends the number of bytes it wants to transfer (>0 and <33). The master

acknowledges each byte except the last and sends a stop function.

1

7

1 1

8

1 1

7

1 1

r

Rd

Wr

A

T Slave

Command Code

A

Slave

Register # to

read

2 x 7 bit = 1

repeat starT

Acknowledge

Command

starT

Condition

Master to

Slave to

8

1

8

1

8

1 1

Data Byte

Data Byte 0

A

A Data Byte 1 N P

Not acknowledge

stoP Condition

Block Read Protocol

Figure 10. Block Read Protocol

4.2.2. Block Write

After the slave address is sent with the R/W condition bit not set, the command byte is sent with the MSB = 0. The

lower seven bits indicate the register at which to start the transfer. If the command byte is 00h, the slave device will

be compatible with existing block mode slave devices. The next byte of a write must be the count of bytes that the

master will transfer to the slave device. The byte count must be greater than zero and less than 33. Following this

byte are the data bytes to be transferred to the slave device. The slave device always acknowledges each byte

received. The transfer is terminated after the slave sends the Ack and the master sends a stop function.

1

7

1 1

8

1

A

Master to

Slave to

Wr

Command

A

T Slave Address

Register # to

write

Command bit

starT

Acknowledge

2 x 7 bit = 0

Condition

1

8

1

8

1 1

8

A Data Byte 1 A P

Byte Count = 2

Data Byte 0

A

stoP Condition

Block Write Protocol

Figure 11. Block Write Protocol

Rev. 1.1

19

Si53112

4.3. Control Registers

Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register

Description

If Bit = 0

If Bit = 1

Type

Default

Output(s)

Affected

Bit

0

100M_133M#

Frequency Select

133 MHz

100 MHz

R

Latched at

power up

DIF[11:0]

1

2

3

PLL Mode 0

PLL Mode 1

See PLL Operating Mode

Readback Table

RW

1

0

PLL Software Enable

HW Latch

SMBUS

Control

4

5

6

Reserved

0

PLL Mode 0

See PLL Operating Mode

Readback Table

R

Latched at

power up

7

PLL Mode 1

See PLL Operating Mode

Readback Table

Latched at

power up

Note: Byte 0, bit_[3:1] are BW PLL SW enable for the DB1200ZL. Setting bit 3 to 1 allows the user to override the Latch value

from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode Readback Table. Note that Bits 7 and 6

will keep the value originally latched on pin 5. A warm reset of the system will have to be accomplished if the user

changes these bits.

20

Rev. 1.1

Si53112

Table 18. Byte 1: Output Enable Control Register

Bit

0

Description

If Bit = 0

If Bit = 1

Enabled

Type

RW

Default

Output(s)

Affected

Output Enable DIF 0

Output Enable DIF 1

Output Enable DIF 2

Output Enable DIF 3

Output Enable DIF 4

Output Enable DIF 5

Output Enable DIF 6

Output Enable DIF 7

Low/Low for

Si53112

1

DIF[0]

DIF[1]

DIF[2]

DIF[3]

DIF[4]

DIF[5]

DIF[6]

DIF[7]

1

Low/Low for

Si53112

2

Low/Low for

Si53112

3

Low/Low for

Si53112

4

Low/Low for

Si53112

5

Low/Low for

Si53112

6

Low/Low for

Si53112

7

Low/Low for

Si53112

Rev. 1.1

21

Si53112

Table 19. Byte 2: Output Enable Control Register

Bit

Description

If Bit = 0

If Bit = 1

Enabled

Type

RW

Default

Output(s)

Affected

0

1

2

3

Output Enable DIF 8

Output Enable DIF 9

Output Enable DIF 10

Output Enable DIF 11

Low/Low for

Si53112

1

DIF[8]

Low/Low for

Si53112

DIF[9]

Low/Low for

Si53112

DIF[10]

DIF[11]

Low/Low for

Si53112

4

5

6

7

Reserved

0

Table 20. Byte 3: Reserved Control Register

Bit

Description

If Bit = 0

If Bit = 1

Type

Default

Output(s)

Affected

0

1

2

3

4

5

6

7

Reserved

0

22

Rev. 1.1

Si53112

Table 21. Byte 4: Reserved Control Register

Bit

Description

If Bit = 0

If Bit = 1

Type

Default

Output(s)

Affected

0

1

2

3

4

5

6

7

Reserved

0

Table 22. Byte 5: Vendor/Revision Identification Control Register

Bit

0

Description

Vendor ID Bit 0

If Bit = 0

If Bit = 1

Type

R

Default

Vendor Specific

0

1

0

1

Vendor ID Bit 1

R

2

Vendor ID Bit 2

R

3

Vendor ID Bit 3

R

4

Revision Code Bit 0

Revision Code Bit 1

Revision Code Bit 2

Revision Code Bit 3

R

5

R

6

R

7

R

Table 23. Byte 6: Device ID Control Register

Bit

0

Description

Device ID 0

If Bit = 0

If Bit = 1

Type

R

Default

0

1

Device ID 1

R

2

Device ID 2

R

3

Device ID 3

R

4

Device ID 4

R

5

Device ID 5

R

6

Device ID 6

R

7

Device ID 7 (MSB)

R

Rev. 1.1

23

Si53112

Table 24. Byte 7: Byte Count Register

Bit

Description

If Bit = 0

If Bit = 1

Type

Default

Output(s)

Affected

0

1

2

3

4

BC0 - Writing to this register con-

figures how many bytes will be

read back

RW

0

BC1 -Writing to this register con-

figures how many bytes will be

read back

RW

0

1

0

BC2 -Writing to this register con-

figures how many bytes will be

read back

BC3 -Writing to this register con-

figures how many bytes will be

read back

BC4 -Writing to this register con-

figures how many bytes will be

read back

5

6

7

Reserved

0

24

Rev. 1.1

Si53112

5. Power Filtering Example

5.1. Ferrite Bead Power Filtering

Recommended ferrite bead filtering equivalent to the following: 600  impedance at 100 MHz, < 0.1  DCR max.,

> 400 mA current rating.

Figure 12. Schematic Example of Si53112 Power Filtering

Rev. 1.1

25

Si53112

6. Pin Descriptions: 64-Pin QFN

VDDA 1

GNDA 2

NC 3

48 GND

47 DIF_7

46 DIF_7

45 OE_7 ¹

44 OE_6 ¹

43 DIF_6

42 DIF_6

41 GND

100M_133M

HBW_BYPASS_LBW

PWRGD / PWRDN

4

5

6

GND 7

VDDR 8

CLK_IN 9

CLK_IN 10

SA_0 11

SDA 12

SCL 13

Si53112

40 VDD

39 DIF_5

38 DIF_5

37 OE_5 ¹

36 OE_4 ¹

35 DIF_4

34 DIF_4

33 GND

SA_1 14

NC 15

NC 16

Notes:

1) Internal 100K pull-down

26

Rev. 1.1

Si53112

Table 25. Si53112 64-Pin QFN Descriptions

Pin #

Name

VDDA

Type

Description

3.3 V 3.3 V power supply for PLL.

1

2

3

4

GND Ground for PLL.

I/O No connect.

GNDA

NC

I,SE 3.3 V tolerant inputs for input/output frequency selection. An external pull-

100M_133M

up or pull-down resistor is attached to this pin to select the input/output

frequency.

High = 100 MHz output

Low = 133 MHz output

I, SE Tri-Level input for selecting the PLL bandwidth or bypass mode.

High = High BW mode

5

HBW_BYPASS_LBW

Med = Bypass mode

Low = Low BW mode

I

3.3 V LVTTL input to power up or power down the device.

6

7

8

PWRGD/PWRDN

GND

GND Ground for outputs.

VDD 3.3 V power supply for differential input receiver. This VDDR should be

treated as an analog power rail and filtered appropriately.

VDDR

I, DIF 0.7 V Differential input.

9

CLK_IN

SA_0

SDA

10

11

12

13

14

15

I

3.3 V LVTTL input selecting the address. Tri-level input.

I/O Open collector SMBus data.

I/O SMBus slave clock input.

SCL

I

3.3 V LVTTL input selecting the address. Tri-level input.

SA_1

NC

I/O No connect. There are active signals on pin 15 and 16, do not connect

anything to these pins.

I/O No connect. There are active signals on pin 15 and 16, do not connect

anything to these pins.

16

NC

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

17

18

19

DIF_0

OE_0

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

20

OE_1

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

GND Ground for outputs.

21

22

23

DIF_1

GND

Rev. 1.1

27

Si53112

Table 25. Si53112 64-Pin QFN Descriptions

Pin #

Name

Type

Description

3.3 V 3.3 V power supply for outputs.

24

VDD

VDD Power supply for differential outputs.

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

25

26

27

28

VDD_IO

DIF_2

OE_2

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

29

OE_3

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

VDD Power supply for differential outputs.

GND Ground for outputs.

30

31

32

33

34

35

36

DIF_3

VDD_IO

GND

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

DIF_4

OE_4

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

37

OE_5

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

3.3 V 3.3 V power supply for outputs.

38

39

40

41

42

43

44

DIF_5

VDD

GND Ground for outputs.

GND

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

DIF_6

OE_6

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

45

OE_7

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

GND Ground for outputs.

46

47

48

49

50

DIF_7

GND

VDD Power supply for differential outputs.

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

VDD_IO

DIF_8

28

Rev. 1.1

Si53112

Table 25. Si53112 64-Pin QFN Descriptions

Pin #

51

Name

DIF_8

OE_8

Type

Description

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

52

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

53

OE_9

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

VDD Power supply for differential outputs.

3.3 V 3.3 V power supply for outputs.

54

55

56

57

58

59

60

61

DIF_9

VDD_IO

VDD

GND Ground for outputs.

GND

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

DIF_10

OE_10

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).

Controls the corresponding output pair. Internal pull-down.

62

OE_11

O, DIF 0.7 V Differential clock outputs. Default is 1:1.

63

64

DIF_11

Rev. 1.1

29

Si53112

7. Ordering Guide

Part Number

Lead-free

Package Type

Temperature

Si53112-A00AGM

Si53112-A00AGMR

64-pin QFN

Extended, –40 to 85 C

64-pin QFN—Tape and Reel

30

Rev. 1.1

Si53112

8. Package Outline

Figure 13 illustrates the package details for the Si53112. Table 26 lists the values for the dimensions shown in the

illustration.

Figure 13. 64-Pin Quad Flat No Lead (QFN) Package

Table 26. Package Diagram Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

9.00 BSC.

6.10

D2

e

6.00

6.20

0.50 BSC.

9.00 BSC.

6.10

E

E2

L

6.00

0.30

6.20

0.50

0.40

aaa

bbb

ccc

ddd

eee

0.10

0.08

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Rev. 1.1

31

Si53112

9. Land Pattern

Figure 14 illustrates the recommended land pattern details for the Si53112 in a 64-pin QFN package. Table 27 lists

the values for the dimensions shown in the illustration.

Figure 14. Land Pattern

32

Rev. 1.1

Si53112

Table 27. PCB Land Pattern Dimensions

Dimension

mm

8.90

0.50

0.30

0.85

6.20

C1

C2

E

X1

Y1

X2

Y2

Notes:

General

1. All dimensions shown are in millimeters (mm).

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 m minimum, all the way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.

8. A 3x3 array of 1.45 mm square openings on a 2.00 mm pitch should be used for

the center ground pad.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Rev. 1.1

33

Si53112

DOCUMENT CHANGE LIST

Revision 0.7 to Revision 1.0

 Updated Table 25, “Si53112 64-Pin QFN Descriptions,” on page 27.

Updated pin type for pins 11 and 14.

Revision 1.0 to Revision 1.1

 Updated Features on page 1.

 Updated Description on page 1.

 Updated specs in Table 4, “Phase Jitter,” on page 6.

34

Rev. 1.1

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

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www.silabs.com/timing

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www.silabs.com/CBPro

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www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers

using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific

device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories

reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific

written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected

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型号：	SI53112-A00AGMR
厂家：	SILICON
描述：	PLL Based Clock Driver, 53112 Series, 24 True Output(s), 0 Inverted Output(s), LEAD FREE, MO-220, QFN-64 驱动逻辑集成电路
文件：	总35页 (文件大小：1447K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI53112-A00AGMR [SILICON]

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