SI53119-A03AGM [SILICON]
PLL Based Clock Driver, 53119 Series, 38 True Output(s), 0 Inverted Output(s), QFN-72;型号: | SI53119-A03AGM |
厂家: | SILICON |
描述: | PLL Based Clock Driver, 53119 Series, 38 True Output(s), 0 Inverted Output(s), QFN-72 驱动 逻辑集成电路 |
文件: | 总35页 (文件大小:1334K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si53119-A03A
19-OUTPUT PCI
E
G
EN
3
BUFFER
Features
Nineteen 0.7 V low-power, push- Integrated termination resistors
pull HCSL PCIe Gen 3 outputs supporting 85 transmission lines
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
PLL or bypass mode
Spread spectrum tolerable
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
Ordering Information:
®
Low phase jitter (Intel QPI, PCIe
9 selectable SMBUS addresses
See page 31.
Gen 1/Gen 2/Gen 3 common
clock compliant)
SMBus address configurable to
allow multiple buffers in a single
control network 3.3 V supply
voltage operation
100 ps input-to-output delay
Gen3 SRNS Compliant
Pin Assignments
Extended Temperature:
Separate VDDIO for outputs
–40 to 85 °C
DIF_12
DIF_12
VDD_IO
GND
54
53
52
51
50
49
VDDA
GNDA
1
2
72-pin QFN
100M_133M
HBW_BYPASS_LBW
PWRGD / PWRDN
GND
3
4
DIF_11
DIF_11
DIF_10
DIF_10
5
For variations of this device,
6
VDDR
7
48
47
46
45
44
43
42
41
40
39
38
37
CLK_IN
contact Silicon Labs
8
Si53119
GND
VDD
CLK_IN
9
SA_0
10
11
12
13
14
15
16
17
18
SDA
DIF_9
DIF_9
DIF_8
DIF_8
VDD_IO
SCL
SA_1
Applications
FBOUT_NC
FBOUT_NC
GND
GND
DIF_0
DIF_0
DIF_7
DIF_7
Server
Data center
Storage
Enterprise switches and routers
Description
Patents pending
The Si53119-A03A is a 19-output, low-power HCSL differential clock
buffer that meets all of the performance requirements of the Intel
DB1200ZL specification. To reduce board space and bill of material cost,
the device fully integrates all external resistors, supporting 85
transmission lines. It is optimized for distributing reference clocks for
®
Intel QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/
Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
2
133 MHz operation. Each differential output can be enabled through I C
for maximum flexibility and power savings. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it
for free at www.silabs.com/pcie-learningcenter.
Rev. 1.1 12/17
Copyright © 2017 by Silicon Laboratories
Si53119-A03A
Si53119-A03A
Functional Block Diagram
FB_OUT
SSC Compatible
PLL
DIF_[18:0]
CLK_IN
CLK_IN
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
Control
Logic
PWRGD / PWRDN
SDA
SCL
2
Rev. 1.1
Si53119-A03A
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5. Pin Descriptions: 72-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Land Pattern: 72-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.1
3
Si53119-A03A
1. Electrical Specifications
Table 1. DC Operating Characteristics
VDD_A = 3.3 V±5%, VDD = 3.3 V±5%
Parameter
Symbol
Test Condition
3.3 V ±5%
Min
3.135
0.9975
2.0
Max
3.465
3.465
VDD+0.3
0.8
Unit
V
3.3 V Core Supply Voltage
VDD/VDD_A
VDD_IO
1
3.3 V I/O Supply Voltage
1.05 V to 3.3 V ±5%
VDD
V
3.3 V Input High Voltage
3.3 V Input Low Voltage
V
V
IH
V
VSS-0.3
–5
V
IL
2
Input Leakage Current
I
0 < VIN < VDD
VDD
+5
µA
V
IL
3
3.3 V Input High Voltage
V
0.7
VDD+0.3
0.35
0.9
IH_FS
3
3.3 V Input Low Voltage
V
VSS–0.3
0
V
IL_FS
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
V
V
IL_Tri
V
1.3
1.8
V
IM_Tri
V
2.4
VDD
—
V
IH_Tri
4
3.3 V Output High Voltage
V
I
= –1 mA
= 1 mA
OL
2.4
V
OH
OH
4
3.3 V Output Low Voltage
V
I
—
0.4
V
OL
5
Input Capacitance
C
2.5
4.5
pF
pF
nH
°C
IN
5
Output Capacitance
C
2.5
4.5
OUT
Pin Inductance
Ambient Temperature
Notes:
L
—
7
PIN
T
No Airflow
0
70
A
1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3. Internal voltage reference is to be used to guarantee VIH_FS and VIL_FS threshold levels over full operating range.
4. Signal edge is required to be monotonic when transitioning through this region.
5. Ccomp capacitance based on pad metalization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.1
Si53119-A03A
Table 2. SMBus Characteristics
Parameter
Symbol
Test Condition
Min
—
Max
Unit
V
1
SMBus Input Low Voltage
V
0.8
ILSMB
IHSMB
1
SMBus Input High Voltage
V
2.1
V
V
DDSMB
1
SMBus Output Low Voltage
V
@ I
0.4
V
OLSMB
DDSMB
PULLUP
PULLUP
1
Nominal Bus Voltage
V
@ V
2.7
4
5.5
—
V
OL
1
SMBus sink Current
I
3 V to 5 V +/-10%
(Max V – 0.15) to (Min V + 0.15)
mA
ns
ns
kHz
1
SCLK/SDAT Rise Time
t
—
1000
300
—
RSMB
IL
IH
1
SCLK/SDAT Fall Time
t
(Min V + 0.15) to (Max V – 0.15)
—
FSMB
IH
IL
1,2
SMBus Operating Frequency
f
Minimum Operating Frequency
100
MINSMB
Notes:
1. Guaranteed by design and characterization
2. The differential input clock must be running for the SMBus to be active
Table 3. Current Consumption
TA = 0–70 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min
—
Typ
25
Max
35
Unit
mA
mA
Operating Current
IDD
100 MHz, VDD Rail, Zo=85
VDD
IDD
100 MHz, VDDA + VDDR, PLL Mode,
—
16
20
VDDA
Zo=85
IDD
100 MHz, CL = Full Load, VDDIO Rail,
—
130
150
mA
VDDIO
Zo=85
Power Down Current
IDD
Power Down, VDD Rail
Power Down, VDDA Rail
Power Down, VDD_IO Rail
—
—
—
1.5
8
2
mA
mA
mA
VDDPD
VDDAPD
VDDIOPD
IDD
IDD
12
0.5
0.17
Rev. 1.1
5
Si53119-A03A
Table 4. Clock Input Parameters
TA = 0–70 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input High Voltage
V
Differential Inputs
600
700
1150
mV
IHDIF
(singled-ended measurement)
Input Low Voltage
V
Differential Inputs
(singled-ended measurement)
Vss-
300
0
300
mV
mV
IHDIF
Input Common Mode
Voltage
V
Common mode input voltage
300
—
1000
com
Input Amplitude, CLK_IN
Input Slew Rate, CLK_IN
Input Duty Cycle
V
Peak to Peak Value
300
0.4
45
—
—
50
1450
8
mV
V/ns
%
swing
dv/dt
Measured differentially
Measurement from differential wave
form
55
Input Jitter–Cycle to Cycle
Input Frequency
J
Differential measurement
VDD = 3.3 V, bypass mode
—
33
90
—
—
125
150
110
147
33
ps
DFin
F
MHz
MHz
MHz
kHz
ibyp
iPLL
iPLL
F
F
VDD = 3.3 V, 100 MHz PLL Mode
VDD = 3.3 V, 133.33 MHz PLL Mode
Triangle wave modulation
100
120 133.33
30 31.5
Input SS Modulation Rate
f
MODIN
6
Rev. 1.1
Si53119-A03A
Table 5. Output Skew, PLL Bandwidth and Peaking
TA = 0–70 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Test Condition
Min
Typ
Max
Unit
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
–100
18
100
ps
1,2,3,4
Nominal Value
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
DIF[11:0]
Input-to-Output Delay in Bypass Mode
2.5
–50
–250
0
3.6
20
—
4.5
50
ns
ps
ps
ps
2,4,5
Nominal Value
Input-to-Output Delay Variation in PLL mode
2,4,5
Over Voltage and Temperature
Input-to-Output Delay Variation in Bypass Mode
250
50
2,4,5
Over Voltage and Temperature
Output-to-Output Skew across all 19 Outputs
20
1,2,3,4,5
(Common to Bypass and PLL Mode)
6
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
(HBW_BYPASS_LBW = 0)
—
—
—
—
0.4
0.1
0.7
2
2.0
2.5
1.4
4
dB
dB
6
(HBW_BYPASS_LBW = 1)
7
(HBW_BYPASS_LBW = 0)
MHz
MHz
7
PLL Bandwidth
(HBW_BYPASS_LBW = 1)
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. This parameter is deterministic for a given device.
4. Measured with scope averaging on to find mean value.
5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7. Measured at 3 dB down or half power point.
Rev. 1.1
7
Si53119-A03A
Table 6. Phase Jitter
Parameter
Test Condition
Min
Typ
Max
Unit
1,2,3
Phase Jitter
PLL Mode
PCIe Gen 1, Common Clock
—
25
86
ps
PCIe Gen 2 Low Band, Common Clock
—
—
—
—
—
—
—
2.5
2.5
3.0
3.1
1.0
0.71
0.5
0.3
0.2
ps
(RMS)
1,3,4,5
F < 1.5 MHz
PCIe Gen 2 High Band, Common Clock
ps
(RMS)
1,3,4,5
1.5 MHz < F < Nyquist
PCIe Gen 3, Common Clock
(PLL BW 2–4 MHz, CDR = 10 MHz)
0.5
ps
(RMS)
1,3,4,5
6
PCIe Gen 3 Separate Reference No Spread, SRNS
0.35
0.25
0.15
0.16
ps
(RMS)
1,3,4,5
(PLL BW of 2-4 or 2-5 MHz, CDR = 10 MHz)
®
Intel QPI & Intel SMI
ps
(RMS)
1,7,8
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)
Intel QPI & Intel SMI
(8 Gb/s, 100 MHz, 12 UI)
ps
(RMS)
1,7
Intel QPI & Intel SMI
(9.6 Gb/s, 100 MHz, 12 UI)
ps
(RMS)
1,7
Notes:
1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2. ζ = 0.54 implies a jitter peaking of 3 dB.
3. PCIe* Gen 3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
7. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
8. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
9. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.9.
8
Rev. 1.1
Si53119-A03A
Table 6. Phase Jitter (Continued)
1,2,3
Additive Phase Jitter
Bypass Mode
PCIe Gen 1
—
—
10
—
—
ps
PCIe Gen 2 Low Band
1.0
ps
(RMS)
1,3,4,5
F < 1.5 MHz
PCIe Gen 2 High Band
1.5 MHz < F < Nyquist
—
—
—
1.0
0.3
0.3
—
—
—
ps
(RMS)
1,3,4,5
PCIe Gen 3
(PLL BW 2–4 MHz, CDR = 10 MHz)
ps
(RMS)
1,3,4,5
PCIe Gen 4, Common Clock
ps
(PLL BW of 2–4 or 2–5 MHz, CDR = 10
(RMS)
1,3,4,5,6,9
MHz)
Intel QPI & Intel® SMI
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)
—
—
—
0.15
0.1
—
—
—
ps
(RMS)
1,7,8
Intel QPI & Intel® SMI
(8 Gb/s, 100 MHz, 12 UI)
ps
(RMS)
1,7
Intel QPI & Intel® SMI
(9.6 Gb/s, 100 MHz, 12 UI)
0.1
ps
(RMS)
1,7
Notes:
1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2. ζ = 0.54 implies a jitter peaking of 3 dB.
3. PCIe* Gen 3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
7. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
8. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
9. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.9.
Rev. 1.1
9
Si53119-A03A
Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Min
Typ
1.5
—
Max
2
Clock Stabilization Time
T
—
—
1.8
100
ms
ppm
ns
STAB
3,4,5
Long Term Accuracy
L
ACC
3,4,6
3,4,6
Absolute Host CLK Period (100 MHz)
Absolute Host CLK Period (133 MHz)
T
9.94900
7.44925
1.0
—
10.05100
7.55075
4.0
ABS
T
—
ns
ABS
3,4,7
Slew Rate
Edge_rate
∆ Trise
3.0
—
V/ns
ps
3,8,9
Rise Time Variation
—
125
3,8,9
Fall Time Variation
∆ Tfall
—
—
125
ps
3,8,10,11
Rise/Fall Matching
T
/
—
7
20
%
RISE_MAT
T
FALL_MAT
3,8,12
Voltage High (typ 0.7 V)
V
660
750
850
mV
HIGH
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3. Test configuration is 2 pF for 85 transmission line.
4. Measurement taken from differential waveform.
5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum
specified period.
7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from
–150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making
most of the dynamic wiggles along the clock edge. Only valid for Rising clock and Falling CLOCK. Signal must be
monotonic through the Vol to Voh region for Trise and Tfall.
8. Measurement taken from single-ended waveform.
9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10. Measured with oscilloscope, averaging on. The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of CLOCK.
11. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figures 3–4 for further clarification).
18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19. Overshoot is defined as the absolute value of the maximum voltage.
20. Undershoot is defined as the absolute value of the minimum voltage.
10
Rev. 1.1
Si53119-A03A
Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 (Continued)
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Min
Typ
15
Max
3,8,13
Voltage Low (Typ 0.7 V)
V
–150
—
150
1150
—
mV
mV
mV
mV
mV
LOW
8
Maximum Voltage
Minimum Voltage
V
850
—
MAX
V
–300
300
—
MIN
3,8,14,15,16
Absolute Crossing Point Voltages
Vox
450
14
550
140
ABS
3,8,18
Total Variation of Vcross Over All Edges
Total ∆
Vox
3,4
Duty Cycle
DC
45
—
—
—
—
—
55
%
V
V
V
3,8,19
Maximum Voltage (Overshoot)
V
V
+ 0.3
High
ovs
3,8,20
Maximum Voltage (Undershoot)
V
—
V
– 0.3
Low
uds
3,8
Ringback Voltage
V
0.2
N/A
rb
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3. Test configuration is 2 pF for 85 transmission line.
4. Measurement taken from differential waveform.
5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum
specified period.
7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from
–150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making
most of the dynamic wiggles along the clock edge. Only valid for Rising clock and Falling CLOCK. Signal must be
monotonic through the Vol to Voh region for Trise and Tfall.
8. Measurement taken from single-ended waveform.
9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10. Measured with oscilloscope, averaging on. The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of CLOCK.
11. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figures 3–4 for further clarification).
18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19. Overshoot is defined as the absolute value of the maximum voltage.
20. Undershoot is defined as the absolute value of the minimum voltage.
Rev. 1.1
11
Si53119-A03A
Table 8. Clock Periods Differential Clock Outputs with SSC Disabled
SSC OFF
Measurement Window
Unit
Center
Freq, MHz
1 Clock
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
–C-C
Jitter
–SSC
Short
–ppm
Long
0 ppm
Period
+ppm
Long
+SSC
Short
+C-C
Jitter
AbsPer
Max
Term AVG Nominal Term AVG Term AVG
AbsPer Term AVG
Min
Min
Max
Max
Min
100.00
133.33
9.94900
7.44925
9.99900
7.49925
10.00000 10.00100
10.05100
7.55075
ns
ns
7.50000
7.50075
Table 9. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Measurement Window
Unit
Center
Freq, MHz
1 Clock
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
–C-C
Jitter
–SSC
Short
–ppm
Long
0 ppm
Period
+ppm
Long
+SSC
Short
+C-C
Jitter
AbsPer
Max
Term AVG Nominal Term AVG Term AVG
AbsPer Term AVG
Min
Min
Max
Max
Min
99.75
9.94906
7.44930
9.99906
7.49930
10.02406 10.02506 10.02607 10.05107 10.10107
ns
ns
133.33
7.51805
7.51880
7.51955
7.53830
7.58830
Table 10. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
4.6
4.6
4.6
—
Unit
1
3.3 V Core Supply Voltage
VDD/VDD_A
VDD_IO
VIH
—
—
V
V
1
3.3 V I/O Supply Voltage
1,2
3.3 V Input High Voltage
—
V
1
3.3 V Input Low Voltage
VIL
−0.5
–65
2000
V
1
Storage Temperature
t
150
—
°C
V
s
3
Input ESD protection
ESD
Notes:
1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.
2. Maximum VIH is not to exceed maximum VDD
.
3. Human body model.
12
Rev. 1.1
Si53119-A03A
2. Functional Description
2.1. CLK_IN, CLK_IN
The differential input clock is expected to be sourced from a clock synthesizer or PCH.
2.2. 100M_133M—Frequency Selection
The Si53119-A03A is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.
100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.
Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53119-A03A is operated in
1:1 mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-
down resistor is attached to this pin to select the input/output frequency. The functionality is summarized in
Table 11.
Table 11. Frequency Program Table
100M_133M
Optimized Frequency (DIF_IN = DIF_x)
133.33 MHz
0
1
100.00 MHz
Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner.
2.3. SA_0, SA_1—Address Selection
SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53119-A03A. The two
tri-level input pins that can configure the device to nine different addresses.
Table 12. SMBUS Address Table
SA_1
L
SA_0
L
SMBUS Address
D8
DA
DE
C2
C4
C6
CA
CC
CE
L
M
H
L
M
M
M
H
L
M
H
L
H
M
H
H
Rev. 1.1
13
Si53119-A03A
2.4. CKPWRGD/PWRDN
CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to
indicating a power down condition. CKPWRGD (assertion) is used by the Si53119-A03A to sample initial
configurations, such as frequency select condition and SA selections. After CKPWRGD has been asserted high for
the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and
instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When
entering power-saving mode, PWRDN should be asserted low prior to shutting off the input clock or power to
ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior
to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal
behavior and will meet all ac and dc parameters.
Note: The assertion and deassertion of PWRDN is absolutely asynchronous.
Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended. Oper-
ation in this mode may result in glitches, excessive frequency shifting, etc.
Table 13. CKPWRGD/PWRDN Functionality
CKPWRGD/
PWRDN
DIF_IN/
SMBus
EN bit
DIF-x/
FBOUT_NC/
FBOUT_NC#
PLL State
DINF_IN#
DIF_x#
0
1
X
X
0
1
Low/Low
Low/Low
Running
Low/Low
Running
Running
OFF
ON
Running
ON
2.4.1. PWRDN Assertion
When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/
LOW on the next DIF high-to-low transition.
PWRDWN
DIF
DIF
Figure 1. PWRDN Assertion
14
Rev. 1.1
Si53119-A03A
2.4.2. CKPWRGD Assertion
The powerup latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion of
the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs
stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN
deassertion to a voltage greater than 200 mV.
Tstable
<1.8 ms
PWRGD
DIF
DIF
Tdrive_Pwrdn#
<300 µs; > 200 mV
Figure 2. PWRDG Assertion (Pwrdown—Deassertion)
2.5. HBW_BYPASS_LBW
The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 1 for VIL_Tri, VIM_Tri, and VIH_Tri
signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In
PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive
cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In PLL mode, the input clock is passed through a
PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be selected by asserting
the HBW_BYPASS_LBW input pin to the appropriate level described in Table 14.
Table 14. PLL Bandwidth and Readback Table
HBW_BYPASS_LBW Pin
Mode
LBW
Byte 0, Bit 7
Byte 0, Bit 6
L
M
H
0
0
1
0
1
1
BYPASS
HBW
The Si53119-A03A has the ability to override the latch value of the PLL operating mode from hardware strap pin 5
via the use of Byte 18 and bits 1 and 0. Byte 18 bit 2 must be set to 1 to allow the user to change Bits 1 and 0,
affecting the PLL. Byte0, Bits 7 and 6 will always read back the original latched value from hardware strap pin5. A
warm reset of the external system will have to be accomplished if the user changes these bits.
Rev. 1.1
15
Si53119-A03A
2.6. Miscellaneous Requirements
Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps)
functionality is optional.
Logic Levels: SMBus logic levels are based on a percentage of V
for the controller and other devices on the
DD
bus. Assume all devices are based on a 3.3 V supply.
Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock
stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than
this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all
data transfers can be completed as specified without the use of clock/data stretching.
General Call: It is assumed that the clock buffer will not have to respond to the “general call.”
Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in
Section 3 of the SMBus 2.0 specification.
Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual
data sheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board
designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k range.
Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock
driver plus one/two more SMBus devices on the platform for capacitive loading purposes.
Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock
buffer is specified as a standard mode device and is not required to support this feature. However, it is considered
a good design practice to include the filters.
PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the
device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and
in the data sheet.
16
Rev. 1.1
Si53119-A03A
3. Test and Measurement Setup
3.1. Input Edge
Input edge rate is based on single-ended measurement. This is the minimum input edge rate at which the Si53119-
A03A is guaranteed to meet all performance specifications.
Table 15. Input Edge Rate
Frequency
100 MHz
133 MHz
Min
0.35
0.35
Max
N/A
N/A
Unit
V/ns
V/ns
3.1.1. Measurement Points for Differential
Slew_fall
Slew_rise
+150 mV
+150 mV
-150 mV
0.0 V
V_swing
0.0 V
-150 mV
Diff
Figure 3. Measurement Points for Rise Time and Fall Time
Vovs
VHigh
Vrb
Vrb
VLow
Vuds
Figure 4. Single-Ended Measurement Points for Vovs, Vuds, Vrb
Rev. 1.1
17
Si53119-A03A
TPeriod
Low Duty Cycle %
High Duty Cycle %
Skew measurement
point
0.000 V
Figure 5. Differential (CLOCK–CLOCK) Measurement Points (Tperiod, Duty Cycle, Jitter)
3.2. Termination of Differential Outputs
All differential outputs are to be tested into an 85 differential impedance transmission line. All output termination
resistors are fully integrated into the Si53119-A03A, no external components are required. Contact Silicon Labs if
100 differential impedance support is needed.
Clock
Receiver
Z0 = 85ohm, 10" Trace
2 pF
2 pF
Clock #
Z0 = 85ohm, 10" Trace
Figure 6. 0.7 V Configuration Test Load Board Termination for NMOS Push-Pull
18
Rev. 1.1
Si53119-A03A
4. Control Registers
4.1. Byte Read/Write
Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register
number.
4.1.1. Byte Read
The standard byte read is as shown in Figure 7. It is an extension of the byte write. The write start condition is
repeated; then, the slave device starts sending data, and the master acknowledges it until the last byte is sent. The
master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the
command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte
must be the byte transfer count.
1
7
1 1
8
1 1
7
1 1
8
1 1
r
Rd
Data Byte 0
Wr
A
A
N
P
T Slave
Command
A
Slave
Register # to
read
2 x 7 bit = 1
Not ack
Command
starT
Condition
Byte Read Protocol
repeat starT
Acknowledge
stoP
Condition
Master to
Slave to
Figure 7. Byte Read Protocol
4.1.2. Byte Write
Figure 8 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set.
For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count.
The count can be between 1 and 32. It is not allowed to be zero or to exceed 32.
1
7
1 1
8
1
8
1 1
Wr
A
P
A
T Slave
Command
A Data Byte 0
Register # to
write
2 x 7 bit = 1
Command
starT Condition
stoP Condition
Acknowledge
Master to
Slave to
Byte Write Protocol
Figure 8. Byte Write Protocol
Rev. 1.1
19
Si53119-A03A
4.2. Block Read/Write
4.2.1. Block Read
After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The
slave acknowledges the register index in the command byte. The master sends a repeat start function. After the
slave acknowledges this, the slave sends the number of bytes it wants to transfer (>0 and <33). The master
acknowledges each byte except the last and sends a stop function.
1
7
1 1
8
1 1
7
1 1
r
Rd
Wr
A
A
T Slave
Command Code
A
Slave
Register # to
read
2 x 7 bit = 1
repeat starT
Acknowledge
Command
starT
Condition
Master to
Slave to
8
1
8
1
8
1 1
Data Byte
Data Byte 0
A
A Data Byte 1 N P
Not acknowledge
stoP Condition
Block Read Protocol
Figure 9. Block Read Protocol
4.2.2. Block Write
After the slave address is sent with the R/W condition bit not set, the command byte is sent with the MSB = 0. The
lower seven bits indicate the register at which to start the transfer. If the command byte is 00h, the slave device will
be compatible with existing block mode slave devices. The next byte of a write must be the count of bytes that the
master will transfer to the slave device. The byte count must be greater than zero and less than 33. Following this
byte are the data bytes to be transferred to the slave device. The slave device always acknowledges each byte
received. The transfer is terminated after the slave sends the ACK and the master sends a stop function.
1
7
1 1
8
1
A
Master to
Slave to
Wr
Command
A
T Slave Address
Register # to
write
Command bit
starT
Acknowledge
2 x 7 bit = 0
Condition
1
8
1
8
1 1
8
A Data Byte 1 A P
Byte Count = 2
Data Byte 0
A
stoP Condition
Block Write Protocol
Figure 10. Block Write Protocol
20
Rev. 1.1
Si53119-A03A
4.3. Control Registers
Table 16. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register
Output(s)
Affected
Description
If Bit = 0
If Bit = 1
Type
Default
Bit
100M_133M#
Frequency Select
Latched at
power up
0
133 MHz
100 MHz
R
DIF[18:0]
1
2
3
4
5
Reserved
Reserved
Low/Low
Low/Low
Low/Low
0
0
1
1
1
Output Enable DIF 16
Output Enable DIF 17
Output Enable DIF 18
Enable
Enable
Enable
RW
RW
RW
DIF_16
DIF_17
DIF_18
See PLL Operating Mode
Readback Table
Latched at
power up
6
7
PLL Mode 0
PLL Mode 1
R
R
See PLL Operating Mode
Readback Table
Latched at
power up
Table 17. Byte 1: Output Enable Control Register
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
1
2
3
4
5
6
7
Output Enable DIF 0
Output Enable DIF 1
Output Enable DIF 2
Output Enable DIF 3
Output Enable DIF 4
Output Enable DIF 5
Output Enable DIF 6
Output Enable DIF 7
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
DIF[0]
DIF[1]
DIF[2]
DIF[3]
DIF[4]
DIF[5]
DIF[6]
DIF[7]
Rev. 1.1
21
Si53119-A03A
Table 18. Byte 2: Output Enable Control Register
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
1
2
3
4
5
6
7
Output Enable DIF 8
Output Enable DIF 9
Output Enable DIF 10
Output Enable DIF 11
Output Enable DIF 12
Output Enable DIF 13
Output Enable DIF 14
Output Enable DIF 15
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
DIF[8]
DIF[9]
DIF[10]
DIF[11]
DIF[112
DIF[14]
DIF[15]
DIF[16
Table 19. Byte 3: Reserved Control Register
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
1
2
3
4
5
6
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
22
Rev. 1.1
Si53119-A03A
Table 20. Byte 4: Reserved Control Register
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
1
2
3
4
5
6
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Table 21. Byte 5: Vendor/Revision Identification Control Register
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
1
2
3
4
5
6
7
Vendor ID Bit 0
Vendor ID Bit 1
R
R
R
R
R
R
R
R
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
0
0
0
1
0
0
0
0
Vendor ID Bit 2
Vendor ID Bit 3
Revision Code Bit 0
Revision Code Bit 1
Revision Code Bit 2
Revision Code Bit 3
Rev. 1.1
23
Si53119-A03A
Table 22. Byte 6: Device ID Control Register
Default =
01110111
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
0
1
2
3
4
5
6
7
Device ID 0
Device ID 1
R
R
R
R
R
R
R
R
1
1
1
0
1
1
1
0
Device ID 2
Device ID 3
Device ID 4
Device ID 5
Device ID 6
Device ID 7 (MSB)
24
Rev. 1.1
Si53119-A03A
Table 23. Byte 7: Byte Count Register
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
BC0—Writing to this register config-
ures how many bytes will be read
back
0
RW
RW
RW
RW
RW
0
BC1—Writing to this register config-
ures how many bytes will be read
back
1
2
3
4
0
0
1
0
BC2—Writing to this register config-
ures how many bytes will be read
back
BC3—Writing to this register config-
ures how many bytes will be read
back
BC4—Writing to this register config-
ures how many bytes will be read
back
5
6
7
Reserved
Reserved
Reserved
0
0
0
Table 24. Byte 18: PLL Mode Control Register
Outputs
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
If Byte0[3] = 1 allows the user to over-
ride the latch from pin5 via use of
Byte0[2:1]
0
PLL_MODE0
R/W
0
00 = Low Bandwidth Mode
01 = Bypass Mode
11 = High Bandwidth Mode
1
PLL_MODE1
R/W
R/W
0
2
2
3
4
5
6
7
PLL_SW_EN
Reserved
Reserved
Reserved
Reserved
Reserved
HW Select
I C Select
0
0
0
0
0
0
Rev. 1.1
25
Si53119-A03A
5. Pin Descriptions: 72-Pin QFN
DIF_12
DIF_12
VDD_IO
GND
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VDDA
GNDA
1
2
100M_133M1
3
3
HBW_BYPASS_LBW
4
DIF_11
DIF_11
DIF_10
DIF_10
PWRGD / PWRDN
GND
5
6
VDDR
7
CLK_IN
CLK_IN
SA_01
8
Si53119
GND
VDD
9
10
11
12
13
14
15
16
17
18
SDA
DIF_9
DIF_9
DIF_8
DIF_8
VDD_IO
SCL
SA_11
FBOUT_NC
FBOUT_NC
GND
GND
DIF_0
DIF_0
DIF_7
DIF_7
Note1: Internal Pullup
Note2: Internal Pulldown
Note3: Internal Pullup/pulldown (biased to Vdd/2)
26
Rev. 1.1
Si53119-A03A
Table 25. Si53119-A03A 72-Pin QFN Descriptions
Pin #
Name
VDDA
Type
Description
3.3 V
3.3 V power supply for PLL.
Ground for PLL.
1
2
3
GND
I,SE
GNDA
3.3 V tolerant inputs for input/output frequency selection. An external
pull-up or pull-down resistor is attached to this pin to select the input/
output frequency. Internal pullup.
100M_133M
High = 100 MHz output
Low = 133 MHz output
I, SE
Tri-Level input for selecting the PLL bandwidth or bypass mode.
High = High BW mode
4
HBW_BYPASS_LBW
Med = Bypass mode
Low = Low BW mode
I
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
5
6
7
PWRGD/PWRDN
GND
GND
VDD
3.3 V power supply for differential input receiver. This VDDR should
be treated as an analog power rail and filtered appropriately.
VDDR
I, DIF
I, DIF
I,PU
0.7 V Differential input.
0.7 V Differential input.
8
9
CLK_IN
CLK_IN
SA_0
3.3 V LVTTL input selecting the address. Tri-level input. Internal
pullup.
10
I/O
I/O
Open collector SMBus data.
SMBus slave clock input.
11
12
13
SDA
SCL
I,PU
3.3 V LVTTL input selecting the address. Tri-level input. Internal
pullup.
SA_1
I/O
Complementary differential feedback output. Do not connect this pin
to anything.
14
FBOUT / NC
I/O
True differential feedback output. Do not connect this pin to anything.
Ground for outputs.
15
16
17
18
19
20
21
22
23
24
FBOUT / NC
GND
GND
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_0
DIF_0
DIF_1
DIF_1
VDD
GND
Power supply for differential outputs.
Ground for outputs.
VDD_IO
GND
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_2
DIF_2
Rev. 1.1
27
Si53119-A03A
Table 25. Si53119-A03A 72-Pin QFN Descriptions (Continued)
Pin #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Name
DIF_3
DIF_3
GND
Type
Description
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
GND
3.3 V
Ground for outputs.
3.3 V power supply for outputs.
VDD
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_4
DIF_4
DIF_5
DIF_5
VDD_IO
GND
VDD
GND
Power supply for differential outputs.
Ground for outputs.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_6
DIF_6
DIF_7
DIF_7
GND
GND
VDD
Ground for outputs.
Power supply for differential outputs.
VDD_IO
DIF_8
DIF_8
DIF_9
DIF_9
VDD
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
3.3 V
GND
3.3 V power supply for outputs.
Ground for outputs.
GND
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_10
DIF_10
DIF_11
DIF_11
GND
GND
VDD
Ground for outputs.
Power supply for differential outputs.
VDD_IO
DIF_12
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
28
Rev. 1.1
Si53119-A03A
Table 25. Si53119-A03A 72-Pin QFN Descriptions (Continued)
Pin #
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Name
DIF_12
DIF_13
DIF_13
VDD_IO
GND
Type
Description
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
VDD
GND
Power supply for differential outputs.
Ground for outputs.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_14
DIF_14
DIF_15
DIF_15
GND
GND
3.3 V
Ground for outputs.
3.3 V power supply for outputs.
VDD
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_16
DIF_16
DIF_17
DIF_17
VDD_IO
GND
VDD
GND
Power supply for differential outputs.
Ground for outputs.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
DIF_18
DIF_18
GND
GND
Ground for outputs.
Rev. 1.1
29
Si53119-A03A
6. Power Filtering Example
6.1. Ferrite Bead Power Filtering
Recommended ferrite bead filtering equivalent to the following: 600 impedance at 100 MHz, < 0.1 DCR max.,
> 400 mA current rating.
Figure 11. Schematic Example of the Si53119-A03A Power Filtering
30
Rev. 1.1
Si53119-A03A
7. Ordering Guide
Part Number
Lead-free
Package Type
Temperature
Si53119-A03AGM
Si53119-A03AGMR
72-pin QFN
Extended, –40 to 85 C
Extended, –40 to 85 C
72-pin QFN—Tape and Reel
Rev. 1.1
31
Si53119-A03A
8. Package Outline
Figure 12 illustrates the package details for the Si53119-A03A. Table 26 lists the values for the dimensions shown
in the illustration.
Figure 12. 72-Pin Quad Flat No Lead (QFN) Package
Table 26. Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Dimension
Min
5.90
0.30
Nom
6.00
0.40
0.10
0.10
0.08
0.10
0.05
Max
6.10
0.50
A
E2
L
A1
0.02
b
0.25
aaa
bbb
ccc
ddd
eee
D
10.00 BSC.
6.00
D2
5.90
6.10
e
E
0.50 BSC.
10.00 BSC.
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
32
Rev. 1.1
Si53119-A03A
9. Land Pattern: 72-pin QFN
Figure 13 shows the recommended land pattern details for the Si53119-A03A in a 72-pin QFN package. Table 27
lists the values for the dimensions shown in the illustration.
Figure 13. 72-pin QFN Land Pattern
Table 27. PCB Land Pattern Dimensions
Dimension
mm
9.90
9.90
0.50
0.30
0.85
6.10
6.10
C1
C2
E
X1
Y1
X2
Y2
Rev. 1.1
33
Si53119-A03A
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Updated " Functional Block Diagram" on page 2.
Updated "2.5. HBW_BYPASS_LBW" on page 15.
Updated "4.3. Control Registers" on page 21.
Updated Default settings in Table 22, “Byte 6: Device ID
Control Register,” on page 24.
34
Rev. 1.1
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