DSP56F805PB [ETC]
56F805 16-Bit Hybrid Controller Product Brief ; 56F805 16位混合控制器产品简介\n
| 型号： | DSP56F805PB |
| 厂家： | 
ETC |
| 描述： | 56F805 16-Bit Hybrid Controller Product Brief
|
| 文件： | 总2页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
HYBRID FLASH SOLUTION
56F805
16-bit Hybrid Controller
TARGET APPLICATIONS
BENEFITS
• Regenerative drives
• ID tag readers
• Winders/pullers
• On-board voltage regulator and power
management is designed to reduce
overall system cost by allowing for a
single supply voltage
• Supports multiple processor
connections
• Glass breakage detection
• Critical reliability drives
• Cable test equipment
• HVAC
• Remote monitoring
• Automotive control
• General purpose devices
• Switched-mode power supplies
• Patented distortion correction in PWM
for reducing design risk and better
performance control
• Flash memory is engineered to provide
reliable, non-volatile memory storage,
eliminating the need for external
storage devices
• PWM and ADC modules are tightly
coupled to reduce processing overhead
• Low voltage interrupts protect the
system during brownout or power
failure
• Easy to program with flexible
application development tools
• Simple updating of Flash memory
through SPI, SCI or OnCE™, using
on-chip boot loader
• Simple interface with other
asynchronous serial communication
devices and off-chip EE memory
• Program can boot directly from Flash
The 56F805 is a member of the 56800 core-based
family of Hybrid Controllers. It combines, on a single
chip, the processing power of a DSP and the
56F805 16-BIT HYBRID CONTROLLER
• Up to 40 MIPS at 80MHz core frequency • Up to 64K each of external program and
functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective
solution. Because of its low cost, configuration
flexibility, and compact program code, the 56F805 is
well-suited for many applications. The 56800 core is
based on a Harvard-style architecture consisting of
three execution units operating in parallel, allowing
as many as six operations per instruction cycle. The
microprocessor-style programming model and
optimized instruction set allow straightforward
generation of efficient, compact code for both DSP
and MCU applications. The instruction set is also
highly efficient for C compilers to enable rapid
development of optimized control applications.
data memory
• DSP and MCU functionality in a unified,
C-efficient architecture
• Two 6-channel PWM modules
• Two 4-channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 A/B module
• Hardware DO and REP loops
• MCU-friendly instruction set supports
both DSP and controller functions: MAC,
bit manipulation unit, 14 addressing
modes
• Two Serial Communication Interfaces
(SCIs)
• 38K On-chip Flash
- 32K Program Flash
- 4K Data Flash
• Serial Peripheral Interface (SPI)
• Four general purpose Quad Timers
• JTAG/OnCE port for debugging
• 14 dedicated and 18 shared GPIO lines
• 144-pin LQFP Package
- 2K Boot Flash
• 512 Program RAM
• 2K Data RAM
ENERGY INFORMATION
Program Memory
COP/Watchdog
Ext Memory I/F
• Fabricated in high-density CMOS with
5V-tolerant, TTL-compatible digital inputs
• On-chip regulators for digital and analog
circuitry to lower cost and reduce noise
512 RAM
32K Flash
• Uses a single 3.3V power supply
• Wait and Stop modes available
SPI
2K Boot Flash
(2) SCI
Up to 32 GPIO
(4) 16-Bit
Quad Timers
56800 Core
CAN 2.0 A/B
40 MIPS
Dual 4-Channel
ADC, 12-Bit
(2) 4-Channel
Quad Decoder
Data Memory
Power Mgmt
PLL
(2) 6-Channel
PWM
2K RAM
4K Flash
JTAG/OnCE
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
56800 CORE FEATURES
HYBRID FLASH SOLUTION
• Efficient 16-bit 56800 family hybrid
controller engine with dual Harvard
architecture
• Four internal data buses and one
external data bus
56F805
• Instruction set supports both DSP and
controller functions
• As many as 40 Million Instructions Per
Second (MIPS) at 80MHz core frequency
PRODUCT DOCUMENTATION
• Controller-style addressing modes and
instructions for compact code
• Single-cycle 16 x 16-bit parallel
Multiplier-Accumulator (MAC)
DSP56800
Family Manual
Detailed description of the 56800
family architecture, and 16-bit DSP core
processor and the instruction set
• Efficient C compiler and local variable
support
• Two 36-bit accumulators, including
extension bits
Order Number: DSP56800FM/D
• Software subroutine and interrupt stack
with depth limited only by memory
• 16-bit bidirectional barrel shifter
DSP56F80x
User’s Manual
Detailed description of memory,
peripherals, and interfaces of the
56F801, 56F802, 56F803,
• Parallel instruction set with unique
addressing modes
• JTAG/OnCE debug programming
interface
56F805, and 56F807
• Hardware DO and REP loops
Order Number: DSP56F801-07UM/D
• Three internal address buses and one
external address bus
DSP56F805
Technical Data
Sheet
Electrical and timing specifications,
pin descriptions, and package
descriptions
56F805 MEMORY FEATURES
• Harvard architecture permits as many as • Off-chip memory expansion capabilities
three simultaneous accesses to program
and data memory
Order Number: DSP56F805/D
– As much as 64K data memory
DSP56F805
Product Brief
Summary description and block diagram
of the core, memory,
peripherals and interfaces
– As much as 64K program memory
• On-chip memory including a low-cost,
high-volume Flash solution
Order Number: DSP56F805PB/D
- 38K On-chip Flash
- 32K Program Flash
- 4K Data Flash
AWARD-WINNING
- 2K Boot Flash
DEVELOPMENT ENVIRONMENT
- 512 Program RAM
- 2K Data RAM
• Processor Expert™ (PE) technology provides a rapid
application design (RAD) tool that combines easy-to-use
component-based software application creation with an
expert knowledge system.
56F805 PERIPHERAL CIRCUIT FEATURES
• Two Pulse Width Modulator modules
each with six PWM outputs, three
Current Sense inputs, and four Fault
inputs, fault-tolerant design with
dead-time insertion; supports both
center- and edge- aligned modes
• CAN 2.0 A/B module
• The CodeWarrior™ Integrated Development Environment
(IDE) is a sophisticated tool for code navigation, compiling
and debugging. A comprehensive set of evaluation modules
(EVMs) and development system cards will support
concurrent engineering. Together, PE, the CodeWarrior tool
suite and EVMs create a comprehensive, scalable tools
solution for easy, fast and efficient development.
• Serial Peripheral Interface (SPI)
• 14 dedicated General Purpose I/O (GPIO)
pins, 18 multiplexed GPIO pins
• Computer Operating Properly (COP)/
Watchdog timer
• Two 12-bit Analog-to-Digital Converters
(ADC) which support two simultaneous
conversions; ADC and PWM modules
can be synchronized
• Two dedicated external interrupt pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• JTAG/OnCE™ module for unobtrusive,
processor speed-independent debugging
• Two Quadrature Decoders
• Four general purpose Quad Timers
• Two Serial Communication Interfaces
(SCI)
• Software-programmable, Phase Lock
Loop-based frequency synthesizer
ORDERING INFORMATION
PART
SUPPLY
VOLTAGE
PACKAGE TYPE
PIN COUNT
FREQUENCY
(MHz)
ORDER NUMBER
DSP56F805
DSP56F805
3.0–3.6V
3.0–3.6V
Low-profile Quad Flat Pack (LQFP)
Low-profile Quad Flat Pack (LQFP)
144
144
80
80
DSP56F805FV80
SPAK56F805FV80
Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This
product incorporates SuperFlash® technology licensed from SST. All other product or service
names are the property of their respective owners. © Motorola, Inc. 2003
DSP56F805PB/D
For More Information On This Product,
REV 6
Go to: www.freescale.com
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