CXD3423GA [ETC]
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor; 时序发生器和信号处理器的帧读出CCD图像传感器
| 型号： | CXD3423GA |
| 厂家： | 
ETC |
| 描述： | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| 文件： | 总54页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD3423GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
96 pin LFLGA (Plastic)
The CXD3423GA is a timing generator and CCD
signal processor IC for the ICX284, ICX432/434
CCD image sensor.
Features
• Timing generator functions
• Horizontal drive frequency 18 to 24.3MHz
(Base oscillation frequency 36 to 48.6MHz)
• Supports frame readout/draft (sextuple speed)/
AF (Auto focus drive) (ICX432 mode)
• Supports frame readout/draft (quadruple speed)/
AF (Auto focus drive) (ICX434 mode)
• High-speed/low-speed shutter function
• Horizontal and vertical drivers for CCD image
sensor
Absolute Maximum Ratings
• Supply voltage
VDDa, VDDb, VDDc, VDDd VSS – 0.3 to +7.0
V
V
V
V
VDDe, VDDf, VDDg
VSS – 0.3 to +4.0
–10.0 to VSS
VL
VH
VL – 0.3 to +26.0
• Input voltage (analog)
• CCD signal processor functions
• Correlated double sampling
VIN
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
V
V
• Input voltage (digital)
• Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
• 12-bit A/D converter
VI
• Output voltage
VO1
VSS – 0.3 to VDD + 0.3
VL – 0.3 to VSS + 0.3
VL – 0.3 to VH + 0.3
V
V
V
• Chip Scale Package (CSP):
VO2
CSP allows vast reduction in the CCD camera
block footprint
VO3
• Operating temperature
Topr
–20 to +75
°C
°C
Applications
• Storage temperature
Tstg
Digital still cameras
–55 to +125
Applicable CCD Image Sensors
ICX284 (Type 1/2.7, 2020K pixels)
ICX432 (Type 1/2.7, 3240K pixels)
ICX434 (Type 1/3.2, 2020K pixels)
Recommended Operating Conditions
• Supply voltage
VDDa, VDDb, VDDc, VDDd,
VDDe, VDDf, VDDg
3.0 to 3.6
0.0
V
V
V
V
VM
VH
14.5 to 15.5
–7.0 to –8.0
VL
• Operating temperature
Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E02301A2X-PS
CXD3423GA
Block Diagram
C7 D8 D7
B8 B6 B9 A6 C5
A3 A4 B4 A5 C4 B5
E2 F2 F3 E3 F1
C4
AVDD5
AVSS6
C7
C8
A9
A8
B7
A7
C6
C9
E9
E8
D9
E7
F9
F8
F7
G9
G8
G7
A2 D0 (LSB)
Serial Port
Register
DAC
A1
B3
D1
D2
B2 D3
B1 D4
C8
C9
C3
C2
C1
D3
D2
D5
D6
D7
CDS
ADC
CCDIN
AVDD1
AVDD2
AVSS1
PGA
Latch
D8
D9
AVSS2
XSHPI
D1 D10
E1
D11 (MSB)
ADCLKI
Dummy Pixel
Black Level
Auto Zero
XSHDI
PBLKI
XSHP
XSHD
PBLK
Preblanking
G1
G2
G3
Auto Zero
CLPOBI
CLPDMI
ADCLK
CLPOB
CLPDM
H1
H2
H3
V
DD4
DD2
RG
H8
K7
K8
K9
H9
V
V
SS4
J3
OSCI
OSCO
CKI
L1
K1
J1
V
SS2
V
DD3
H1
H2
Pulse Generator
J8
J9
CKO
J2
MCKO
K2
V
SS3
J7
1/2
Selector
ID/EXP
N9
M9
SNCSL
N8
Latch
WEN/FLD
SSI1
L2
M1
N1
Serial Port
Register
SCK1
SEN1
VH
VM
VL
L5
M3
M6
V Driver
Selector
N2 M2
SSGSL
SSG
L8
H7 L3 M8 L4 M5 N5 M4 L6 N6 N4 N7 M7
L9 K3 L7 N3
– 2 –
CXD3423GA
Pin Configuration (Top View)
A
B
C
D
E
F
D1
D4
D0
D3
SCK2
D2
SSI2
SEN2
TEST4
TEST3
TEST5
AVSS5
AVSS4
AVDD4
C9
C8
C7
AVSS6
AVDD3
C4
AVDD5
AVSS3
CCDIN
AVSS1
AVDD1
XSHPI
XSHP
VDD3
D7
D6
D5
C3
D10
D9
D8
C1
C2
D11
DVDD1
DVSS3
CLPOBI
CLPOB
DVSS1
DVDD2
CLPDMI
CLPDM
AVSS2
PBLKI
PBLK
TEST1
AVDD2
XSHDI
XSHD
VDD4
DVSS2
ADCLKI
ADCLK
G
H
J
CKI
CKO
MCKO
SSI1
VD
VSS4
VDD5
TEST2
VM
VSS3
VDD2
VSS1
SUB
H1
RG
H2
VSS2
K
L
OSCO
OSCI
SCK1
V4 (V2)
VH
V3A (V1A)
VL
SSGSL
RST
VDD1
M
N
V2 (NC) V5B (V3B)
V5A (V3A) V1 (NC)
WEN/FLD
SEN1
1
HD
2
VSS5
V3B (V1B) V6 (V4)
SNCSL
8
ID/EXP
9
3
4
5
6
7
Note) The symbol in parenthesis is for ICX434 mode.
– 3 –
CXD3423GA
Pin Description
Pin
Symbol
No.
I/O
Description
A1 D1
O
O
I
ADC output.
A2 D0
ADC output (LSB).
A3 SCK2
A4 SSI2
A5 TEST3
A6 AVSS4
A7 C8
CCD signal processor block serial interface clock input. (Schmitt trigger)
CCD signal processor block serial interface data input. (Schmitt trigger)
CCD signal processor block test input 3. Connect to DVSS.
CCD signal processor block analog GND.
Capacitor connection.
I
I
—
—
—
—
O
O
O
I
A8 AVSS6
A9 AVDD5
B1 D4
CCD signal processor block analog GND.
CCD signal processor block analog power supply.
ADC output.
B2 D3
ADC output.
B3 D2
ADC output.
B4 SEN2
B5 TEST5
B6 AVDD4
B7 C7
CCD signal processor block serial interface enable input. (Schmitt trigger)
CCD signal processor block test input 5. Connect to DVDD.
CCD signal processor block analog power supply.
Capacitor connection.
I
—
—
—
—
O
O
O
I
B8 AVDD3
B9 AVSS3
C1 D7
CCD signal processor block analog power supply.
CCD signal processor block analog GND.
ADC output.
C2 D6
ADC output.
C3 D5
ADC output.
C4 TEST4
C5 AVSS5
C6 C9
CCD signal processor block test input 4. Connect to DVSS.
CCD signal processor block analog GND.
Capacitor connection.
—
—
—
—
I
C7 C3
Capacitor connection.
C8 C4
Capacitor connection.
C9 CCDIN
D1 D10
D2 D9
CCD output signal input.
O
O
O
—
—
—
O
—
—
—
ADC output.
ADC output.
D3 D8
ADC output.
D7 C1
Capacitor connection.
D8 C2
Capacitor connection.
D9 AVSS1
E1 D11
E2 DVDD1
E3 DVSS1
E7 AVSS2
CCD signal processor block analog GND.
ADC output (MSB).
CCD signal processor block digital power supply. (Power supply for ADC)
CCD signal processor block digital GND. (GND for ADC)
CCD signal processor block analog GND.
– 4 –
CXD3423GA
Pin
No.
Symbol
I/O
Description
E8 AVDD2
E9 AVDD1
F1 DVSS2
F2 DVSS3
F3 DVDD2
—
—
—
—
—
CCD signal processor block analog power supply.
CCD signal processor block analog power supply.
CCD signal processor block digital GND.
CCD signal processor block digital GND.
CCD signal processor block digital power supply.
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
F7 PBLKI
I
F8 XSHDI
F9 XSHPI
G1 ADCLKI
G2 CLPOBI
G3 CLPDMI
G7 PBLK
I
I
CCD data level sample-and-hold pulse input. (Schmitt trigger)
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
Clock input for analog/digital conversion. (Schmitt trigger)
CCD optical black signal clamp pulse input. (Schmitt trigger)
CCD dummy signal clamp pulse input. (Schmitt trigger)
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD data level sample-and-hold pulse output.
I
I
I
O
O
O
G8 XSHD
G9 XSHP
CCD precharge level sample-and-hold pulse output.
Clock output for analog/digital conversion.
Logical phase adjustment possible using the serial interface data.
H1 ADCLK
O
CCD optical black signal clamp pulse output.
Horizontal and vertical OB pattern charge possible using the serial interface data.
H2 CLPOB
H3 CLPDM
H7 TEST1
O
O
I
CCD dummy signal clamp pulse output.
Timing generator block test input 1.
Normally fix to GND. (With pull-down resistor)
H8 VDD4
H9 VDD3
J1 CKI
J2 CKO
—
—
I
Timing generator block digital power supply. (Power supply for CDS block)
Timing generator block digital power supply. (Power supply for H1/H2)
Inverter input.
O
—
—
O
O
O
O
—
—
O
—
I
Inverter output.
J3
J7
VSS4
Timing generator block digital GND.
VSS3
Timing generator block digital GND.
J8 H1
CCD horizontal register clock output.
J9 H2
CCD horizontal register clock output.
K1 OSCO
K2 MCKO
K3 VDD5
K7 VDD2
K8 RG
Inverter output for oscillation. When not used, leave open or connect a capacitor.
System clock output for signal processor IC.
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block digital power supply. (Power supply for RG)
CCD reset gate pulse output.
K9 VSS2
L1 OSCI
L2 SSI1
Timing generator block digital GND.
Inverter input for oscillation. When not used, fix to low.
Timing generator block serial interface data input. Schmitt trigger input.
I
– 5 –
CXD3423GA
Pin
No.
Symbol
I/O
I
Description
Timing generator block test input 2.
Normally fix to GND. (With pull-down resistor)
L3 TEST2
L4 V4 (V2)
L5 VH
O
—
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
Timing generator block 15.0V power supply. (Power supply for vertical driver)
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
Timing generator block digital GND.
L6 V3A (V1A)
L7
L8 SSGSL
L9
VSS1
—
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid (With pull-down resistor)
I
—
I
VDD1
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block serial interface clock input.
Schmitt trigger input.
M1 SCK1
M2 VD
I/O Vertical sync signal input/output.
M3 VM
—
O
Timing generator block GND. (GND for vertical driver)
M4 V2 (NC)
M5 V5B (V3B)
M6 VL
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
Timing generator block –7.5V power supply. (Power supply for vertical driver)
CCD electric shutter pulse.
O
—
O
M7 SUB
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input.
M8 RST
I
Memory write timing pulse output/field discrimination pulse output.
Switching possible using the serial interface data. (Default: WEN output)
M9 WEN/FLD
N1 SEN1
O
I
Timing generator block serial interface strobe input.
Schmitt trigger input.
N2 HD
I/O Horizontal sync signal input/output.
N3 VSS5
—
O
O
O
O
Timing generator block digital GND.
N4 V5A (V3A)
N5 V1 (NC)
N6 V3B (V1B)
N7 V6 (V4)
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync (With pull-down resistor)
N8 SNCSL
N9 ID/EXP
I
Vertical direction line identification pulse output/Exposure time identification pulse
output.
O
Switching possible using the serial interface data. (Default: ID output)
– 6 –
CXD3423GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Pins
Symbol
VDDa
VDDb
VDDc
VDDd
VI+
Conditions
Min.
3.0
Typ.
3.3
3.3
3.3
3.3
Max.
3.6
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage 1 VDD2
Supply voltage 2 VDD3
Supply voltage 3 VDD4
Supply voltage 4 VDD1, VDD5
3.0
3.6
3.0
3.6
3.0
3.6
0.8VDDd
Input
RST, SSI1,
SCK1, SEN1
1
2
voltage 1
VI–
0.2VDDd
0.3VDDd
0.2VDDd
0.4
VIH1
0.7VDDd
0.8VDDd
Input
TEST1, TEST2,
SNCSL, SSGSL
voltage 2
VIL1
VIH2
VIL2
Input/output
voltage
VD, HD
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
Feed current where IOH = –1.2mA
Pull-in current where IOL = 2.4mA
VDDd – 0.8
Feed current where IOH = –14.0mA VDDb – 0.8
Pull-in current where IOL = 9.6mA
Output
voltage 1
H1, H2
RG
0.4
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
V
DDa – 0.8
Output
voltage 2
0.4
XSHP, XSHD,
PBLK,
CLPOB,
CLPDM,
ADCLK
VOH4
VOL4
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
VDDc – 0.8
V
V
Output
voltage 3
0.4
VOH5
VOL5
VOH6
VOL6
VOH7
VOL7
Feed current where IOH = –6.9mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
VDDd – 0.8
VDDd – 0.8
VDDd – 0.8
V
V
V
V
V
V
Output
voltage 4
CKO
0.4
0.4
0.4
Output
voltage 5
MCKO
Output
voltage 6
ID/EXP,
WEN/FLD
V1, V2, V3A/B, V4, V5A/B, V6
= –8.25V
IOL
10.0
mA
mA
V1, V2,
V1, V2, V3A/B, V4, V5A/B, V6
= –0.25V
IOM1
–5.0
Output
current 1
V3A, V3B,
V4, V5A,
V5B, V6
IOM2
IOH
V1, V3A/B, V5A/B = 0.25V
V1, V3A/B, V5A/B = 14.75V
SUB = –8.25V
5.0
5.4
mA
mA
mA
mA
–7.2
–4.0
IOSL
IOSH
Output
current 2
SUB
SUB = 14.75V
1
This input pin is a schmitt trigger input.
2
These input pins are with pull-down resistor in the IC.
Note) The above table indicates the condition for 3.3V drive.
– 7 –
CXD3423GA
Inverter I/O Characteristics for Oscillation
Item Pins Symbol Conditions
(Within the recommended operating conditions)
Min.
Typ.
Max.
Unit
V
Logical Vth OSCI
LVth
VIH
VDDd/2
0.7VDDd
V
Input
OSCI
voltage
VIL
0.3VDDd
V
VOH
VOL
Feed current where IOH = –3.6mA VDDd – 0.8
Pull-in current where IOL = 2.4mA
V
Output
OSCO
voltage
0.4
5M
V
Feedback
resistor
OSCI,
OSCO
RFB
f
VIN = VDDd or VSS
500k
20
2M
Ω
Oscillation
frequency
OSCI,
OSCO
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins Symbol
Conditions
Min.
Typ.
Max.
Unit
V
Logical Vth
LVth
VDDd/2
VIH
0.7VDDd
V
Input
voltage
CKI
VIL
VIN
0.3VDDd
V
Input
amplitude
fmax 50MHz sine wave
0.3
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source.
Input amplitude is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item Symbol
(VH = 15.0V, VM = GND, VL = –7.5V)
Conditions
Min.
200
200
30
Typ.
350
350
60
Max.
500
500
90
Unit
ns
ns
ns
ns
ns
ns
V
TTLM VL to VM
TTMH VM to VH
Rise time
TTLH
VL to VH
TTML VM to VL
TTHM VH to VM
200
200
30
350
350
60
500
500
90
Fall time
TTHL
VCLH
VCLL
VCMH
VCML
VH to VL
1.0
1.0
1.0
1.0
V
Output noise voltage
V
V
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
– 8 –
CXD3423GA
Switching Waveforms
TTMH
90%
TTHM
90%
VH
VM
V1 (V3A, V3B, V5A, V5B)
TTLM
10%
90%
TTML
10%
90%
10%
10%
VL
TTLM
TTML
VM
90%
90%
V2 (V4, V6)
10%
10%
VL
TTLH
TTHL
VH
90%
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
– 9 –
CXD3423GA
C 9
P B L K
X S H D
X S H P
S S 5 A V
T E S T 4
D 5
D 6
S S V 4
C L P O B
D 7
C L P D M
T E S T 1
D D 3 A V
S S 3 A V
C 7
D D V 4
D D V 3
D D 4 A V
C K I
C K
T E S T 5
O
S E N 2
D 2
S S V 4
S S V 3
H 1
D 3
D 4
H 2
D D 5 A V
D D V 5
S S 6 A V
C 8
O S C I
O S C O
S S 4 A V
D D V 2
R G
S S V 2
T E S T 3
S S I 2
S C K 2
D 1
O
M C K
S S I 1
D 0
S S V 5
– 10 –
CXD3423GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
d
SSI1
0.2VDD
d
0.8VDD
d
SCK1
SEN1
SEN1
ts1
th1
ts2
0.2VDD
d
ts3
0.8VDD
d
(Within the recommended operating conditions)
Symbol
ts1
Definition
Min.
20
Typ.
Max.
Unit
ns
SSI1 setup time, activated by the rising edge of SCK1
SSI1 hold time, activated by the rising edge of SCK1
SCK1 setup time, activated by the rising edge of SEN1
SEN1 setup time, activated by the rising edge of SCK1
th1
ts2
ts3
20
ns
20
ns
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1, V3A/B, V5A/B
HD
Enlarged view
0.2VDD
d
V1, V3A/B, V5A/B
ts1
th1
0.8VDD
d
SEN1
0.2VDD
d
Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal
period during which V1, V3A/B and V5A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
0
Typ.
Max.
Unit
ns
SEN1 setup time, activated by the falling edge of HD
SEN1 hold time, activated by the falling edge of HD
µs
123
– 11 –
CXD3423GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
0.2VDD
d
HD
ts1
th1
0.8VDD
d
SEN1
0.2VDD
d
Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
0
Typ.
Max.
Unit
ns
SEN1 setup time, activated by the falling edge of VD
SEN1 hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3423GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3423GA and controlled at the rising edge of SEN1. See "Description of Operation".
0.8VDDd
SEN1
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
5
Typ.
Max.
100
Unit
ns
Output signal delay, activated by the rising edge of SEN1
tpdPULSE
– 12 –
CXD3423GA
RST loading characteristics
0.8VDD
d
RST
0.2VDD
d
tw1
(Within the recommended operating conditions)
Symbol
Definition
Min.
35
Typ.
Max.
Unit
ns
tw1
RST pulse width
VD and HD loading characteristics
VD, HD
MCKO
0.2VDD
d
0.2VDD
d
ts1
0.8VDD
th1
d
MCKO load capacitance = 10pF
Symbol
(Within the recommended operating conditions)
Definition
Min.
13
0
Typ.
Max.
Unit
ns
ts1
th1
VD and HD setup time, activated by the rising edge of MCKO
VD and HD hold time, activated by the rising edge of MCKO
ns
Output variation characteristics
0.8VDDd
MCKO
WEN/FLD,
ID/EXP
tpd1
WEN/FLD and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Time until the above outputs change after the rise of MCKO
Min.
20
Typ.
Max.
60
Unit
ns
– 13 –
CXD3423GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Item
Pins
Symbol
VDDe
Conditions
Min.
3.0
Typ. Max. Unit
Supply voltage 1 DVDD1
Supply voltage 2 DVDD2
3.3 3.6
3.3 3.6
V
V
VDDf
3.0
AVDD1,
AVDD2,
Supply voltage 3 AVDD3,
AVDD4,
VDDg
3.0
3.3 3.6
V
AVDD5
Analog input
CCDIN
CIN
15
pF
V
capacitance
SCK2, SSI2,
VI+
1.8
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI, VI–
CLPOBI,
Input voltage
1.1
V
CLPDMI, PBLKI
A/D clock duty ADCLKI
50
%
V
VOH
VOL
Feed current where IOH = –2.0mA VDDe – 0.9
Pull-in current where IOL = 2.0mA
Output voltage D0 to D11
0.4
V
Analog Characteristics
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Item
Pins
VIN
Conditions
Min. Typ. Max. Unit
CCDIN input voltage amplitude
PGA maximum gain
PGA gain = 0dB, output full scale
PGA gain setting data = "3FFh"
PGA gain setting data = "000h"
900
1100 mV
dB
Gmax
Gmin
42
–6
12
PGA minimum gain
dB
ADC resolution
bit
ADC maximum conversion rate
ADC integral non-linearity error
Fc max
EL
24.3
MHz
LSB
LSB
dB
PGA gain = 0dB
PGA gain = 0dB
PGA gain = 0dB
±2.0
±1.0
77
ADC differential non-linearity error ED
Signal-to-noise ratio
SNR
CCDIN input voltage clamp level
CLP
OB
1.5
V
CCD optical black signal clamp
level
OBLVL = "8h"
PGA gain = 0dB
130
LSB
– 14 –
CXD3423GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
SSI2
0.2VDD
0.8VDD
ts1
SCK2
th1
ts2
SEN2
SEN2
0.2VDD
ts3
0.8VDD
The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise
of SEN2.
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tp1
Definition
Min.
100
30
Typ.
Max.
Unit
ns
SCK2 clock period
ts1
th1
ts2
ts3
SSI2 setup time, activated by the rise of SCK2
SSI2 hold time, activated by the rise of SCK2
SCK2 setup time, activated by the rise of SEN2
SEN2 setup time, activated by the rise of SCK2
ns
30
ns
30
ns
30
ns
– 15 –
CXD3423GA
CDS/ADC Timing Chart
N
N + 1
N + 2
N + 3
CCDIN
XSHPI
XSHDI
tw1
ADCLKI
DL
D0 to D11
N – 10
N – 9
N – 8
N – 7
Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tw1
Definition
Min.
41
Typ.
Max.
Unit
ns
ADCLKI clock period
ADCLKI clock duty
Data latency
50
9
%
DL
clocks
Preblanking Timing Chart
PBLKI
11 Clocks
ADCLKI
11 Clocks
All "0"
D0 to D11
– 16 –
CXD3423GA
Description of Operation
Pulses output from the CXD3423GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 19 and thereafter.
Pin Status Table
Pin
No.
Pin
No.
Symbol
D1
CAM
SLP
STB
RST
Symbol
C2
CAM
SLP
STB
RST
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D0
AVSS1
D11
SCK2
SSI2
TEST3
AVSS4
C8
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
TEST1
VDD4
AVSS6
AVDD5
D4
D3
D2
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
D7
ACT
ACT
ACT
ACT
ACT
ACT
L
L
L
L
L
L
L
L
L
L
L
L
H
ACT
ACT
ACT
H
D6
D5
TEST4
AVSS5
C9
H
—
—
—
C3
C4
VDD3
CCDIN
D10
D9
CKI
ACT
ACT
ACT
ACT
ACT
L
ACT
ACT
J2
CKO
J3
VSS4
—
—
D8
J7
VSS3
C1
J8
H1
ACT
L
L
ACT
– 17 –
CXD3423GA
Pin
No.
Pin
No.
Symbol
H2
CAM
SLP
STB
RST
Symbol
CAM
ACT
SLP
L
STB
RST
H
1
J9
K1
K2
K3
K7
K8
K9
L1
L2
L3
L4
L5
L6
L7
L8
L9
M1
ACT
ACT
ACT
L
L
ACT
L
ACT
ACT
ACT
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
VD
L
OSCO
MCKO
VDD5
ACT
ACT
VM
—
—
V2 (NC)
V5B (V3B)
VL
ACT
ACT
VM
VH
VM
VH
VM
VL
—
—
VDD2
RG
ACT
L
L
ACT
SUB
ACT
ACT
ACT
ACT
ACT
VH
ACT
L
VH
ACT
L
VL
L
VSS2
—
RST
OSCI
SSI1
ACT
ACT
ACT
ACT
ACT
ACT
ACT
DIS
WEN/FLD
SEN1
L
ACT
L
ACT
L
DIS
H
1
TEST2
V4 (V2)
VH
—
—
—
—
HD
ACT
ACT
ACT
ACT
VM
VH
VM
VH
VM
VM
VSS5
—
V5A (V3A)
V1 (NC)
V3B (V1B)
V6 (V4)
SNCSL
ID/EXP
ACT
ACT
ACT
ACT
ACT
ACT
VH
VH
VH
VH
ACT
L
VH
VH
VH
VH
ACT
L
VL
VM
VM
VL
V3A (V1A)
VSS1
SSGSL
VDD1
ACT
ACT
ACT
DIS
ACT
L
SCK1
ACT
ACT
1
It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin L5), VM (Pin M3) and VL (Pin M6),
respectively, in the controlled status.
– 18 –
CXD3423GA
Timing Generator Block Serial Interface Control
The CXD3423GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V3A/B and V5A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
00 01 02 03 04 05 06 07
41 42 43 44 45
46 47
SSI1
SCK1
SEN1
There are two categories of timing generator block serial interface data: CXD3423GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 19 –
CXD3423GA
Control Data
Data Symbol
D00
Function
Data = 0
10000001
Data = 1
→ Enabled
RST
All
0
to
CHIP
Chip enable
Other values → Disabled
D07
D08 CTG
D09
Category switching
—
See D08 CTG.
0
All
0
to
—
—
—
D11
D12,
D13
MODE
—
Drive mode switching
See D12 , D13 MODE.
0
0
D14,
D15
—
—
—
1
D16 NTPL
D17 CCD
Internal SSG function switching
NTSC
PAL
0
0
1
CCD switching
ICX432
ICX284/434
D18,
—
—
—
—
0
D19
2
D20 SMD
D21 HTSG
D22
Electronic shutter mode switching
OFF
OFF
ON
ON
0
0
2
HTSG control switching
All
0
to
—
—
—
—
D30
D31 FLD
D32 FGOB
D33 EXP
WEN/FLD output switching
Wide CLPOB generation switching
ID/EXP output switching
WEN
OFF
ID
FLD
ON
0
0
0
FL
EXP
D34,
PTOB
D35
All
0
CLPOB waveform pattern switching
ADCLK logic phase adjustment
Standby control
See D34 , D35 PTOB.
D36,
LDAD
D37
All
0
See D36 , D37 LDAD.
See D38 , D39 STB.
D38,
STB
D39
All
0
D40
to
D47
All
0
—
—
—
—
1
See D12 , D13 MODE.
See D20 SMD.
2
– 20 –
CXD3423GA
Shutter Data
Data Symbol
D00
Function
Data = 0
10000001
Data = 1
→ Enabled
RST
All
0
to
CHIP
Chip enable
Other values → Disabled
See D08 CTG.
—
D07
D08 CTG
Category switching
—
0
0
D09
—
D10
to
D19
Electronic shutter vertical period
specification
All
0
SVD
See D10 to D19 SVD.
See D20 to D31 SHD.
See D32 to D41 SPL.
—
D20
to
D31
Electronic shutter horizontal period
specification
All
0
SHD
SPL
—
D32
to
D41
High-speed shutter position
specification
All
0
D42
to
D47
All
0
—
– 21 –
CXD3423GA
Detailed Description of Each Data
Shared data: D08 CTG [Category]
Of the data provided to the CXD3423GA by the timing generator block serial interface, the CXD3423GA loads
D10 and subsequent data to each data register as shown in the table below according to D08 .
D08
0
Description of operation
Loading to control data register
Loading to shutter data register
1
Note that the CXD3423GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D12 , D13 MODE [Drive mode]
The CXD3423GA drive mode can be switched as follows. However, the drive mode bits are loaded to the
CXD3423GA and reflected at the falling edge of VD.
D13
0
D12
0
Description of operation
Draft mode (default)
0
1
Frame mode
1
1
0
AF mode
1
1
Test mode
1
The test mode results in ICX284/434 mode.
Draft mode is the pulse elimination drive mode. This is a high frame rate drive mode that can be used for
purposes such as monitoring and moving pictures.
AF mode is the drive mode for applications with an even higher frame rate, and is used for auto focus (AF).
Frame mode is the drive mode in which the data for all lines of the ICX284/432/434 are read.
Control data: D16 NTPL [SSG function switching]
The CXD3423GA internal SSG output pattern can be switched as follows. However, the drive mode bits are
loaded to the CXD3423GA and reflected at the falling edge of VD. The default is "NTSC".
D16
0
Description of operation
NTSC equivalent pattern output (internal SSG)
PAL equivalent pattern output (internal SSG)
1
– 22 –
CXD3423GA
Control data: D17 CCD [Used CCD switching]
This specifies the CCD image sensor to be used. However, like the drive mode bits, the CCD switching bits are
loaded to the CXD3423GA and reflected at the falling edge of VD. The default is "ICX432".
D17
0
Description of operation
ICX432
ICX284/434
1
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
0
Description of operation
Wide CLPOB generation OFF
Wide CLPOB generation ON
1
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
0
D34
0
Waveform pattern
(Normal)
0
1
(Shifted rearward)
(Shifted forward)
(Wide)
1
0
1
1
Control data: D36 , D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO.
D37
0
D36
0
Degree of adjustment (°)
0
0
1
90
1
0
180
270
1
1
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3423GA and
control is applied immediately at the rising edge of SEN1.
D39
X
D38 Symbol
Operating mode
0
1
1
CAM Normal operating mode
0
SLP
STB
Sleep mode
1
Standby mode
See the Pin Status Table for the pin status in each mode.
– 23 –
CXD3423GA
Control data/shutter data: [Electronic shutter]
The CXD3423GA realizes various electronic shutter functions by using control data D20 SMD and D21
HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using control data D20 SMD.
D20
0
Description of operation
Electronic shutter stopped mode
Electronic shutter mode
1
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
LSB
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20
X
0
0
1
1
1
0
0
0
0
1
1
↓
↓
↓
1
C
3
→ SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
SVD
Data
Description
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
D10 to D19
D20 to D31
D32 to D41
SHD
SPL
Note) The bit data definition area is assured in terms of the CXD3423GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD × (1V period) + {(number of HD per 1V) – (SHD + 1)} × (1H period)
+ (distance from SUB to SG during the readout period)
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 24 –
CXD3423GA
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
SVD
SHD
01
01
002h
10Fh
000h
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
002
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
SPL
1
1
001h
002h
10Fh
000h
000h
0A3h
SVD
SHD
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 25 –
CXD3423GA
[HTSG control mode]
This mode controls the ternary level outputs of V1, V3A/B, V5A/B (readout pulse block) using D21 HTSG.
D21
0
Description of operation
Readout pulse (SG) normal operation
HTSG control mode
1
VD
V1A
SUB
VCK
WEN
EXP
HTSG
SMD
0
1
1
0
0
1
Exposure time
[EXP pulse]
The ID/EXP pin (Pin N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP.
The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure
time when it is high. In principle, the transition points are the last SUB pulse falling edge and the readout
pulse falling edge, that is to say from the time the charge is completely discharged until transfer ends.
However, when the readout pulse timing differs within the same readout portion such as in draft mode, the
average value is used. Then, when there is no SUB pulse in the next field, the readout pulse falling edge is
defined as the start position, but in this case the transition points overlap and disappear, so a tentative start
position is defined.
This is shown below.
SG↓
1460
Tentative start position
1480
1784
1091
1195
1175
Frame mode
[ICX432]
Draft/AF mode
1682
A: 1071
B: 1175
1123
Frame mode
Draft mode
[ICX284/
434]
See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
– 26 –
CXD3423GA
4
1
6
3
1 5 4 8
1 5 4 5
1 2 3 6
9
6
3
8
5
2
1 5 5 0
1 5 4 7
8
5
2
7
4
1
1 5 4 9
1 5 4 6
– 27 –
CXD3423GA
3 0 2 8
2 9 2 5
2 2 2 0
1 7 1 3
1 0
8
1
5
6
4
1 5 4 9
1 5 4 6 1 5 4 4
1 5 4 1 1 5 3 7
1 5 3 4 1 5 3 2
1 5 2 7 1 5 2 5
3 0 2 8
2 9 2 5
2 2 2 0
1 7 1 3
1 0
8
1
5
6
4
1 5 4 9
1 5 4 6 1 5 4 4
1 5 4 1 1 5 3 7
1 5 3 4 1 5 3 2
– 28 –
CXD3423GA
6
4
1 5 2 7 1 5 2 5
4 9 0 4 8 8
4 8 5 4 8 1
4
6
– 29 –
CXD3423GA
6 8 0
6 7 6
6 7 2
– 30 –
CXD3423GA
9 2 4
9 2 0
9 1 6
– 31 –
CXD3423GA
– 32 –
CXD3423GA
9 2 4
9 2 0
9 1 6
– 33 –
CXD3423GA
9 2 4
9 2 0
9 1 6
– 34 –
CXD3423GA
6 0 2
5 6 0
5 1 8
4 7 6
4 3 4
3 9 2
3 5 0
3 0 8
2 6 6
2 2 4
1 8 2
1 4 0
1 5 4 6
1 5 0 2
1 4 6 0
1 4 2 0
1 3 8 0
1 3 3 8
1 2 9 6
1 2 5 4
– 35 –
CXD3423GA
6 0 2
5 6 0
5 1 8
4 7 6
4 3 4
3 9 2
3 5 0
3 0 8
2 6 6
2 2 4
1 8 2
1 4 0
1 4 6 0
1 4 2 0
1 3 8 0
1 3 3 8
1 2 9 6
1 2 5 4
1 2 1 2
1 1 7 0
1 1 2 8
1 0 8 6
– 36 –
CXD3423GA
7 2 9
6 9 8
6 6 7
6 3 6
6 0 5
5 7 4
5 4 3
5 1 2
4 8 1
4 5 0
4 1 9
3 8 8
3 5 7
3 2 6
2 9 5
2 6 4
2 3 3
2 0 2
1 7 1
1 4 0
1 9 0 8
1 8 7 7
1 8 4 6
1 8 1 5
1 7 8 4
1 7 4 4
1 7 0 4
1 6 7 3
1 6 4 2
1 6 1 1
1 5 8 0
1 5 4 0
1 5 0 0
1 4 6 9
1 4 3 8
1 4 0 7
– 37 –
CXD3423GA
– 38 –
CXD3423GA
1 2
1 0
8
6
4
2
1 0
8
6
4
2
1 2 3 5
1 2 3 3
1 2 3 1
1 2 2 9
1 2 2 7
1 2 2 5
2 7
2 5
2 3
2 1
1 9
1 7
1 5
1 3
1 1
9
7
5
3
1
9
7
5
3
1
1 2 3 6
1 2 3 4
1 2 3 2
1 2 3 0
1 2 2 8
– 39 –
CXD3423GA
3 4
3 1
2 6
2 3
1 8
1 5
1 0
7
2
9
4
1 2 3 4
1 2 3 1
1 2 2 6
1 2 2 3
1 2 1 8
1 2 1 5
1 2 1 0
1 2 0 7
1 2 0 2
6 3
5 8
5 5
5 0
4 7
4 2
3 9
3 4
3 1
2 6
2 3
1 8
1 5
1 0
7
2
9
4
1 2 3 4
1 2 3 1
1 2 2 6
1 2 2 3
1 2 1 8
1 2 1 5
1 2 1 0
1 2 0 7
– 40 –
CXD3423GA
– 41 –
CXD3423GA
– 42 –
CXD3423GA
– 43 –
CXD3423GA
1 1 7 5
1 1 3 3
1 1 3 1
1 0 9 1
1 0 7 1
1 0 2 9
1 0 2 7
– 44 –
CXD3423GA
1 1 7 5
1 1 3 3
1 1 3 1
1 1 1 1
1 0 9 1
1 0 7 1
1 0 2 9
1 0 2 7
– 45 –
CXD3423GA
– 46 –
CXD3423GA
– 47 –
CXD3423GA
CCD Signal Processor Block Serial Interface Control
The CXD3423GA's CCD signal processor block basically loads the CCD signal processor block serial
interface data sent in the following format at the rising edge of SEN2, and the setting values are then reflected
to the operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
SSI2
SCK2
SEN2
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
There are five categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, input pulse polarity setting data, and output delay adjustment data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value has been reflected to operation 6 ADCKLI clocks after that, then
transmit the next category.
When the power supply is set to ON, be sure to initialize for transmitting all category data.
The details of each data are described below.
Standby Control Data
Data
Symbol
Function
Data = 0
Data = 1
D00 TEST
Test code
Set to "0".
D01
to
D03
CTG
Category switching
D01 to D03 CTG
Set to "all 0".
D04
to
FIXED
—
D14
D15 STB
Standby control
Normal operation mode
Standby mode
PGA Gain Setting Data
Data
Symbol
Function
Data = 0
Data = 1
D00 TEST
Test code
Set to "0".
D01
to
D03
CTG
Category switching
—
D01 to D03 CTG
Set to "all 0".
D04,
D05
FIXED
GAIN
D06
to
PGA gain setting data
See D06 to D15 GAIN.
D15
– 48 –
CXD3423GA
OB Clamp Level Setting Data
Data Symbol
Function
Data = 0
Data = 1
D00 TEST
D01
Test code
Set to "0".
to
D03
CTG
Category switching
—
D01 to D03 CTG
Set to "all 0".
D04
to
D11
FIXED
OBLVL
D12
to
OB clamp level setting data
See D12 to D15 OBLVL.
D15
Input Pulse Polarity Setting Data
Data Symbol
Function
Data = 0
Data = 1
D00 TEST
Test code
Set to "0".
D01
to
CTG
Category switching
D01 to D03 CTG
D03
D04
to
D12
FIXED
POL
—
Set to "all 0".
Set to "all 0".
D13
to
Input pulse polarity setting data
D15
Output Delay Adjustment Data
Data Symbol
Function
Data = 0
Data = 1
D00 TEST
Test code
Set to "0".
D01
to
CTG
Category switching
D01 to D03 CTG
D03
D04
to
D13
FIXED
ODL
—
Set to "all 0".
D14,
D15
Output delay adjustment data
See D14 and D15 ODL.
– 49 –
CXD3423GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3423GA by the CCD signal processor block serial interface, the CXD3423GA
loads D04 and subsequent data to each data register as shown in the table below according to the
combination of D01 to D03 .
D01
0
D02
0
D03
0
Description of operation
Loading to standby control data register
Loading to PGA gain setting data register
Loading to OB clamp level setting data register
Loading to input pulse polarity setting data register
Loading to output delay adjustment data register
Access prohibited
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
x
Access prohibited
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
D15
0
Description of operation
Normal operating mode
Standby mode
1
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3423GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
MSB
LSB
D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
0
1
1
1
0
0
0
0
1
1
↓
↓
↓
→ GAIN is expressed as 1C3h .
1
C
3
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
– 50 –
CXD3423GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp level]
The CXD3423GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
LSB
D12 D13 D14 D15
MSB
0
1
1
0
↓
→ OBLVL is expressed as 6h .
6
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 2LSB, 18LSB, 130LSB and 242LSB.
Output delay adjustment data: D14 and D15 ODL [Output delay]
The CXD3423GA can adjust the output delay time of 12-bit digital output against rising of ADCLK by using
output delay adjustment data D14 and D15 ODL.
D14
0
D15
0
Description of operation
Output delay is not added.
0
1
Output delay addition 5ns (Typ.)
Output delay addition 10ns (Typ.)
Output delay addition 13ns (Typ.)
1
0
1
1
Note: In the case that the output delay is not added, the delay time is about 2 to 10ns.
– 51 –
CXD3423GA
S C K 2
S E N 2
S S I 2
C 9
0 . 1 µ F
C 8
0 . 1 µ F
S C K 1
S E N 1
C 7
0 . 1 µ F
S S I 1
A D C L K I
A D C L K
C L P O B
C L P D M
T E S T 5
T E S T 4
T E S T 3
T E S T 2
T E S T 1
P B L K
X S H D
X S H P
C L P O B I
C L P D M I
P B L K I
O S C I
X S H D I
X S H P I
O S C O
C K I
– 52 –
CXD3423GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins and CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
+15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5 pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin
from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block VDD4, pin supply voltage 3 VDDc and the CCD
signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2
VDDf and 3 VDDg should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,
VSS5 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5
and AVSS6 should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
– 53 –
CXD3423GA
Package Outline
Unit: mm
0.2
S
A
96PIN LFLGA
8.0
X
PIN 1 INDEX
1.3 MAX
0.10MAX
x4
0.15
DETAIL X
96 -φ0.45 ± 0.05
(0.3)
0.5
0.8
A
M
S A B
φ0.08
N
M
L
K
J
B
H
G
F
E
D
C
B
3 – φ0.50
A
1 2
0.5
3
4 5
6
7
0.8
8 9
PACKAGE STRUCTURE
0.5
(0.3)
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
ORGANIC SUBSTRATE
NICKEL & GOLD PLATING
COPPER
LFLGA-96P-02
SONY CODE
EIAJ CODE
P-LFLGA96-12X8-0.8
JEDEC CODE
0.3g
Sony Corporation
– 54 –
相关型号：
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