CXD3504R [SONY]
Color Shading Correction IC for Liquid Crystal Projectors; 色着色校正集成电路为液晶投影机
| 型号： | CXD3504R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Color Shading Correction IC for Liquid Crystal Projectors |
| 文件： | 总12页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD3504R
Selective Delay Line for LCD
Description
176 pin LQFP (Plastic)
The CXD3504R is a selective delay line IC for
performing signal processing during dot and line
inverted drive of liquid crystal panels for Sony
projectors.
This chip has three built-in 10-bit × 1200-word 1H
delay lines, and data path with or without a 1H delay
can be selected by the control pins.
Features
Absolute Maximum Ratings (Vss = 0V)
• Supports dot and line inverted drive of liquid crystal
panels for Sony projectors
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
–0.3 to +4.6
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–30 to +75
V
V
• Three built-in 10-bit × 1200-word 1H delay lines
• Data path with or without a 1H delay can be selected
by the control pins.
VO
V
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
°C
°C
–55 to +125
Applications
PDmax 850mW (Ta ≤ 75°C)
LCD projectors, etc.
Recommended Operating Conditions
Structure
• Supply voltage
• Operating temperature Topr
• Input voltage
VDD
3.0 to 3.6
–30 to +75
0 to VDD
V
°C
V
Silicon gate CMOS IC
VIN
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99815-PS
CXD3504R
Block Diagram
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VSS 133
G1IN9 134
G1IN8 135
G1IN7 136
G1IN6 137
G1IN5 138
G1IN4 139
G1IN3 140
G1IN2 141
G1IN1 142
G1IN0 143
G2IN9 144
G2IN8 145
G2IN7 146
G2IN6 147
G2IN5 148
G2IN4 149
G2IN3 150
G2IN2 151
G2IN1 152
G2IN0 153
VDD 154
88 VDD
87 R2OUT4
86 R2OUT3
85 R2OUT2
84 R2OUT1
83 R2OUT0
82 VSS
R CH FIFO
81 VDD
80 TEST2
79 G1OUT9
78 G1OUT8
77 G1OUT7
76 G1OUT6
75 G1OUT5
74 VSS
INPUT
LATCH
&
OUTPUT
SELECT
&
G CH FIFO
73 VDD
SELECT
LATCH
72 G1OUT4
71 G1OUT3
70 G1OUT2
69 G1OUT1
68 G1OUT0
67 VSS
66 VDD
VSS 155
65 G2OUT9
64 G2OUT8
63 G2OUT7
62 G2OUT6
61 G2OUT5
60 VSS
B1IN9 156
B1IN8 157
B1IN7 158
B1IN6 159
B1IN5 160
B1IN4 161
B1IN3 162
B1IN2 163
B1IN1 164
B1IN0 165
B2IN9 166
B2IN8 167
B2IN7 168
B2IN6 169
B2IN5 170
B2IN4 171
B2IN3 172
B2IN2 173
B2IN1 174
B2IN0 175
VDD 176
B CH FIFO
59 VDD
58 G2OUT4
57 G2OUT3
56 G2OUT2
55 G2OUT1
54 G2OUT0
53 VSS
TIMING
GENERATOR
52 VDD
51 TEST1
50 B1OUT9
49 B1OUT8
48 B1OUT7
47 B1OUT6
46 B1OUT5
SS
CLK SEL
45
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
– 2 –
CXD3504R
Pin Configuration
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VSS 133
G1IN9 134
G1IN8 135
G1IN7 136
G1IN6 137
G1IN5 138
G1IN4 139
G1IN3 140
G1IN2 141
G1IN1 142
G1IN0 143
G2IN9 144
G2IN8 145
G2IN7 146
G2IN6 147
G2IN5 148
G2IN4 149
G2IN3 150
G2IN2 151
G2IN1 152
G2IN0 153
VDD 154
88 VDD
87 R2OUT4
86 R2OUT3
85 R2OUT2
84 R2OUT1
83 R2OUT0
82 VSS
81 VDD
80 TEST2
79 G1OUT9
78 G1OUT8
77 G1OUT7
76 G1OUT6
75 G1OUT5
74 VSS
73 VDD
72 G1OUT4
71 G1OUT3
70 G1OUT2
69 G1OUT1
68 G1OUT0
67 VSS
VSS 155
66 VDD
B1IN9 156
B1IN8 157
B1IN7 158
B1IN6 159
B1IN5 160
B1IN4 161
B1IN3 162
B1IN2 163
B1IN1 164
B1IN0 165
B2IN9 166
B2IN8 167
B2IN7 168
B2IN6 169
B2IN5 170
B2IN4 171
B2IN3 172
B2IN2 173
B2IN1 174
B2IN0 175
VDD 176
65 G2OUT9
64 G2OUT8
63 G2OUT7
62 G2OUT6
61 G2OUT5
60 VSS
59 VDD
58 G2OUT4
57 G2OUT3
56 G2OUT2
55 G2OUT1
54 G2OUT0
53 VSS
52 VDD
51 TEST1
50 B1OUT9
49 B1OUT8
48 B1OUT7
47 B1OUT6
46 B1OUT5
SS
45
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
– 3 –
CXD3504R
Pin Description
Pin
Input pin for
open status
Symbol
No.
I/O
Description
1
2
3
4
5
6
7
8
9
VSS
P
I
GND
1
PECLCK
NC
Very little amp. clock input
2
CMOSCK
VSS
I
P
I
CMOS clock input
GND
CLKSEL
SELRA
SELGA
SELBA
0: PECL, 1: CMOS
L
L
L
L
L
H
I
SELA (Data path selection A) for R
SELA (Data path selection A) for G
SELA (Data path selection A) for B
Data path selection B
I
I
10 SELB
11 XCLR
12 HD
I
I
0: Direct Reset
I
Horizontal sync signal input
HD selection (0: ↓, 1: ↑)
13 HDSEL
14 HDEDGE
15 NC
I
L
L
I
CK trigger selection of HD (0: ↓, 1: ↑)
Reserve
16 REDGE
17 GEDGE
18 BEDGE
19 POLSLA
20 NC
I
I
I
I
CK trigger selection of R (0: ↓, 1: ↑)
CK trigger selection of G (0: ↓, 1: ↑)
CK trigger selection of B (0: ↓, 1: ↑)
SELA polarity selection
L
L
L
L
21 NC
22
23
VDD
VSS
P
P
Power supply
GND
24 B2OUT0
25 B2OUT1
26 B2OUT2
27 B2OUT3
28 B2OUT4
O
O
O
O
O
P
B2 output
B2 output
B2 output
B2 output
B2 output
Power Supply
GND
29
30
VDD
VSS
P
31 B2OUT5
32 B2OUT6
33 B2OUT7
O
O
O
B2 output
B2 output
B2 output
1
2
Connect to GND or VDD when using CMOS clock.
Connect to GND or VDD when using small amplitude clock.
– 4 –
CXD3504R
Pin
No.
Input pin for
open status
Symbol
I/O
Description
34 B2OUT8
35 B2OUT9
O
O
P
P
O
O
O
O
O
I
B2 output
B2 output
Power supply
GND
36
37
VDD
VSS
38 B1OUT0
39 B1OUT1
40 B1OUT2
41 B1OUT3
42 B1OUT4
43 TEST0
B1 output
B1 output
B1 output
B1 output
B1 output
1: Test mode
Power supply
GND
L
44
45
VDD
VSS
P
P
O
O
O
O
O
I
46 B1OUT5
47 B1OUT6
48 B1OUT7
49 B1OUT8
50 B1OUT9
51 TEST1
B1 output
B1 output
B1 output
B1 output
B1 output
1: Test mode
Power supply
GND
L
52
53
VDD
VSS
P
P
O
O
O
O
O
P
P
O
O
O
O
O
P
P
O
54 G2OUT0
55 G2OUT1
56 G2OUT2
57 G2OUT3
58 G2OUT4
G2 output
G2 output
G2 output
G2 output
G2 output
Power supply
GND
59
60
VDD
VSS
61 G2OUT5
62 G2OUT6
63 G2OUT7
64 G2OUT8
65 G2OUT9
G2 output
G2 output
G2 output
G2 output
G2 output
Power supply
GND
66
67
VDD
VSS
68 G1OUT0
G1 output
– 5 –
CXD3504R
Pin
No.
Input pin for
open status
Symbol
I/O
Description
69 G1OUT1
70 G1OUT2
71 G1OUT3
72 G1OUT4
O
O
O
O
P
P
O
O
O
O
O
I
G1 output
G1 output
G1 output
G1 output
Power supply
GND
73
74
VDD
VSS
75 G1OUT5
76 G1OUT6
77 G1OUT7
78 G1OUT8
79 G1OUT9
80 TEST2
G1 output
G1 output
G1 output
G1 output
G1 output
1: Test mode
Power supply
GND
L
81
82
VDD
VSS
P
P
O
O
O
O
O
P
P
O
O
O
O
O
I
83 R2OUT0
84 R2OUT1
85 R2OUT2
86 R2OUT3
87 R2OUT4
R2 output
R2 output
R2 output
R2 output
R2 output
Power supply
GND
88
89
VDD
VSS
90 R2OUT5
91 R2OUT6
92 R2OUT7
93 R2OUT8
94 R2OUT9
95 TEST3
R2 output
R2 output
R2 output
R2 output
R2 output
1: Test mode
Power supply
GND
L
96
97
VDD
VSS
P
P
O
O
O
O
O
P
P
98 R1OUT0
99 R1OUT1
100 R1OUT2
101 R1OUT3
102 R1OUT4
103 VDD
R1 output
R1 output
R1 output
R1 output
R1 output
Power supply
GND
104 VSS
– 6 –
CXD3504R
Pin
No.
Input pin for
open status
Symbol
I/O
Description
105 R1OUT5
106 R1OUT6
107 R1OUT7
108 R1OUT8
109 R1OUT9
110 VDD
O
O
O
O
O
P
P
I
R1 output
R1 output
R1 output
R1 output
R1 output
Power supply
GND
111 VSS
112 R1IN9
113 R1IN8
114 R1IN7
115 R1IN6
116 R1IN5
117 R1IN4
118 R1IN3
119 R1IN2
120 R1IN1
121 R1IN0
122 R2IN9
123 R2IN8
124 R2IN7
125 R2IN6
126 R2IN5
127 R2IN4
128 R2IN3
129 R2IN2
130 R2IN1
131 R2IN0
132 VDD
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
Power supply
GND
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P
P
I
133 VSS
134 G1IN9
135 G1IN8
136 G1IN7
137 G1IN6
138 G1IN5
139 G1IN4
140 G1IN3
G1 input
G1 input
G1 input
G1 input
G1 input
G1 input
G1 input
I
I
I
I
I
I
– 7 –
CXD3504R
Pin
No.
Input pin for
open status
Symbol
I/O
Description
141 G1IN2
142 G1IN1
143 G1IN0
144 G2IN9
145 G2IN8
146 G2IN7
147 G2IN6
148 G2IN5
149 G2IN4
150 G2IN3
151 G2IN2
152 G2IN1
153 G2IN0
154 VDD
I
I
G1 input
G1 input
G1 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
Power supply
GND
I
I
I
I
I
I
I
I
I
I
I
P
P
I
155 VSS
156 B1IN9
157 B1IN8
158 B1IN7
159 B1IN6
160 B1IN5
161 B1IN4
162 B1IN3
163 B1IN2
164 B1IN1
165 B1IN0
166 B2IN9
167 B2IN8
168 B2IN7
169 B2IN6
170 B2IN5
171 B2IN4
172 B2IN3
173 B2IN2
174 B2IN1
175 B2IN0
176 VDD
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
Power supply
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P
– 8 –
CXD3504R
Electrical Characteristics
(Input/Output level/VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C)
Item
Symbol
VIH
Conditions
Min.
0.7VDD
—
Typ.
—
Max.
—
Unit Applicable pins
V
High level input voltage
Low level input voltage
1, 2,
3
CMOS input
VIL
—
0.2VDD
—
V
V
High level output voltage VOH
Low level output voltage VOL
IOH = –12mA
IOL = 12mA
VDD – 0.8
—
—
4
—
0.4
V
1, 2,
3
Input leak current
Pull-up resistor
IIL
VI = VSS, VDD
–10
—
10
µA
kΩ
kΩ
2
3
RUP
RDN
80
160
180
320
360
Pull-down resistor
90
1
Input pins except PECLCK
XCLR
2
3
4
CLKSEL, SELRA, SELGA, SELBA, SELB, HDSEL, HDEDGE, REDGE, GEDGE, BEDGE, POLSLA
All output pins
AC Characteristics
PECLCK
(CMOSCK)
t1
t3
t2
HD
t4
d in
Input Data
(R, G, B )
d in
99b
d in
100b
d in
1c
d in
3c
d in
4c
d in
5c
d in
6c
d in
7c
d in
8c
d in
9c
d in
10c
d in
11c
d in
12c
d in
13c
2c
t5
Through
Output
d in
95b
d in
96b
d in
97b
d in
98b
d in
99b
d in
100b
d in
4c
d in
5c
d in
6c
d in
7c
d in
8c
d in
9c
No Care
No Care
Delay
Output
d in
95a
d in
96a
d in
97a
d in
98a
d in
99a
d in
100a
d in
4b
d in
5b
d in
6b
d in
7b
d in
8b
d in
9b
Item
Symbol
Min.
—
1.5
4.5
1
Max.
80
—
Unit
Input frequency
f
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HD set-up time to PECLCK bar
HD hold time from PECLCK bar
t1
t2
t3
—
R, G, B input data set-up time to PECLCK bar
—
R, G, B input data hold time from PECLCK bar t4
6.5
4
—
R, G, B output data delay from PECLCK
HD set-up time to CMOSCK bar
HD hold time from CMOSCK bar
t5
t1
t2
13
—
2
3
—
R, G, B input data set-up time to CMOSCK bar t3
R, G, B input data hold time from CMOSCK bar t4
1.5
4.5
3
—
—
R, G, B output data delay from CMOSCK
t5
12
Note: The above timing values are for PECCLK (CMOSCK) = 80MHz and an output pin capacitance of 20pF.
– 9 –
CXD3504R
Description of Operation
1) The following describes only R, but the operation for G and B is the same.
SELRA:SELB = 0:0
SELRA:SELB = 0:1
SELRA:SELB = 1:0
SELRA:SELB = 1:1
However, POLSLA = 0
R2IN → through → R1OUT
R1IN → delay
R2IN → delay
→
→
R2OUT
R1OUT
R1IN → through → R2OUT
R1IN → through → R1OUT
R2IN → delay
R1IN → delay
→
→
R2OUT
R1OUT
R2IN → through → R2OUT
2) Be sure to set XCLR to "0" for a clock or more while HD is "1". (when HDSEL = 0) Also, input the HD signal
with a "0" period length of 6 clocks or more.
Very Little Signal Amplifier (VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C)
Item
Symbol
VIH
Min.
0.4
0
Typ.
—
Max.
3.6
3.2
80
Unit
V
High level input voltage
Low level input voltage
Input frequency
VIL
—
V
f
—
—
MHz
V
1
Input amplitude
Vpp
0.4
—
—
Applicable pins: PECLCK (Pin 2)
1
Input the signal through a capacitor. Also, this amplitude is the value between the through capacitor and the
input pin.
PECLCK
2
– 10 –
CXD3504R
Application Circuit
From CXD2467Q
3.3V
0.1µ
0.1µ
0.1µ
0.1µ
10µ/16V
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
0.1µ
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VDD 88
87
VSS
G1IN9
G1IN8
G1IN7
G1IN6
G1IN5
G1IN4
G1IN3
G1IN2
G1IN1
G1IN0
G2IN9
G2IN8
G2IN7
G2IN6
G2IN5
G2IN4
G2IN3
G2IN2
G2IN1
G2IN0
VDD
R2OUT4
R2OUT3 86
R2OUT2 85
R2OUT1 84
R2OUT0 83
VSS 82
0.1µ
VDD 81
TEST2 80
G1OUT9 79
G1OUT8 78
G1OUT7 77
G1OUT6 76
G1OUT5 75
VSS 74
0.1µ
VDD 73
G1OUT4 72
G1OUT3 71
G1OUT2 70
G1OUT1 69
G1OUT0 68
VSS 67
0.1µ
VDD 66
VSS
0.1µ
G2OUT9 65
G2OUT8 64
G2OUT7 63
G2OUT6 62
G2OUT5 61
VSS 60
B1IN9
B1IN8
B1IN7
B1IN6
B1IN5
B1IN4
B1IN3
B1IN2
B1IN1
B1IN0
B2IN9
B2IN8
B2IN7
B2IN6
B2IN5
B2IN4
B2IN3
B2IN2
B2IN1
B2IN0
VDD
0.1µ
VDD 59
G2OUT4 58
G2OUT3 57
G2OUT2 56
G2OUT1 55
G2OUT0 54
VSS 53
0.1µ
VDD 52
TEST1 51
B1OUT9 50
B1OUT8 49
B1OUT7 48
B1OUT6 47
B1OUT5 46
VSS 45
0.1µ
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
To CXA3197R
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 11 –
CXD3504R
Package Outline
Unit: mm
176PIN LQFP(PLASTIC)
26.0 ± 0.2
24.0 ± 0.2
1.6 MAX
(1.4)
132
89
0.1
133
88
A
176
45
1
44
+ 0.05
0.2 – 0.04
+ 0.07
0.125 – 0.02
0.5
0.1 M
0.1 ± 0.1
0 ° to 10 °
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
42 ALLOY
SONY CODE
EIAJ CODE
LQFP-176P-L061
P-LQFP176-24X24-0.5
JEDEC CODE
PACKAGE MASS
1.8 g
– 12 –
Sony Corporation
相关型号：
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