CXD3519 [SONY]
Reference Voltage and Driver IC for LCD; 参考电压和驱动IC的液晶
| 型号： | CXD3519 |
| 厂家： | 
SONY CORPORATION |
| 描述： | Reference Voltage and Driver IC for LCD |
| 文件： | 总8页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD3519TQ
Reference Voltage and Driver IC for LCD
Description
48 pin TQFP (Plastic)
The CXD3519TQ is suitable IC for applying
reference voltage for gamma correction which is
necessary for TFT liquid crystal display. This IC has
a built-in 9 channels of rail-to-rail buffer circuit which
enables 2-input switch and a common driver circuit.
Features
• Built-in 9 channels of rail-to-rail buffer circuit
• Built-in common driver circuit
• Current consumption: 3.6mA (typ.)
• Package: 48-pin TQFP
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD VSS – 0.3 to +6.0
V
• Input pin voltage
VI VSS – 0.3 to VDD + 0.3 V
• Storage temperature Tstg
• Allowable power dissipation (Ta ≤ 85°C)
220
–55 to +150
°C
Structure
CMOS IC
PD
mW
Applications
Operating Conditions
• Supply voltage
Small liquid crystal monitor
VDD 4.5 to 5.5 (5.0 typ.)
V
• Operating temperature
Topr
–35 to +85
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00Y07-PS
CXD3519TQ
Block Diagram
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
37
38
24
23
GND
GND
V6 39
V5 40
V4 41
NC 42
VDD 43
22 V7
21 V8
20 NC
19 VDD
18 V2
44
45
46
47
48
17
16
15
14
13
V1
V0
V3
GND
VDD
GND
NC
buff
COMOUT
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
– 2 –
CXD3519TQ
Pin Description
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
0.5 to 4.0V
(max.:
1
VH3
VL3
VH2
VL2
VH1
VL1
VH0
VL0
VH8
VL8
VH7
VL7
VH6
VL6
VH5
VL5
VH4
VL4
V0
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
DC input when SW is high.
DC input when SW is low.
V0 output.
2
2.0Vp-p)
3
V
DD
4
5
1
3
5
7
26
6
28
30
32
34
7
VH
8
0.2 to 4.8V
26
27
28
29
30
31
32
33
34
35
45
44
18
39
22
21
17
41
40
2
4
6
8
27
29
31
33
35
VL
GND
0.5 to 4.0V
(max.:
2.0Vp-p)
VDD
V1
V1 output.
V2
V2 output.
17 39
18 40
21 41
22 44
45
0.2 to 4.8V
0.5 to 4.0V
V6
V6 output.
V7
V7 output.
V8
V8 output.
V3
V3 output.
V4
V4 output.
GND
V5
V5 output.
VDD
Input switch.
For V0 to V8 output, VL is
output for low; VH for high.
For COMOUT output, VDD level
is output for low; GND level for
high.
Also, Pins 9 and 10 are
connected internally. Input the
same signal, or input one signal
and leave the other signal open.
9
SW
SW
9
10
10
GND
– 3 –
CXD3519TQ
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VDD
COMOUT 14
14
COMOUT
COM output.
GND
15
19
43
11
16
23
38
46
12
13
20
24
25
36
37
42
47
48
VDD
VDD
VDD
GND
GND
GND
GND
GND
NC
5.0V
5.0V
5.0V
5V power supply.
5V power supply.
5V power supply.
GND.
GND.
GND.
GND.
GND.
No connected.
No connected.
No connected.
No connected.
No connected.
No connected.
No connected.
No connected.
No connected.
No connected.
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note)
• GND
Make sure that Pins 11, 16, 23, 38 and 46 are connected to GND potential, and do not release them.
• Decoupling capacitor
Locate decoupling capacitor connected between power supply and GND as near IC pin as possible.
• Design VH and VL input pins not to have capacity.
– 4 –
CXD3519TQ
Electrical Characteristics
(Ta = 25°C, VDD = 5V)
No.
1
Item
Symbol
ICC
Conditions
Min.
—
Typ.
3.6
—
—
—
—
—
—
—
—
—
—
—
—
Max.
Unit
mA
µA
µA
µA
µA
V/V
V
Current consumption
VH, VL input current high
VH, VL input current low
SW input current high
SW input current low
VREF voltage gain
Input voltage = 2.5V, No load
Input voltage = 4.8V
Input voltage = 0.2V
Input voltage = 5V
6.0
2
IIH
–0.1
–0.1
–10
0.1
3
IIL
0.1
4
IISH
IISL
10
5
Input voltage = 0V
–10
10
6
AV
Input voltage = 0.2 to 4.8V
0.985
2.0
—
7
SW input voltage high
SW input voltage low
VREF output voltage high
VIH
VIL
—
8
—
0.8
—
V
9
VOH
VOL
ISOURCE = 10mA
ISINK = 10mA
VDD – 1.0
—
V
10 VREF output voltage low
GND + 1.0
—
V
11 COMOUT output voltage high VCOH ISOURCE = 10mA
VDD – 0.1
—
V
12 COMOUT output voltage low VCOL
ISINK = 10mA
GND + 0.1
20
V
13 VREF offset voltage
VOFF
—
mV
Input voltage = 0.2 to 4.8V
∆VO1 ISOURCE = 10mA
VREF (V0, 1, 2, 6, 7, 8)
load regulation 1
14
—
±5
±10
mV
ISINK = 10mA
Input voltage = 0.5 to 4.0V
∆VO2 ISOURCE = 10mA
VREF (V3, 4, 5)
15
—
—
±7
±14
10
mV
µs
load regulation 2
ISINK = 10mA
ts1
16
—
Setting time 1
Measurement circuits 1, 2
ts2
ts3
ts4
17
18
—
—
—
6
µs
Setting time 2
Measurement circuit 3
Ω
15
—
Output impedance
Rimp V0 – V8
– 5 –
CXD3519TQ
Measurement Circuits
Measurement circuit 1
VH
VL
4.8V
15Ω
Measurement point
V0, V1, V2,
V6, V7, V8
30nF
0.2V
Measurement circuit 2
VH
VL
4.0V (max.)
15Ω
Measurement point
2.0Vp-p (max.)
V3, V4, V5
30nF
0.5V (min.)
Measurement circuit 3
5.0V
15Ω
Measurement point
V0, COMOUT
30nF
0V
SW
50%
50%
90%
Output (V0 to V8)
10%
ts1
ts2
10%
Output (VCOM)
90%
ts3
ts4
– 6 –
CXD3519TQ
Application Circuit
5V
0.01µ
47µ
36
35
34
33
32
31
30
29
28
27
26
25
37
38
24
23
22
21
20
19
18
17
16
15
14
13
To LCD
To LCD
To LCD
39
40
41
42
43
44
45
46
47
48
To LCD
To LCD
To LCD
To LCD
To LCD
To LCD
0.01µ
buff
47µ
To LCD (VCOM)
1
2
3
4
5
6
7
8
9
10
11
12
Polarity inverted pulse
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 7 –
CXD3519TQ
Package Outline
Unit: mm
48PIN TQFP (PLASTIC)
1.2 MAX
9.0 ± 0.2
7.0 ± 0.1
25
(1.0)
36
0.1
37
24
A
13
48
1
12
+ 0.07
0.125 – 0.02
+ 0.1
0.2 – 0.05
0.5
0.1
M
0.1 ± 0.1
0˚ to 10˚
DETAIL A
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
TQFP-48P-L061
P-TQFP48-7X7-0.5
SOLDER PLATING
COPPER ALLOY
0.15g
JEDEC CODE
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
LEAD TREATMENT
SPEC.
COPPER ALLOY
Sn-Pb 10%
LEAD TREATMENT THICKNESS 5-18µm
Sony Corporation
– 8 –
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