CXD3508TQ [SONY]
LCD Interface IC; LCD接口IC
| 型号： | CXD3508TQ |
| 厂家： | 
SONY CORPORATION |
| 描述： | LCD Interface IC |
| 文件： | 总18页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD3508TQ
LCD Interface IC
For the availability of this product, please contact the sales office.
Description
100 pin TQFP (Plastic)
The CXD3508TQ is a LCD interface IC for the color
LCD module ACX704AKM driver.
Features
• Generates the color LCD module ACX704AKM drive
pulse.
• Standby mode function
• Thin package (100-pin TQFP)
Applications
PDA, compact LCD monitor, etc.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
Vss – 0.3 to +5.5
Vss – 0.3 to VDD + 0.3
Vss – 0.3 to VDD + 0.3
–25 to +75
V
V
VO
V
• Operating temperature Topr
• Storage temperature Tstg
°C
°C
–55 to +150
Recommended Operating Conditions
• Supply voltage
• Operating temperature Topr
VDD
3.0 to 3.6
V
–10 to +60
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00228-PS
CXD3508TQ
Block Diagram
9
8
7
6
R0
R1
R2
R3
31 to 28
R01, R11, R21, R31
43 to 41
94 to 97
82 to 89
35 to 32
47 to 44
90 to 93
78 to 81
39 to 36
XR01, XR11, XR21, XR31
R02, R12, R22, R32
13
12
11
10
G0
G1
G2
G3
XR02, XR12, XR22, XR32
G01, G11, G21, G31
DATA IN
Serial/
XG01, XG11, XG21, XG31
G02, G12, G22, G32
Parallel
Conversion
Block
B0 17
B1 16
B2 15
XG02, XG12, XG22, XG32
B01, B11, B21, B31
53, 52,
49, 48
B3
14
XB01, XB11, XB21, XB31
B02, B12, B22, B32
24
FA
86 to 89
72 to 74,
77
XB02, XB12, XB22, XB32
20
MCK
PCI 21
27
Power CTR.
PCO
64
65
66
67
HST1
18
22
Hsync/DENB
H Counter
XHST1
HST2
Delay
Delay
SLIN
XHST2
60
61
62
HCK1
XHCK1
HCK2
H Timing Pulse GEN.
63 XHCK2
OE1
68
69
70
71
XOE1
OE2
19
V sync
V Counter
XOE2
54
55
VST
XVST
58 VCK
V Timing Pulse GEN.
59 XVCK
56
57
ENB
XENB
98
FRP
Timing Generator Block
– 2 –
CXD3508TQ
Pin Configuration
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
50
VDD
XB32
XG02
XG12
XG22
XG32
XR02
XR12
XR22
XR32
VDD
49 XB21
48 XB31
47 XG01
46 XG11
45 XG21
44 XG31
43 XR01
42 XR11
41 XR21
B02 86
B12 87
B22 88
B32 89
G02 90
G12 91
G22 92
G32 93
R02 94
R12 95
R22 96
R32 97
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
XR31
B01
B11
B21
B31
G01
G11
G21
G31
R01
R11
R21
R31
PCO
VDD
FRP
TESTV
VDD
98
99
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
– 3 –
CXD3508TQ
Pin Description
Pin
No.
Input pin for
open status
Symbol
I/O
Description
1
VSS
—
I
GND
—
1
2
TEST1
TEST2
VSS
Test signal input
Test signal input
GND
DWN
1
3
I
DWN
4
—
I
—
2
5
CLR
R3
System reset
UP
6
I
Red signal input (MSB)
Red signal input
Red signal input
Red signal input (LSB)
Green signal input (MSB)
Green signal input
Green signal input
Green signal input (LSB)
Blue signal input (MSB)
Blue signal input
Blue signal input
Blue signal input (LSB)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
R2
I
8
R1
I
9
R0
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
G3
I
G2
I
G1
I
G0
I
B3
I
B2
I
B1
I
B0
I
Hsync/DENB
Vsync
MCK
PCI
I
Hsync/data enable pulse input
Vsync pulse input
I
I
Dot clock input
I
Power control signal input
Sync input signal mode switch
Test signal input
1
SLIN
TESTP
FA
I
DWN
1
I
DWN
1
I
Data phase adjustment
GND
DWN
VSS
—
—
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
VDD
Power supply
PCO
R31
R21
R11
R01
G31
G21
Power control signal output
Red signal output
Red signal output
Red signal output
Red signal output
Green signal output
Green signal output
1
2
Built-in pull-down resistor (82.5kΩ)
Built-in pull-up resistor (82.5kΩ)
– 4 –
CXD3508TQ
Pin
No.
Input pin for
open status
Symbol
G11
I/O
Description
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Green signal output
Green signal output
Blue signal output
Blue signal output
Blue signal output
Blue signal output
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
G01
B31
B21
B11
B01
XR31
XR21
XR11
XR01
XG31
XG21
XG11
XG01
XB31
XB21
VDD
Red signal output (inverse)
Red signal output (inverse)
Red signal output (inverse)
Red signal output (inverse)
Green signal output (inverse)
Green signal output (inverse)
Green signal output (inverse)
Green signal output (inverse)
Blue signal output (inverse)
Blue signal output (inverse)
Power supply
VSS
GND
XB11
XB01
VST
Blue signal output (inverse)
Blue signal output (inverse)
VST pulse output
XVST
ENB
VST pulse output (inverse)
ENB pulse output
XENB
VCK
ENB pulse output (inverse)
VCK pulse output
XVCK
HCK1
XHCK1
HCK2
XHCK2
HST1
XHST1
HST2
XHST2
VCK pulse output (inverse)
HCK1 pulse output
HCK1 pulse output (inverse)
HCK2 pulse output
HCK2 pulse output (inverse)
HST1 pulse output
HST1 pulse output (inverse)
HST2 pulse output
HST2 pulse output (inverse)
– 5 –
CXD3508TQ
Pin
No.
Input pin for
open status
Symbol
OE1
I/O
Description
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
OE1 pulse output
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XOE1
OE2
XOE2
XB02
XB12
XB22
VSS
OE1 pulse output (inverse)
OE2 pulse output
OE2 pulse output (inverse)
Blue signal output (inverse)
Blue signal output (inverse)
Blue signal output (inverse)
GND
VDD
Power supply
XB32
XG02
XG12
XG22
XG32
XR02
XR12
XR22
XR32
B02
Blue signal output (inverse)
Green signal output (inverse)
Green signal output (inverse)
Green signal output (inverse)
Green signal output (inverse)
Red signal output (inverse)
Red signal output (inverse)
Red signal output (inverse)
Red signal output (inverse)
Blue signal output
B12
Blue signal output
B22
Blue signal output
B32
Blue signal output
G02
Green signal output
G12
Green signal output
G22
Green signal output
G32
Green signal output
R02
Red signal output
R12
Red signal output
R22
Red signal output
R32
Red signal output
FRP
TESTV
VDD
Polarity inversion pulse signal output
Test signal input
1
DWN
—
Power supply
—
1
Built-in pull-down resistor (82.5kΩ)
– 6 –
CXD3508TQ
Electrical Characteristics
DC Characteristics
(VDD = 3.0 to 3.6V, Ta = –25 to + 75°C)
Item
Symbol
Applicable pins
—
Conditions
—
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
Supply voltage
VDD
VDD
No load, Ta = 25°C,
DD = 3.3V,
MCK: 5.58MHz
Current
consumption
IDD
V
0.9
mA
V
VIH1
VIL1
2.0
LVTTL input
cell
Input voltage 1
Input voltage 2
MCK
0.8
2.0
Vt+
LVTTL
Schmitt trigger
input cell
All output pins excluding
MCK
V
Vt–
0.5
0.2
Vt+ – Vt–
R0, R1, R2, R3, G0, G1,
G2, G3, B0, B1, B2, B3,
Hsync/DENB, Vsync,
MCK, PCI
| IIL1 |
| IIH1 |
VI = 0V
1.0
1.0
µA
Input current 1
VI = VDD
VI = 0V
10
100
3.0
| IIL2 |
| IIH2 |
µA
µA
V
Input current 2
Input current 3
CLR
VI = VDD
TEST1, TEST2,
SLIN, TESTV, FA,
TESTP
VI = 0V
3.0
| IIL3 |
| IIH3 |
VI = VDD
10
100
0.2
IOL1 = 0.75mA
VOL1
VOH1
Output voltage
1
ENB, XENB
IOH1 = –0.50mA
V
DD – 0.2
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
VOL2
0.2
IOL2 = 1.5mA
Output voltage
2
V
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32,
PCO, VST, XVST, VCK,
XVCK, OE1, XOE1, OE2,
XOE2, FRP
VOH2
IOH2 = –1.0mA
V
DD – 0.2
0.2
0.2
VOL3
VOH3
VOL4
VOH4
IOL3 = 3.0mA
IOH3 = –2.0mA
IOL4 = 4.5mA
IOH4 = –3.0mA
HST1, XHST1,
HST2, XHST2
Output voltage
3
V
V
V
DD – 0.2
DD – 0.2
HCK1, XHCK1,
HCK2, XHCK2
Output voltage
4
V
– 7 –
CXD3508TQ
AC Characteristics
(VDD = 3.0 to 3.6V, Ta = –10 to +60°C)
Item
Symbol
Applicable pins
Conditions
Min.
Typ.
Max.
Unit
ns
HCK1, HCK2, XCHK1,
XHCK2, HST1, HST2,
XHST1, XHST2
HCK, HST
time difference
∆tHST-HCKU
∆tHST-HCKD
2
15
R01, R11, R21, R31,
R02, R12, R22, R32,
Data output
rise time
GND – VDD
(0 – 90%)
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
40
40
t
RD
FD
G02, G12, G22, G32,
ns
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
Data output
fall time
VDD – GND
(100 – 10%)
t
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
H pulse output
rise time
GND – VDD
(0 – 90%)
HCK1, HCK2,
XCHK1, XHCK2,
HST1, HST2,
tRHP
tFHP
tRVP
tFVP
tREP
t
FEP
30
30
60
60
80
80
ns
ns
ns
H pulse output
fall time
VDD – GND
(100 – 10%)
XHST1, XHST2
V pulse output
rise time
GND – VDD
(0 – 90%)
VCK, XVCK,
VST, XVST,
OE1, OE2, XOE1,
XOE2, FRP, PCO
VDD – GND
(100 – 10%)
V pulse output
fall time
ENB pulse
output rise time
GND – VDD
(0 – 90%)
ENB, XENB
ENB pulse
output fall time
VDD – GND
(100 – 10%)
HCK1, HCK2, XHCK1,
XHCK2, R01, R11, R21,
R31, R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31, G02,
G12, G22, G32, XG01,
XG11, XG21, XG31,
HCK1, HCK2,
XHCK1, XHCK2,
DATA
3
35
48
50
50
120
ns
%
t
STP
setup time
XG02, XG12, XG22,
XG32, B01, B11, B21,
B31, B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
dHCK
dVCK
HCK1, HCK2, XHCK1,
XHCK2, VCK, XVCK
4
HCK, VCK duty
52
1
CL of each output pin is shown below.
• R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11,
G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21,
B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, ENB, XENB: CL = 70pF
• HCK1, HCK2, XHCK1, XHCK2
• HST, XHST, VCK, XVCK
• VST, XVST
: CL = 150pF
: CL = 100pF
: CL = 85pF
• OE1, XOE1, OE2, XOE2, PCO, FRP : CL = 60pF
The absolute value of time difference (HST1, XHST1, HCK1, XHCK1) is within 15ns.
In the same manner, the absolute value of time difference (HST2, XHST2, HCK2, XHCK2) is within 15ns.
2
3
4
t
STP: tST1D, tST1U, tST2D, tST2U
dHCK = (tHH/(tHH + tHL)) × 100, dVCK = (tVH/(tVH + tVL)) × 100
– 8 –
CXD3508TQ
Timing Definition
H system
tHH
tHL
VDD
HCK1
50%
50%
50%
GND
VDD
50%
XHCK1
GND
VDD
∆tH
∆tH
HCK2
50%
50%
50%
GND
VDD
50%
50%
XHCK2
GND
∆tH
∆tH
VDD
HST1
50%
50%
(HST2)
GND
VDD
50%
XHST1
50%
(XHST2)
GND
VDD
HCK1
(HCK2)
50%
50%
50%
50%
GND
VDD
XHCK1
(XHCK2)
GND
∆tHST-HCKU
∆tHST-HCKD
– 9 –
CXD3508TQ
V system
tVH
tVL
VDD
VCK
50%
50%
50%
GND
VDD
50%
50%
XVCK
GND
∆tV
∆tV
DATA
VDD
HCK1
50%
50%
GND
VDD
50%
50%
XHCK1
GND
VDD
HCK2
50%
50%
GND
VDD
50%
XHCK2
GND
VDD
DATA
GND
tST1D
tST2D
tST1U
tST2U
tSTX1U
tSTX2U
tSTX1D
tSTX2D
– 10 –
CXD3508TQ
PCI, PCO
These pins control to turn power on/off of the ACX704AKM and the CXD2475TQ when the LCD is turned
on/off.
Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM and the CXD2475TQ.
• When LCD is on, effective screen is displayed after entire white display (2 fields).
• When LCD is off, LCD is off after entire white display.
Power Up Sequence
VDD
VDD
0
VDD
CLR
0
Inactive (low)
Inactive (low)
PCI
Active
Active
PCO
Inactive (low)
Inactive (low)
Pulse
Active
White Data
2 Fields
Valid
DATA (out)
MCK
Hsync
Vsync
DENB
DATA (in)
Invalid (low)
Valid
1 Field (typ.) 288H (min.)
Power Down Sequence (Standby)
Standby Mode
Inactive (low)
Active (high)
Inactive (low)
PCI
Active (high)
PCO
VDD
0
VDD
Invalid (all low)
Invalid (all low)
Valid
Valid
White Data
DATA
Pulse
Vsync
DENB
3 Fields
10 Fields
HST1, HST2, XHST1, XHST2, HCK1, HCK2, XHCK1, XHCK2, VST, XVST, VCK, XVCK,
ENB. XENB, OE1, XOE1, OE2, XOE2, FRP
– 11 –
CXD3508TQ
FA
This is a selector switch for phase relationship between data and other pulses.
(Normally, set to low.)
MCK
HCK1
XHCK1
HCK2
XHCK2
OUTPUT DATA
R/G/B 01 to 31
Invalid
Invalid
2
1
4
3
6
5
8
7
(FA: L)
Default
OUTPUT DATA
R/G/B 02 to 31
OUTPUT DATA
R/G/B 01 to 31
Invalid
Invalid
2
1
4
3
6
5
8
7
(FA: H)
OUTPUT DATA
R/G/B 02 to 31
SLIN
This is a selector switch for input sync signal mode.
SLIN: LOW → Hsync + Vsync Mode
SLIN: HIGH → DENB ONLY Mode (Vsync input is invalid.)
– 12 –
CXD3508TQ
– 13 –
CXD3508TQ
– 14 –
CXD3508TQ
0 2 3
9 1 3
8 1 3
7 1 3
6 1 3
t u p n I
t u p t u O
– 15 –
CXD3508TQ
t u p n I
t u p t u O
– 16 –
CXD3508TQ
Application Circuit
To ACX704AKM
VDD
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
VDD
VDD 50
XB21 49
XB31 48
XG01 47
XG11 46
XG21 45
XG31 44
XR01 43
XR11 42
XB32
XG02
XG12
XG22
XG32
XR02
XR12
XR22
85 XR32
86 B02
87 B12
88 B22
89 B32
90 G02
91 G12
92 G22
93 G32
94 R02
95 R12
96 R22
97 R32
98 FRP
XR21
XR31
B01
B11
B21
B31
G01
G11
G21
G31
R01
R11
R21
R31
PCO
VDD
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TESTV
VDD
99
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDD
To DC-DC Converter
Input
To CXD2475TQ
(Pins 9, 10)
VDD
Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM
and the CXD2475TQ.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 17 –
CXD3508TQ
Package Outline
Unit: mm
TQFP-100P-L111
1.2 MAX
1.0 ± 0.1
16.0 ± 0.3
14.0 ± 0.2
0.4375
0.1
75
51
76
50
A
26
100
1
25
0.5
0.2 ± 0.06
0.08
M
0.1 ± 0.1
0 ° to 10 °
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
SOLDER PLATING
TQFP-100P-L111
EIAJ CODE
P-TQFP100-14X14-0.5
42ALLOY
0.6g
JEDEC CODE
PACKAGE WEIGHT
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Sony Corporation
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