PI3VDP411LSAZBE [DIODES]
Consumer Circuit, 7 X 7 MM, GREEN, MO-220, TQFN-48;
| 型号： | PI3VDP411LSAZBE |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Consumer Circuit, 7 X 7 MM, GREEN, MO-220, TQFN-48 商用集成电路 |
| 文件： | 总13页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Features
Description
ꢀÎConverts low-swing AC coupled differential input to
HDMI™ rev 1.3 compliant open-drain current steering Rx
terminated differential output
Pericom Semiconductor’s PI3VDP411LSA provides the ability
to use a Dual-mode DisplayPort™ transmitter in HDMI™ mode.
is flexibility provides the user a choice of how to connect to
their favorite display. All signal paths accept AC coupled video
signals. e PI3VDP411LSA converts this AC coupled signal into
an HDMI rev 1.3 compliant signal with proper signal swing. is
conversion is automatic and transparent to the user.
ꢀÎHDMI Level shiꢀing operation up to 2.5Gbps per lane
(250MHz pixel clock)
ꢀÎIntegrated 50-ohm termination resistors for AC-coupled
differential inputs.
Output squelch function is provided for each channel. When out-
put channel is enable (OE#=0) and operating, that TMDS pixel
clock input signal determines whether the output is enabled.
When no TMDS pixel clock is present, TMDS output channel
will be disabled.
ꢀÎProvide Output Squelch function to turn off TMDS
common mode output buffer when TMDS clock is not
present
ꢀÎEnable/Disable feature to turn off TMDS outputs to enter
low-power state.
e PI3VDP411LSA supports up to 2.5Gbps, which provides 12-
bits of color depth per channel, as indicated in HDMI rev 1.3.
ꢀÎOutput slew rate control on TMDS outputs to minimize
EMI
ꢀÎIntegrated Active / Passive DDC level shiꢀers (3.3V source
to 5V sink)
ꢀÎTransparent operation: no re-timing or configuration
required
Pin Configuration (48-Pin TQFN)
ꢀÎLevel shiꢀer for HPD signal from HDMI/DVI connector
ꢀÎIntegrated pull-down on HPD_SINK input guarantees
"input low" when no display is plugged in
ꢀÎ3.3V Power supply required
ꢀÎTMDS output enable control
ꢀÎESD protection on all I/O pins
à 4kV HBM
8kV contact ESD protection on the following pins
→ OUT_Dx
→ SDA_SINK, SCL_SINK
→ HPD_SINK
ꢀÎPackaging (Pb-free & Green available):
25
24
36
35
33
29 28 27
26
34
32
31
30
GND
IN_D1-
IN_D1+
VDD
37
GND
23
22
38
39
OUT_D1-
OUT_D1+
VDD
21
20
19
18
40
41
42
43
à
IN_D2-
IN_D2+
GND
OUT_D2-
OUT_D2+
GND
GND
IN_D3-
IN_D3+
VDD
OUT_D3-
OUT_D3+
VDD
17
16
15
14
13
44
45
46
47
48
à 48 TQFN, 7mm × 7mm (ZBE)
IN_D4-
IN_D4+
OUT_D4-
OUT_D4+
12
1
2
8
9
10
11
3
4
5
6
7
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PS9059A
07/28/12
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Block Diagram
OE#
0V
OUT_D4/3/2/1+
OUT_D4/3/2/1-
50Ω
50Ω
IN_D4/3/2/1+
IN_D4/3/2/1-
Rx
SR1/0
SQSEL
Control
Logic
DDC_EN (0V to 3.3V)
DDCBSEL
SDA_SOURCE
SDA_SINK
SCL_SINK
HPD_SINK
SCL_SOURCE
HPD_SOURCE
HPD
100KΩ
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Pin Description
Pin
Name
I/O Type Descriptions
1, 5, 12, 18, 24,
27, 31, 36, 37, 43
GND
VDD
POWER
POWER
GROUND
2, 11, 15, 21, 26,
33, 40, 46
POWER, 3.3V 10%
Slew Rate Control. Acceptable connections to SRx pin are: resistor to 3.3V or
short to GND. (internal 200KΩ pull-LOW)
3, 4
6, 35
7
SR0, SR1
NC
I
O
O
No Connect
HPD_SOURCE: 0V to 3.3V (nominal) output signal. HPD_Sink input can be as
high as 5V and then HPD_Source will output no higher than 3.3V.
HPD_SOURCE
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
DDC_EN
Low
DDCBSEL DDC level shiꢀer type
X
DISABLE DDC level shiꢀer
Passive level shiꢀer ENABLE
8
SDA_SOURCE
I/O
High
High
Low
Connected to SDA_SINK through voltage-
limiting integrated NMOS passgate
Active level shiꢀer ENABLE
High
Connected to SDA_SINK through bi-direc-
tion buffer
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
DDC_EN
Low
DDCBSEL DDC level shiꢀer type
X
DISABLE DDC level shiꢀer
Passive level shiꢀer ENABLE
9
SCL_SOURCE
I/O
High
High
Low
Connected to SCL_SINK through voltage-
limiting integrated NMOS passgate
Active level shiꢀer ENABLE
Connected to SCL_SINK through bi-direction
buffer
High
Active DDC level shiꢀer enable pin. (internal 200KΩ pull-LOW)
DDCBSEL
Low (0V)
DDC path
10
DDCBSEL
I
Passive DDC level shiꢀer
Active DDC level shiꢀer
High (3.3V)
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output
signal with OUT_D4-.
13
14
16
17
OUT_D4+
OUT_D4-
OUT_D3+
OUT_D3-
O
O
O
O
HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output
signal with OUT_D4+
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output
signal with OUT_D3-.
HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output
signal with OUT_D3+
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PS9059A
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Pin
Name
I/O Type Descriptions
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output
signal with OUT_D2-.
19
OUT_D2+
O
HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output
20
22
23
OUT_D2-
OUT_D1+
OUT_D1-
O
signal with OUT_D2+
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output
signal with OUT_D1-.
O
HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output
signal with OUT_D1+
O
Enable for level shiꢀer path.
OE#
IN_D Termination
> 100KΩ
OUT_D Outputs
High-Z
25
OE#
I
1
0
50Ω
Active
5V DDC Clock I/O. Pulled up by external termination to 5V.
DDC_EN
Low
DDCBSEL DDC level shiꢀer type
X
DISABLE DDC level shiꢀer
Passive level shiꢀer ENABLE
28
SCL_SINK
I/O
High
High
Low
Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate
Active level shiꢀer ENABLE
Connected to SCL_SOURCE through bi-
direction buffer
High
5V DDC Data I/O. Pulled up by external termination to 5V.
DDC_EN
Low
DDCBSEL DDC level shiꢀer type
X
DISABLE DDC level shiꢀer
Passive level shiꢀer ENABLE
29
SDA_SINK
I/O
High
High
Low
Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate
Active level shiꢀer ENABLE
Connected to SDA_SOURCE through bi-
direction buffer
High
Low Frequency, 0V to 5V (nominal) input signal. is signal comes from the
TMDS connector. Voltage High indicates “plugged” state; voltage low indicated
“unplugged”. HPD_SINK is pulled down by an integrated 100K ohm pull-down
resistor.
30
32
HPD_SINK
DDC_EN
I
I
Enables DDC level shiꢀer path
DDC_EN
Low (0V)
Passgate
Disable
Enable
High (3.3V)
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Pin
Name
I/O Type Descriptions
TMDS clock detection setting
Pulled up by external termination to 3.3V or short to GND.
SQSEL Clock Monitor Pin
Device monitor HDMI pixel clock on Pin38/39
(Channel IN_D1 )
34
SQSEL
I
0
1
Device monitor DVI pixel clock on Pin 47/48
(Channel IN_D4 )
Low-swing diff input from DP Tx outputs. IN_D1- makes a differential pair
with IN_D1+.
38
39
41
42
44
45
47
48
IN_D1-
IN_D1+
IN_D2-
IN_D2+
IN_D3-
IN_D3+
IN_D4-
IN_D4+
I
I
I
I
I
I
I
I
Low-swing diff input from DP Tx outputs. IN_D1+ makes a differential pair
with IN_D1-.
Low-swing diff input from DP Tx outputs. IN_D2- makes a differential pair
with IN_D2+.
Low-swing diff input from DP Tx outputs. IN_D2+ makes a differential pair
with IN_D2-.
Low-swing diff input from DP Tx outputs. IN_D3- makes a differential pair
with IN_D3+.
Low-swing diff input from DP Tx outputs. IN_D3+ makes a differential pair
with IN_D3-.
Low-swing diff input from DP Tx outputs. IN_D4- makes a differential pair
with IN_D4+.
Low-swing diff input from DP Tx outputs. IN_D4+ makes a differential pair
with IN_D4-.
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PS9059A
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Truth Table (Slew Rate control function)
SR1
SR0
Rise/Fall Time (Typ)
1
1
0
0
1
0
1
0
140ps
130ps
120ps
110ps
Test Setup Condition
VDD = 3.3V, Ambient temperature 25°C
Rise/Fall time is from 20% to 80% on Rising/Falling edge
Date rate: 620 Mbps
Input: 1V differential peak-to-peak clock pattern
Equalization : 3dB
Table 1: OE Pin Description
OE#
Device State
Comments
Differential input buffers and output buffers
enabled. Input impedance = 50Ω
Normal functioning state for IN_D to OUT_D
level shiꢀing function.
Asserted (low voltage)
Low-power state.
Intended for lowest power condition when:
à Differential input buffers and termination
are disabled.
à No display is plugged in or
à e level shiꢀed data path is disabled
HPD_SINK input and HPD_SOURCE
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions
are not affected by OE#
à Differential inputs are in a high
impedance state.
à OUT_D level-shiꢀing outputs are
disabled.
à OUT_D level-shiꢀing outputs are in high
impedance state.
à Internal bias currents are turned off.
Unasserted (high voltage)
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Absolute Maximum Ratings (Over operating free-air temperature range)
Item
Rating
Supply Voltage to Ground Potential
5.5V
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
150°C
Junction Temperature
Soldering Temperature
260°C
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Electrical Characteristics
Table: Power Supplies and Temperature Range
Symbol
VDD
Parameter
Min Typ Max Units
Comments
3.3V Power supply
Max Current
3.0
3.3
3.6
V
100
mA
ICC
Supply Current when no
TMDS clock present
8
mA
ICC_squelch
ICCQ
Standby Current
2
mA
OE# = HIGH
Case temperature range
for operation with spec.
-40
85
Celsius (°)
TCASE
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Table: Differential Input Characteristics ꢀorIN_Dx signals
Symbol
Parameter
Min Typ Max Units
Comments
Tbit is determined by the display mode. Nominal
bit rate ranges from 250Mbps to 2.5Gbps per lane.
Nominal Tbit at 2.5 Gbps = 400 ps. 360ps = 400ps-
10%
UI, Unit Interval
360
ps
Tbit
Input Differential Volt-
age Level
0.175
0.8
1.200
V
See note 1 below
VRX_DIFF
TRX_EYE
VCM-ACp-p
ZRX_DC
Minimum Eye Width at
IN_D input pair
Tbit
mV
Ω
AC Peak Common
Mode Input Voltage
100
60
See note 2 below
Required IN_D+ as well as IN_D- DC impedance
(50 20% tolerance).
40
0
50
Intended to limit power-up stress on chipset's PCIE
output buffers.
2.0
V
ZRX-Bias
Differential inputs must be in a high impedance
state when OE# is HIGH.
100
k Ω
ZRX_HIGH-Z
1. V
= 2x|V
V
| Applies to IN_Dx signals
RX-DIFF
RX-D- - RX-D-
2. V
= |V
- - V -|/2 - V
RX-D RX-CM-DC
CM-AC-p-p
RX-D
V
= DC(avg) oꢀ |V
+ V
-|/2
RX-CM-DC
RX-D+
RX-D
V
includes all ꢀrequencies above 30 kHz.
CM-AC-p-p
TMDS Outputs
e level shiꢀer's TMDS outputs are required to meet HDMI 1.3 specifications.
e HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3
specification.
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Table 2: Differential Output Characteristics ꢀor TMDS_OUT signals
Symbol
Parameter
Min
Typ
Max
Units Comments
VDD is the DC termination voltage
in the HDMI or DVI Sink. VDD is
nominally 3.3V
Single-ended high
level output voltage
V
VH
VDD-10mV VDD
VDD+10mV
Single-ended low level
output voltage
e open-drain output pulls down
V
VL
VDD-600mV VDD-500mV VDD-400mV
from VDD
.
Single ended output
swing voltage
Swing down from TMDS termina-
tion voltage (3.3V 10%)
425
500
600
50
mV
VSWING
Measured with TMDS outputs
pulled up to VDD Max _(3.6V)
through 50Ω resistors.
Single-ended current
in high-Z state
µA
ps
IOFF
is differential skew budget is in
addition to the skew presented be-
tween D+ and D- paired input pins.
HDMI revision 1.3 source allowable
Intra-pair differential
skew
30
TSKEW-INTRA
intrapair skew is 0.15 Tbit
.
is lane-to-lane skew budget is in
addition to skew between differen-
tial input pairs
Inter-pair lane-to-lane
output skew
100
25
ps
ps
TSKEW-INTER
Jitter budget for TMDS signals as
they pass through the level shiꢀer.
25ps = 0.056 at 2.25 Gbps
Jitter added to TMDS
signals
TJIT
TMDS output oscillation elimination
e inputs already incorporate a squelch circuit. erefore, nothing is needed from application standpoint to eliminate TMDS output
oscillation when there is no TMDS input present. e IC will do this automatically.
Table 3: HPD Characteristics
Symbol
Parameter
Min
Typ
Max
Units Comments
Low-speed input changes state on cable plug/
unplug
Input High Level
2.0
5.0
5.3
V
VIH-HPD
HPD_SINK Input Low
Level
0
0.8
70
V
VIL-HPD
IIN-HPD
VOH-HPD
VOL-HPD
HPD_SINK Input Leakage
Current
Measured with HPD_SINK at VIH-HPD max
and VIL-HPD min
µA
VDD = 3.3V 10%
HPD_source Output
High-Level
2.5
0
V
V
VDD
0.4
IOH = -4mA(MIN) / -8mA(MAX)
HPD_source Output Low-
Level
IOL = 4mA(MIN) / 8mA(MAX)
Time from HPD_SINK changing state to
HPD_source changing state. Includes HPD_
source rise/fall time
HPD_SINK to HPD_
200
20
ns
ns
THPD
source propagation delay
Time required to transition from VOH- HPDB
to VOL-HPDB or from VOL-HPDB to VOH-HPDB
HPD_source rise/ fall time
1
TRF-HPDB
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Table 4: OE# Input, SQSEL and DDC_EN
Symbol
Parameter
Min
2.0
0
Typ
Max
Units Comments
TMDS enable input changes state on cable
plug/unplug
Input High Level
Input Low Level
Input Leakage Current
V
VIH
VIL
IIN
VDD
0.8
10
V
Measured with input at VIH-EN max and
VIL-EN min
µA
Table 5: Termination Resistor
Symbol
Parameter
Min
Typ
Max
Units Comments
HPD_SINK input pull-
down resistor.
Guarantees HPD_SINK is LOW when no
display is plugged in.
100K
Ω
RHPD
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Packaging Mechanical: 48-Pin TQFN (ZB)
UNIT: mm
DATE: 02/11/09
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
PACKAGE CODE: ZB48
REVISION: A
DOCUMENT CONTROL #: PD-2080
09-0091
Note:
1.For latest package inꢀo, please check: http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics
2.e exposed die paddle size is 3.6x3.6mm ꢀor PI3VDP411LSAZBE
3. Pad size (D2 * E2) is 157 x 157 mm
Pericom Semiconductor Corporation • 1-800-435-2336
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PS9059A
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All trademarks are property of their respective owners.
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Related Products
Part Number
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DisplayPort 1.2 Re-driver with built-in AUX listener
Dual Mode DisplayPort to HDMI Level Shiꢀer and Re-driver
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2-Lane DisplayPort1.2 Compliant Switch
4-Lane DisplayPort1.2 Compliant Switch
1:2 Active 3.4Gbps HDMI1.4 compliant Splitter/Re-driver
2:1 3.4Gbps HDMI1.4 Switch/Re-driver with built-in ARC and Fast Switching support for Sink Application
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Reference Information
Document
Description
VESA DisplayPort Standard Version 1 Revision 2, Video Electronics Standards Association, January 5, 2010
VESA DisplayPort Dual-Mode Standard Version 1, Video Electronics Standards Association, February 10,
2012
VESA
VESA DisplayPort Interoperability Guideline Version 1.1a, Video Electronics Standards Association, Febru-
ary 5, 2009
HDMI
High-Definition Multimedia Interface Specification Version 1.4, HDMI Licensing, LLC, June 5, 2009
Ordering Information
Ordering Code
Package Code Package Type
PI3VDP411LSAZBE
ZB
Pb-free & Green, 48-pin TQFN
1. ermal characteristics can be ꢀound on the company web site at www.pericom.com/packaging/
2. E = Pb-ꢀree and Green
3. Adding an X suffix = Tape/Reel
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifer)
Revision History
Date
Changes
Actual pad size 157 x 157 mil in package drawing
7/28/2012
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PS9059A
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