PI3VDP411LSTRZBE [PERICOM]
Consumer Circuit, 7 X 7 MM, GREEN, MO-220, TQFN-48;
| 型号： | PI3VDP411LSTRZBE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Consumer Circuit, 7 X 7 MM, GREEN, MO-220, TQFN-48 商用集成电路 |
| 文件： | 总10页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Features
Description
Î Converts low-swing AC coupled differential input to
HDMI™ rev 1.3 compliant open-drain current steering Rx
terminated differential output
Pericom Semiconductor’s PI3VDP411LSTR provides the ability
to use a Dual-mode DisplayPort™ transmitter in HDMI™ mode.
is flexibility provides the user a choice of how to connect to
their favorite display. All signal paths accept AC coupled video
signals. e PI3VDP411LSTR converts this AC coupled signal
into an HDMI rev 1.3 compliant signal with proper signal swing.
is conversion is automatic and transparent to the user.
Î HDMI Level shiꢀing operation up to 2.5Gbps per lane
(250MHz pixel clock)
Î Integrated 50-ohm termination resistors for AC-coupled
differential inputs.
Î Enable/Disable feature to turn off TMDS outputs to enter
e PI3VDP411LSTR supports up to 2.5Gbps, which provides
12-bits of color depth per channel, as indicated in HDMI rev 1.3.
low-power state.
Î Output slew rate control on TMDS outputs to minimize
EMI
Î Integrated Passive DDC level shiꢀers (3.3V source to 5V
sink)
Î Transparent operation: no re-timing or configuration
required
Î Inverted Level shiꢀer for HPD signal from HDMI/DVI
connector
Î Integrated pull-down on HPD_sink input guarantees "input
Pin Configuration (48-Pin TQFN)
low" when no display is plugged in
Î 3.3V Power supply required
Î TMDS output enable control
Î ESD protection on all I/O pins
à 4kV HBM
8kV contact ESD protection on the following pins
→ OUT_Dx
→ SDA_SINK, SCL_SINK
→ HPD_SINK
Î Packaging (Pb-free & Green available):
25
24
36
35
33
29 28 27
26
34
32
31
30
GND
IN_D1-
IN_D1+
VDD
37
GND
23
22
38
39
OUT_D1-
OUT_D1+
VDD
à
21
20
19
18
40
41
42
43
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
GND
GND
GND
à 48 TQFN, 7mm × 7mm (ZBE)
17
16
15
14
13
IN_D3-
IN_D3+
44
45
46
47
48
OUT_D3-
OUT_D3+
VDD
VDD
IN_D4-
IN_D4+
OUT_D4-
OUT_D4+
12
1
2
8
9
10
11
3
4
5
6
7
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PS9113
08/23/11
11-0084
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Block Diagram
OE#
0V
OUTx_D4+
OUTx_D4-
50Ω
50Ω
50Ω
50Ω
50Ω
INx_D4+
INx_D4-
Rx
Rx
Rx
Rx
0V
OUTx_D3+
OUTx_D3-
50Ω
INx_D3+
INx_D3-
0V
OUTx_D2+
OUTx_D2-
50Ω
INx_D2+
INx_D2-
0V
OUTx_D1+
OUTx_D1-
50Ω
INx_D1+
INx_D1-
SR0
SR1
HPD_SOURCE#
HPD
HPD_SINK
100KΩ
DDC_EN (0V to 3.3V)
SDA_Source
SDA_Sink
SCL_Sink
SCL_Source
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Pin Description
Pin
Name
I/O Type
Descriptions
1, 5, 12, 18, 24, 27,
31, 36, 37, 43
GND
POWER
GROUND
2, 11, 15, 21, 26, 33,
40, 46
POWER
I
POWER, 3.3V 10%
VDD
SR0
Slew Rate Control. Acceptable connections to SR0 pin are: resistor
to 3.3V or short to GND. (internal 200KΩ pull-LOW)
3
Slew Rate Control. Acceptable connections to SR1 pin are: resistor
to 3.3V or short to GND. (internal 200KΩ pull-LOW)
4
SR1
NC
I
6, 10, 34, 35
O
No Connect
HPD_SOURCE#: 0V to 1.0V (nominal) output signal. HPD_Sink
input can be as high as 5V and then HPD_SOURCE# will output
no higher than 1.0V.
7
8
9
HPD_SOURCE#
SDA_SOURCE
SCL_SOURCE
O
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
Connected to SDA_SINK through voltage limiting integrated
NMOS passgate.
I/O
I/O
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
Connected to SCL_SINK through voltage-limiting integrated
NMOS passgate
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential
output signal with OUT_D4-.
13
14
16
17
19
20
22
23
OUT_D4+
OUT_D4-
OUT_D3+
OUT_D3-
OUT_D2+
OUT_D2-
OUT_D1+
OUT_D1-
O
O
O
O
O
O
O
O
HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential
output signal with OUT_D4+
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential
output signal with OUT_D3-.
HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential
output signal with OUT_D3+
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential
output signal with OUT_D2-.
HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential
output signal with OUT_D2+
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential
output signal with OUT_D1-.
HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential
output signal with OUT_D1+
Enable for IN_Dx to OUT_Dx level shiꢀer path.
OE#
IN_D Termination
> 100KΩ
OUT_D Outputs
High-Z
25
OE#
I
1
0
50Ω
Active
5V DDC Clock I/O. Pulled up by external termination to 5V.
Connected to SCL_SOURCE through voltage limiting integrated
NMOS passgate.
28
SCL_SINK
I/O
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Pin
Name
I/O Type
Descriptions
5V DDC Data I/O. Pulled up by external termination to 5V. Con-
nected to SDA_SOURCE through voltage limiting integrated
NMOS passgate.
29
SDA_SINK
I/O
Low Frequency, 0V to 5V (nominal) input signal. is signal comes
from the TMDS connector. Voltage High indicates “plugged” state;
voltage low indicated “unplugged”. HPD_SINK is pulled down by
an integrated 100K ohm pull-down resistor.
30
32
HPD_SINK
DDC_EN
I
I
Enables bias voltage to the DDC passgate level shiꢀer gates. (May
be implemented as a bias voltage connection to the DDC pass gates
themselves.)
DDC_EN
0V
Passgate
Disable
Enable
3.3V
Low-swing diff input from DP Tx outputs. IN_D1- makes a differ-
ential pair with IN_D1+.
38
39
41
42
44
45
47
48
IN_D1-
IN_D1+
IN_D2-
IN_D2+
IN_D3-
IN_D3+
IN_D4-
IN_D4+
I
I
I
I
I
I
I
I
Low-swing diff input from DP Tx outputs. IN_D1+ makes a dif-
ferential pair with IN_D1-.
Low-swing diff input from DP Tx outputs. IN_D2- makes a differ-
ential pair with IN_D2+.
Low-swing diff input from DP Tx outputs. IN_D2+ makes a dif-
ferential pair with IN_D2-.
Low-swing diff input from DP Tx outputs. IN_D3- makes a differ-
ential pair with IN_D3+.
Low-swing diff input from DP Tx outputs. IN_D3+ makes a dif-
ferential pair with IN_D3-.
Low-swing diff input from DP Tx outputs. IN_D4- makes a differ-
ential pair with IN_D4+.
Low-swing diff input from DP Tx outputs. IN_D4+ makes a dif-
ferential pair with IN_D4-.
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PS9113
08/23/11
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Absolute Maximum Ratings (Over operating free-air temperature range)
Item
Rating
Supply Voltage to Ground Potential
5.5V
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
150°C
Junction Temperature
Soldering Temperature
260°C
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Recommended Operation Conditions
Parameter
Min.
-40
Typ.
Max.
+85
Unit
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
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PS9113
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Electrical Characteristics
Table: Power Supplies and Temperature Range
Symbol
VDD
Parameter
Min
Typ
Max
3.6
100
2
Units
V
Comments
3.3V Power supply
Max Current
3.0
3.3
mA
mA
ICC
Standby Current
OE# = HIGH
ICCQ
Case temperature range
for operation with spec.
-40
85
Celsius (°)
TCASE
Table: Differential Input Characteristics ꢀor IN_Dx signals
Symbol
Parameter
Min
Typ
Max
Units
Comments
Tbit is determined by the display
mode. Nominal bit rate ranges from
250Mbps to 2.5Gbps per lane. Nomi-
nal Tbit at 2.5 Gbps = 400 ps. 360ps =
400ps-10%
Unit Interval
360
ps
Tbit
Input Differential Volt-
age level
0.175
0.8
1.200
V
See note 1 below
VRX_DIFF
TRX_EYE
VCM-ACp-p
ZRX_DC
Minimum Eye Width at
IN_D input pair
e level shiꢀer may add a maximum
of 0.02UI jitter (400 * 0.02) = 8ps
Tbit
mV
Ω
AC Peak Common
Mode Input Voltage
100
60
See note 2 below
Required IN_D+ as well as IN_D- DC
impedance (50 20% tolerance).
40
0
50
Intended to limit power-up stress on
chipset's PCIE output buffers.
2.0
V
ZRX-Bias
Differential inputs must be in a high
impedance state when OE# is HIGH.
100
k Ω
ZRX_HIGH-Z
1. V
= 2x|V
V
| Applies to IN_Dx signals
RX-DIFF
RX-D- - RX-D-
2. V
= |V
- - V -|/2 - V
RX-D RX-CM-DC
CM-AC-p-p
RX-D
V
= DC(avg) oꢀ |V
+ V
-|/2
RX-CM-DC
RX-D+
RX-D
V
includes all ꢀrequencies above 30 kHz.
CM-AC-p-p
TMDS Outputs
e level shiꢀer's TMDS outputs are required to meet HDMI 1.3 specifications.
e HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3
specification.
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PS9113
08/23/11
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Truth Table (Slew Rate control function)
SR1
SR0
Rise/Fall Time (Typ)
1
1
0
0
1
0
1
0
140ps
130ps
120ps
110ps
Test Setup Condition
VDD = 3.3V, Ambient temperture 25°C
Rise/Fall time is from 20% to 80% on Rising/Falling edge
Date rate: 620 Mbps
Input: 1V differential peak-to-peak clock pattern
Equalization : 3dB
Table 1: OE Pin Description
OE#
Device State
Comments
Differential input buffers and output buffers
enabled. Input impedance = 50Ω
Normal functioning state for IN_D to OUT_D
level shiꢀing function.
Asserted (low voltage)
Low-power state.
Intended for lowest power condition when:
à Differential input buffers and termination
are disabled.
à No display is plugged in or
à e level shiꢀed data path is disabled
HPD_SINK input and HPD_SOURCE#
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions
are not affected by OE#
à Differential inputs are in a high
impedance state.
à OUT_D level-shiꢀing outputs are
disabled.
à OUT_D level-shiꢀing outputs are in high
impedance state.
à Internal bias currents are turned off.
Unasserted (high voltage)
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Table 2: Differential Output Characteristics ꢀor TMDS_OUT signals
Symbol
Parameter
Min
Typ
Max
Units Comments
VDD is the DC termination volt-
age in the HDMI or DVI Sink.
VDD is nominally 3.3V
Single-ended high level
output voltage
V
VH
VDD-10mV VDD
VDD+10mV
Single-ended low level
output voltage
e open-drain output pulls
V
VL
VDD-600mV VDD-500mV VDD-400mV
down from VDD
.
Single ended output swing
voltage
Swing down from TMDS termi-
nation voltage (3.3V 10%)
425
500
600
50
mV
VSWING
Measured with TMDS outputs
pulled up to VDD Max _(3.6V)
through 50Ω resistors.
Single-ended current in
high-Z state
µA
IOFF
is differential skew budget is
in addition to the skew present-
ed between D+ and D- paired
input pins. HDMI revision 1.3
source allowable intrapair skew
Intra-pair differential
skew
30
ps
TSKEW-INTRA
is 0.15 Tbit
.
is lane-to-lane skew budget
is in addition to skew between
differential input pairs
Inter-pair lane-to-lane
output skew
100
25
ps
ps
TSKEW-INTER
Jitter budget for TMDS signals
as they pass through the level
shiꢀer. 25ps = 0.056 Tbit at 2.25
Gb/s
Jitter added to TMDS
signals
TJIT
TMDS output oscillation elimination
e inputs do not incorporate a squelch circuit. erefore, we recommend the input to be externally biased to prevent output oscilla-
tion. Pericom recommends to add a 1.5Kohm pull-up to the CLK- input.
VBIAS
R
R
INT
INT
3.3V
R
T
SS
DMDP
Receiver
TMDS
Driver
1.5Kohm
AV
DD
SS
R
T
TMDS Input Fail-Saꢀe Recommendation
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PS9113
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
Table 3: HPD Characteristics
Symbol
Parameter
Min
Typ
Max
Units Comments
Low-speed input changes state on cable plug/
unplug
Input High Level
2.0
5.0
5.3
V
VIH-HPD
HPD_sink Input Low
Level
0
0.8
70
V
VIL-HPD
IIN-HPD
VOH-HPD
VOL-HPD
HPD_sink Input Leakage
Current
Measured with HPD_sink at VIH-HPD max
and VIL-HPD min
µA
V
HPD_SOURCE# Output
High-Level, IOH = -200µA
0.8
0
1.1
0.1
VDD = 3.3V 10%
HPD_SOURCE# Output
Low-Level, IOL = 200µA
V
HPD_sink to HPD_
SOURCE# propagation
delay
Time from HPD_sink changing state to
HPD_SOURCE# changing state. Includes
HPD_source rise/fall time
200
20
ns
ns
THPD
HPD_SOURCE# rise/ fall
time
Time required to transition from VOH- HPDB
to VOL-HPDB or from VOL-HPDB to VOH-HPDB
1
TRF-HPDB
Table 4: OE# Input, DDC_EN
Symbol
Parameter
Min
2.0
0
Typ
Typ
Max
Units Comments
TMDS enable input changes state on cable
plug/unplug
Input High Level
Input Low Level
Input Leakage Current
V
VIH
VIL
IIN
VDD
0.8
10
V
Measured with input at VIH-EN max and
VIL-EN min
µA
Table 5: Termination Resistor
Symbol
Parameter
Min
Max
Units Comments
HPD_sink input pull-
down resistor.
Guarantees HPD_sink is LOW when no
display is plugged in.
100K
Ω
RHPD
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PS9113
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PI3VDP411LSTR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifer)
UNIT: mm
DATE: 02/11/09
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZB48
REVISION: A
DOCUMENT CONTROL #: PD-2080
09-0091
Note:
•ꢀ For latest package inꢀo, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code Package Type
PI3VDP411LSTRZBE
ZB
Pb-free & Green, 48-pin TQFN
1. ermal characteristics can be ꢀound on the company web site at www.pericom.com/packaging/
2. E = Pb-ꢀree and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336
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PS9113
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DisplayPort is a trademark of VESA www.vesa.org
HDMI, High-Definition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries.
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