PI3VDP411LSZBE [PERICOM]
Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter; 数字视频电平转换器的交流耦合的数字视频输入到一个DVI / HDMI发送器
| 型号： | PI3VDP411LSZBE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter |
| 文件： | 总13页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Features
• Converts low-swing AC coupled differential input to HDMI
rev 1.3 compliant open-drain current steering Rx terminated dif-
ferential output
• HDMI level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
• Integrated 50-ohm termination resistors for AC-coupled dif-
ferential inputs.
• Enable/Disable feature to turn off TMDS outputs to enter low-
power state.
Description
Pericom Semiconductor’s PI3VDP411LS provides the ability to
use a Dual-mode DP transmitter in HDMI mode. This flexibility
provides the user a choice of how to connect to their favorite
display. All signal paths accept AC coupled video signals. The
PI3VDP411LS converts this AC coupled signal into an HDMI
rev 1.3 compliant signal with proper signal swing. This conver-
sion is automatic and transparent to the user.
• Output slew rate control on TMDS outputs to minimize EMI.
• Transparent operation: no re-timing or configuration required.
• 3.3 Power supply required.
The PI3VDP411LS supports up to 2.5Gbps, which provides 12-
bits of color depth per channel, as indicated in HDMI rev 1.3.
• Integrated ESD protection to 8kV contact on all high speed
I/O pins (IN_x and OUT_x) per IEC61000-4-2 test spec, level 4
• DDC level shifters from 5V from sink side down to 3.3V on
source side
• Level shifter for HPD signal from HDMI/DVI connector
• Integrated pull-down on HPD_sink input guarantees "input
low" when no display is plugged in
• Packaging (Pb-Free & Green available)
– 48 TQFN, 7mm × 7mm (ZDE)
– 48 TQFN, 7mm x 7mm (ZBE)
– 42 TQFN, 9mm × 3.5mm (ZHE)
Pin Configuration
42-Pin TQFN (ZHE)
48-Pin TQFN (ZDE/ZBE)
DDC_EN
1
2
3
4
5
6
7
8
VDD
OE#
GND
OUT_D1-
OUT_D1+
VDD
OUT_D2-
OUT_D2+
38
37
36
35
34
39
42 41 40
25
24
36
35
33
29 28
27
26
34
32
31
30
EQ_0
GND
IN_D1-
IN_D1+
VDD
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VDD
IN_D4-
IN_D4+
GND
VDD
OC_0
GND
IN_D1-
IN_D1+
VDD
37
GND
23
22
38
39
OUT_D1-
OUT_D1+
VDD
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
40
41
42
43
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
GND
9
GND
OUT_D3-
OUT_D3+
VDD
OUT_D4-
OUT_D4+
GND
10
11
12
13
14
15
16
17
GND
GND
GND
17
16
15
14
13
IN_D3-
IN_D3+
44
45
46
47
48
OUT_D3-
OUT_D3+
VDD
VDD
IN_D4-
IN_D4+
VDD
SCL_Source
20
18 19
21
OUT_D4-
OUT_D4+
12
1
2
8
9
10
11
3
4
5
6
7
PS8913D
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PI3VDP411LS
Display Port Redriver w/ Level Conversion feature for
DVI/HDMI interoperability
Block Diagram
OE#
OUTx_D4+
OUTx_D4-
0V
INx_D4+
Rx
INx_D4-
OUTx_D3+
OUTx_D3-
0V
INx_D3+
INx_D3-
Rx
OUTx_D2+
OUTx_D2-
0V
INx_D2+
INx_D2-
Rx
OUTx_D1+
OUTx_D1-
0V
INx_D1+
INx_D1-
Rx
HPD_SOURCE
HPD_SINK
HPD
DDC_EN (0V TO 3.3V)
SCL_SINK
SDA_SINK
SCL_SOURCE
SDA_SOURCE
(times 2)
x = 1 or 2
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Note: Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Ratings (Above which useful life may be im-
paired. For user guidelines, not tested.)
Storage Temperature.....................................–65°C to +150°C
Supply Voltage to Ground Potential.............–0.5V to +5V
DC Input Voltage..........................................–0.5V to V
DC Output Current .......................................120mA
Power Dissipation .........................................1.0W
DD
Table 2: Signal Descriptions
Pin Name
Type
Description
OE#
5.5V tolerant low-voltage
single-ended input
Enable for level shifter path
OE#
IN_D Termination OUT_D Outputs
1
0
>100KΩ
50Ω
High-Z
Active
IN_D4+
IN_D4–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D4– makes a differential pair with IN_D4+.
IN_D3+
IN_D3–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D3– makes a differential pair with IN_D3+.
IN_D2+
IN_D2–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D2– makes a differential pair with IN_D2+.
IN_D1+
IN_D1–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D1– makes a differential pair with IN_D1+.
OUT_D4+
OUT_D4–
OUT_D3+
OUT_D3–
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D4+
makes a differential output signal with OUT_D4–.
HDMI 1.3 compliant TMDS output. OUT_D4–
makes a differential output signal with OUT_D4+.
HDMI 1.3 compliant TMDS output. OUT_D3+
makes a differential output signal with OUT_D3–.
HDMI 1.3 compliant TMDS output. OUT_D3–
makes a differential output signal with OUT_D3+.
(Continued)
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Pin Name
Type
Description
OUT_D2+
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
OUT_D2–
OUT_D1+
OUT_D1–
TMDS Differential output
TMDS Differential output
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
HPD_SINK
5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm put-down resistor.
HPD_SOURCE
SCL_SOURCE
3.3V single-ended output
HPD_SOURCE: 0V to 3.3V (nominal) output signal.
This is level-shifted version of the HPD_SINK signal.
Single-ended 3.3V open-drain
DDC I/O
3.3V DDC Data I/O. Pulled up by external termina-
tion to 3.3V. Connected to SCL_SINK through volt-
age-limiting integrated NMOS passgate.
SDA_SOURCE
SCL_SINK
SDA_SINK
DDC_EN
Single-ended 3.3V open-drain
DDC I/O
3.3V DDC Data I/O. Pulled up by external termination
to 3.3V. Connected to SDA_SINK through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
DDC I/O
5V DDC Clock I/O. Pulled up by external termination
to 5V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
DDC I/O
5V DDC Data I/O. Pulled up by external termination
to 5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate.
5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter
gates. (May be implemented as a bias voltage connec-
tion to the DDC pass gates themselves.)
DDC_EN
0V
Passgate
Disabled
Enabled
3.3V
VDD
3.3V DC Supply
3.3V ± 10%
OC_2
(REXT)
3.3V single-ended control input Acceptable connections to OC_1 (REXT) pin are: Re-
sistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Pin Name
Type
Description
OC_3
Analog connection to external
component or supply
Acceptable connections to OC_3 pin are: short to
3.3V or to GND; NC.
OC_0
OC_1
EQ_0
EQ_1
Output and Input jitter elimina- Control pins are to enable Jitter elimination features.
tion control
For normal operation these pins are tied GND or to
VDD. Please see the truth tables for more information.
Truth Table 1
OC_3(2)
OC_2(1)
OC_1(1)
OC_0(1)
Vswing
Pre/De-
(mV)
emphasis
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
500
0
600
0
750
0
1000
500
0
0
500
1.5dB
3.5dB
6dB
0
500
500
400
400
3.5dB
6dB
9dB
0
400
400
1000
1000
1000
1000
-3.5dB
-6dB
-9dB
Truth Table 2
EQ_1(2)
EQ_0(1)
Equalization
@ 1.25GHz
(dB)
0
0
1
0
1
0
1
3
6
9
1
12
Notes:
1) These signals have internal 100kΩ pull-ups.
2) For 42-TQFN package, these signals are internally connected to GND directly.
For 48-TQFN package, these signals have internal 100kΩ pull-ups, with external connection.
PS8913D
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Electrical Characteristics
Table 3: Power Supplies and Temperature Range
Symbol
Parameter
Min
Nom
Max
Units
Comments
VDD
3.3V Power
Supply
3.0
3.3
3.6
V
ICC
Max Current
Total current from
VDD 3.3V supply
when de-emphasis/
pre-emphasis is set to
0dB.
100
mA
ICCQ
Standby Cur-
rent Consump-
tion
OE# = HIGH
2
mA
TCASE
Case tempera-
ture range for
operation with
spec.
-40
85
Celcius
Table 4: OE# Description
OE#
Device State
Comments
Asserted (low voltage)
Differential input buffers and output
buffers enabled. Input impedance =
50ꢀ
Normal functioning state for IN_D
to OUT_D level shifting function.
Unasserted (high voltage)
Low-power state.
Intended for lowest power condi-
tion when:
•
•
No display is plugged in or
The level shifted data path is
disabled
Differential input buffers and termina-
tion are disabled. Differential inputs
are in a high-impedance state.
HPD_SINK input and HPD_SOURCE
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions are
not affected by OE#
OUT_D level-shifting outputs are
disabled.
OUT_D level-shifting outputs are in
high-impedence state.
Internal bias currents are turned off.
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Table 5: Differential Input Characteristics for IN_D and RX_IN signals
Symbol
Parameter
Min Nom Max Units Comments
Tbit is determined by the display mode. Nom-
inal bit rate ranges from 250Mbps to 2.5Gbps
per lane. Nominal Tbit at 2.5 Gbps=400ps.
360ps=400ps-10%
Tbit
Unit Interval
360
ps
VRX-DIFFp-p Differential Input Peak 0.175
to Peak Voltage
1.200 V
VRX-DIFFp-p=2'|VRX-D+ x VRX-D-|
Applies to IN_D and RX_IN signals
TRX-EYE
Minimum Eye Width at 0.8
IN_D input pair
Tbit The level shifter may add a maximum of
0.02UI jitter
VCM-AC-pp AC Peak
Common Mode Input
Voltage
100 mV
VCM-AC-pp = |VRX-D+ + VRX-D-|/2
- VRX-CM-DC.
VRX-CM-DC = DC(avg) of|VRX-D+ +
VRX-D-|/2
VCM-AC-pp includes all frequencies
above 30 kHz.
ZRX-DC
40
0
50
60
Ω
Required IN_D+ as well as IN_D- DC
impedance (50Ω ± 20% tolerance).
Intended to limit power-up stress on
chipset's PCIE output buffers.
VRX-Bias
ZRX-HIGH-Z
2.0
V
100
Differential inputs must be in a high im-
pedance state when OE# is HIGH.
kΩ
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.
The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts
with the HDMI 1.3 specification.
Table 6: Differential Output Characteristics for TMDS_OUT signals
Symbol
Parameter
Min
Nom
Max
Units Comments
VDD is the DC termination
voltage in the HDMI or DVI
Sink. VDD is nominally 3.3V
V
V
V
I
Single-ended
high level output
voltage
VDD-10mV
VDD
VDD+10mV
V
H
The open-drain output pulls
down from VDD.
Single-ended
low level output
voltage
VDD-600mV
450mV
VDD-500mV VDD-400mV
V
L
Swing down from TMDS
termination voltage (3.3V ±
10%)
Single-ended
output swing
voltage
500mV
600mV
50
V
SWING
Measured with TMDS out-
puts pulled up to VDD Max
_(3.6V) through 50Ω resistors.
Single-ended
current in high-Z
state
μA
OFF
Max Rise/Fall time @2.7Gbps
= 148ps. 125ps = 148-15%
T
T
Rise time
125ps
125ps
0.4Tbit
0.4Tbit
ps
ps
R
F
Max Rise/Fall time @2.7Gbps
= 148ps. 125ps = 148-15%
Fall time
This differential skew bud-
get is in addition to the skew
presented between D+ and
D- paired input pins. HDMI
revision 1.3 source allowable
intra-pair skew is 0.15Tbit.
T
Intra-pair
differential skew
30
ps
SKEW-INTRA
This lane-to-lane skew budget
is in addition to skew between
differential input pairs
T
T
Inter-pair lane-
to-lane output
skew
100
25
ps
ps
SKEW-INTER
JIT
Jitter added to
TMDS signals
Jitter budget for TMDS
signals as they pass through
the level shifter. 25ps =
0.056 Tbit at 2.25 Gb/s
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
TMDS output oscillation elimination
The inputs do not incorporate a squelch circuit. Therefore, we reccomend the input to be externally biased to
prevent output oscillation. Pericom reccomends to add a 1.5Kohm pull-up to the CLK- input.
VBIAS
R
R
INT
INT
3.3V
R
T
SS
DMDP
Receiver
TMDS
Driver
1.5Kohm
AV
DD
SS
R
T
TMDS Input Fail-Safe Recommendation
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Table 8: HPD Input Characteristics
Symbol
Parameter
Min Nom Max
Units
Comments
V
V
Input High Level
2.0
5.0
5.3
0.8
70
V
Low-speed input changes state on
cable plug/unplug
IH-HPD
HPD_sink Input
Low Level
0
V
μA
V
IL-HPD
IN-HPD
I
HPD_sink Input
Leakage Current
Measured with HPD_sink at V
IH-HPD
max and V
min
IL-HPD
V
V
HPD_sink Output
High-Level
2.5
0
V
DD
V
= 3.3V ± 10%
DD
OH-HPDB
OL-HPDB
HPD
HPD_sink Output
Low-Level
0.02
200
V
T
HPD_sink to
HPD_source
propagation delay
ns
Time from HPD_sink changing state
to HPD_source changing state. In-
cludes HPD_source rise/fall time
T
HPD_source rise/
fall time
1
20
ns
Time required to transition from V
OH-
RF-HPDB
to V
or from V
OL-HPDB
HPDB
OL-HPDB
to V
OH-HPDB
Table 9: OE# Input and DDC_EN
Symbol
Parameter
Min Nom Max
Units
Comments
V
V
Input High Level
2.0
0
VDD
V
TMDS enable input changes state
on cable plug/unplug
IH
Input Low Level
0.8
10
V
IL
I
Input Leakage Current
μA
Measured with input at V
IH-EN
IN
max and V
min
IL-EN
Table 10: Termination Resistors
Symbol
Parameter
Min Nom Max
Units
Comments
R
HPD_sink input pull- 80K 100k 120K
down resistor.
Ω
Guarantees HPD_sink is LOW when
no display is plugged in.
HPD
PS8913D
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Packaging Mechanical: 48-Pin, TQFN (ZD)
DATE: 09/11/08
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD48)
REVISION: C
DOCUMENT CONTROL #: PD-2045
PS8913D
11/05/08
08-0294
11
PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Packaging Mechanical: 48-Pin, TQFN (ZB)
DATE: 08/13/08
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
ZB48
PACKAGE CODE:
REVISION: --
DOCUMENT CONTROL #: PD-2080
PS8913D
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Packaging Mechanical: 42 pin, TQFN (ZH)
DATE: 03/03/08
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH (ZH42)
REVISION: B
DOCUMENT CONTROL #: PD-2035
08-0098
Ordering Information
Ordering Code
Package Code
ZBE
Package Description
PI3VDP411LSZBE
PI3VDP411LSZDE
PI3VDP411LSZHE
48-pin Pb-free & Green, TQFN
48-pin Pb-free & Green, TQFN
42--pin Pb-free & Green, TQFN
ZDE
ZHE
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8913D
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