PI3VDP411LSTZHE [PERICOM]
Consumer Circuit, 9 X 3.50 MM, GREEN, MO-220, TQFN-42;
| 型号： | PI3VDP411LSTZHE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Consumer Circuit, 9 X 3.50 MM, GREEN, MO-220, TQFN-42 商用集成电路 |
| 文件： | 总13页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI3VDP411LST
Digital Video Level Shifter for dual mode DP signals
w/ inverting buffer for HPD signal
Description
Features
Pericom Semiconductor’s PI3VDP411LST provides the ability
to use a Dual-mode Display Port transmitter in HDMI mode.
This flexibility provides the user a choice of how to connect to
their favorite display. All signal paths accept AC coupled video
signals. The PI3VDP411LST converts this AC coupled signal
into an HDMI rev 1.3 compliant signal with proper signal swing.
This conversion is automatic and transparent to the user.
•
Converts low-swing AC coupled differential input to HDMI
rev 1.3 compliant open-drain current steering Rx terminated
differential output
HDMI level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
Integrated 50-ohm termination resistors for AC-coupled dif-
ferential inputs.
Enable/Disable feature to turn off TMDS outputs to enter
low-power state.
Output slew rate control on TMDS outputs to minimize EMI.
Transparent operation: no re-timing or configuration required.
3.3 Power supply required.
Integrated ESD protection up to 8kV contact on all high
speed I/O pins (IN_x and OUT_x) per IEC61000-4-2 specifi-
cation, level 4
•
•
•
The PI3VDP411LST supports up to 2.5Gbps, which provides
12-bits of color depth per channel, as indicated in HDMI rev 1.3.
•
•
•
•
•
•
DDC level shifters from 5V down to 3.3V
Inverting level shifter for HPD signal from HDMI/DVI
connector
•
•
Integrated pull-down on HPD_sink input guarantees "input
low" when no display is plugged in
Packaging (Pb-Free & Green available)
– 48 TQFN, 7mm × 7mm (ZD)
– 42 TQFN, 9mm × 3.5mm (ZH)
– 48 TQFN, 7mm × 7mm (ZB)
Pin Configuration
42-Pin TQFN (ZH)
48-Pin TQFN (ZD/ZB)
25
24
36
35
33
29 28
27
26
34
32
31
30
39
42 41 40
DDC_EN
EQ_0
1
2
3
4
5
6
7
8
VDD
OE#
GND
OUT_D1-
OUT_D1+
VDD
OUT_D2-
OUT_D2+
GND
IN_D1-
IN_D1+
VDD
37
GND
38
37
36
35
34
23
22
38
39
OUT_D1-
OUT_D1+
VDD
GND
IN_D1-
IN_D1+
VDD
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VDD
IN_D4-
IN_D4+
GND
21
20
19
18
40
41
42
43
33
32
31
30
29
28
27
26
25
24
23
22
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
GND
9
GND
GND
GND
GND
OUT_D3-
OUT_D3+
VDD
OUT_D4-
OUT_D4+
GND
10
11
12
13
14
15
16
17
17
16
15
14
13
44
45
46
47
48
IN_D3-
IN_D3+
VDD
OUT_D3-
OUT_D3+
VDD
IN_D4-
IN_D4+
OUT_D4-
OUT_D4+
VDD
SCL_Source
VDD
OC_S0
20
12
18
19
21
1
2
8
9
10
11
3
4
5
6
7
PS8906F
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08-0294
1
PI3VDP411LST
Digital Video Level Shifter for dual mode DP signals
w/ inverting buffer for HPD signal
Block Diagram
OE#
OUT_D4+
OUT_D4-
0V
IN_D4+
IN_D4-
Rx
OUT_D3+
OUT_D3-
0V
IN_D3+
IN_D3-
Rx
OUT_D2+
OUT_D2-
0V
IN_D2+
IN_D2-
Rx
OUT_D1+
OUT_D1-
0V
IN_D1+
IN_D1-
Rx
HPD_SOURCE#
HPD_SINK
HPD
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Note: Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Ratings (Above which useful life may be im-
paired. For user guidelines, not tested.)
Storage Temperature .....................................–65°C to +150°C
Supply Voltage to Ground Potential .............–0.5V to +5V
DC Input Voltage ..........................................–0.5V to V
DC Output Current .......................................120mA
Power Dissipation .........................................1.0W
DD
Table 2: Signal Descriptions
Pin Name
Type
Description
OE#
5.5V tolerant low-voltage
single-ended input
Enable for level shifter path
OE#
IN_D Termination OUT_D Outputs
1
0
>100KΩ
50Ω
High-Z
Active
IN_D4+
IN_D4–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D4– makes a differential pair with IN_D4+.
IN_D3+
IN_D3–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D3– makes a differential pair with IN_D3+.
IN_D2+
IN_D2–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D2– makes a differential pair with IN_D2+.
IN_D1+
IN_D1–
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1–.
Differential input
Low-swing diff input from GMCH PCIE outputs.
IN_D1– makes a differential pair with IN_D1+.
OUT_D4+
OUT_D4–
OUT_D3+
OUT_D3–
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D4+
makes a differential output signal with OUT_D4–.
HDMI 1.3 compliant TMDS output. OUT_D4–
makes a differential output signal with OUT_D4+.
HDMI 1.3 compliant TMDS output. OUT_D3+
makes a differential output signal with OUT_D3–.
HDMI 1.3 compliant TMDS output. OUT_D3–
makes a differential output signal with OUT_D3+.
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Pin Name
Type
Description
OUT_D2+
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
OUT_D2–
OUT_D1+
OUT_D1–
TMDS Differential output
TMDS Differential output
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
HPD_SINK
5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm pull-down resistor.
HPD_SOURCE# 1V buffer
Inverted buffer from 0V to 5V input signal. If input is
LOGIC HIGH, then output will be LOGIC LOW, with
V
OL
max of 0.1V max. If input is LOGIC LOW, then
output will be LOGIC HIGH, with V of 0.8V min.
OH
SCL_SOURCE
SDA_SOURCE
SCL_SINK
Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external termina-
DDC I/O
tion to 3.3V. Connected to SCL_SINK through volt-
age-limiting integrated NMOS passgate.
Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external termination
DDC I/O
to 3.3V. Connected to SDA_SINK through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
DDC I/O
5V DDC Clock I/O. Pulled up by external termination
to 5V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate.
SDA_SINK
DDC_EN
Single-ended 5V open-drain
DDC I/O
5V DDC Data I/O. Pulled up by external termination
to 5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate.
5.0V tolerant Single-ended
input
Enables bias voltage to the DDC passgate level shifter
gates. (May be implemented as a bias voltage connec-
tion to the DDC pass gates themselves.)
DDC_EN
0V
Passgate
Disabled
Enabled
3.3V
VDD
3.3V DC Supply
3.3V ± 10%
OC_2
(REXT)
3.3V single-ended control input Acceptable connections to OC_1 (REXT) pin are: Re-
sistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
(1)
Note:
1) internal 100Kohm pull-up
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Pin Name
Type
Description
OC_3
Analog connection to external
component or supply
Acceptable connections to OC_3 pin are: short to
3.3V or to GND; NC.
OC_0
OC_1
EQ_0
EQ_1
Output and Input jitter elimina- Control pins are to enable Jitter elimination features.
tion control
For normal operation these pins are tied GND or to
VDD. Please see the truth tables for more information.
Truth Table 1
OC_3(2)
OC_2(1)
OC_1(1)
OC_0(1)
Vswing
Pre/De-
(mV)
emphasis
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
500
0
600
0
750
0
1000
500
0
0
500
1.5dB
3.5dB
6dB
0
500
500
400
400
3.5dB
6dB
9dB
0
400
400
1000
1000
1000
1000
-3.5dB
-6dB
-9dB
Truth Table 2
(2)
(1)
EQ_1
EQ_0
Equalization
@ 1.25GHz
(dB)
0
0
1
1
0
1
0
1
3
6
9
12
Notes:
1. Internal 100Kohm pull-up
2. For 42-TQFN (ZHE) package, there is an internal connection to GND.
For 48-TQFN (ZDE) package, external connection is allowed and there is an internal 100KΩ pull-up.
PS8906F
11/06/08
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Electrical Characteristics
Table 3: Power Supplies and Temperature Range
Symbol
Parameter
Min
Nom
Max
Units
Comments
VDD
3.3V Power
Supply
3.0
3.3
3.6
V
ICC
Max Current
Total current from
VDD 3.3V supply
when de-emphasis/
pre-emphasis is set to
0dB.
100
mA
ICCQ
Standby Cur-
rent Consump-
tion
OE# = HIGH
2
mA
TCASE
Case tempera-
ture range for
operation with
spec.
-40
85
Celcius
Table 4: OE# Description
OE#
Device State
Comments
Asserted (low voltage)
Differential input buffers and output Normal functioning state for IN_D
buffers enabled. Input impedance =
to OUT_D level shifting function.
50ꢀ
Unasserted (high voltage)
Low-power state.
Intended for lowest power condi-
tion when:
•
•
No display is plugged in or
The level shifted data path is
disabled
Differential input buffers and ter-
mination are disabled. Differential
inputs are in a high-impedance state.
HPD_SINK input and HPD_SOURCE#
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions are
not affected by OE#
OUT_D level-shifting outputs are
disabled.
OUT_D level-shifting outputs are in
high-impedence state.
Internal bias currents are turned off.
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 5: Differential Input Characteristics for IN_D and RX_IN signals
Symbol
Parameter
Min Nom Max Units Comments
Tbit is determined by the display mode. Nom-
inal bit rate ranges from 250Mbps to 2.5Gbps
per lane. Nominal Tbit at 2.5Gbps=400ps.
360ps=400ps-10%
Tbit
Unit Interval
360
ps
VRX-DIFFp-p Differential Input Peak 0.175
to Peak Voltage
1.200 V
VRX-DIFFp-p=2'|VRX-D+ x VRX-D-|
Applies to IN_D and RX_IN signals
TRX-EYE
Minimum Eye Width at 0.8
IN_D input pair
Tbit The level shifter may add a maximum of
0.02UI jitter
VCM-AC-pp AC Peak
Common Mode Input
Voltage
100 mV
VCM-AC-pp = |VRX-D+ + VRX-D-|/2
- VRX-CM-DC.
VRX-CM-DC = DC(avg) of|VRX-D+ +
VRX-D-|/2
VCM-AC-pp includes all frequencies
above 30 kHz.
ZRX-DC
40
0
50
60
Ω
Required IN_D+ as well as IN_D- DC
impedance (50Ω ± 20% tolerance).
Intended to limit power-up stress on
chipset's PCIE output buffers.
VRX-Bias
ZRX-HIGH-Z
2.0
V
100
Differential inputs must be in a high im-
pedance state when OE# is HIGH.
kΩ
PS8906F
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.
The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts
with the HDMI 1.3 specification.
Table 6: Differential Output Characteristics for TMDS_OUT signals
Symbol
Parameter
Min
Nom
Max
Units Comments
AVDD is the DC termina-
V
Single-ended
high level output
voltage
AVDD-10mV AVDD
AVDD+10mV
V
H
tion voltage in the HDMI
or DVI Sink. AVDD is
nominally 3.3V
The open-drain output
pulls down from AVDD.
V
V
I
Single-ended
low level output
voltage
AVDD-600mV AVDD-500mV AVDD-400mV
V
L
Swing down from TMDS
termination voltage (3.3V
± 10%)
Single-ended
output swing
voltage
450mV
500mV
600mV
50
V
SWING
Measured with TMDS
outputs pulled up to
AVDD Max (3.6V)
through 50Ω resistors.
Single-ended
current in high-Z
state
μA
OFF
Max Rise/Fall time
@2.7Gbps = 148ps.
125ps = 148-15%
T
T
T
Rise time
125ps
125ps
0.4Tbit
0.4Tbit
30
ps
ps
ps
R
Max Rise/Fall time
@2.7Gbps = 148ps.
125ps = 148-15%
Fall time
F
This differential skew
budget is in addition to
the skew presented be-
tween D+ and D- paired
input pins. HDMI revision
1.3 source allowable in-
tra-pair skew is 0.15Tbit.
Intra-pair
differential skew
SKEW-INTRA
This lane-to-lane skew
budget is in addition to
skew between differential
input pairs
T
T
Inter-pair lane-
to-lane output
skew
100
25
ps
ps
SKEW-INTER
Jitter added to
TMDS signals
Jitter budget for TMDS
signals as they pass
through the level
JIT
shifter. 25ps = 0.056
Tbit at 2.25 Gb/s
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
TMDS output oscillation elimination
The inputs do not incorporate a squelch circuit. Therefore, we reccomend the input to be externally biased to
prevent output oscillation. Pericom reccomends to add a 1.5Kohm pull-up to the CLK- input for each oif the
video input ports.
VBIAS
3.3V
R
INT
R
INT
R
T
SS
DMDP
Receiver
TMDS
Driver
1.5Kohm
AV
DD
SS
R
T
TMDS Input Fail-Safe Recommendation
PS8906F
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 8: HPD Characteristics
Symbol
Parameter
Min Nom Max
Units
Comments
V
V
Input High Level
2.0
5.0
5.3
0.8
70
V
Low-speed input changes state on
cable plug/unplug
IH-HPD
HPD_sink Input
Low Level
0
V
μA
V
IL-HPD
IN-HPD
I
HPD_sink Input
Leakage Current
Measured with HPD_sink at V
IH-HPD
max and V
min
IL-HPD
V
HPD_Source#
Output High-Lev-
0.8
0
1.1
V
DD
= 3.3V ± 10%
OH-HPDB
OL-HPDB
HPD
el, I = -200μA
OH
V
HPD_Source#
Output Low-Lev-
0.1
200
20
V
ns
ns
el, I = 200μA
OL
T
T
HPD_Source#
to HPD_source
propagation delay
Time from HPD_sink changing state
to HPD_source# changing state. In-
cludes HPD_source rise/fall time
HPD_Source#
rise/fall time
1
Time required to transition from V
OH-
RF-HPDB
to V
or from V
OL-HPD
to
HPD
OL-HPD
V
OH-HPD
Table 9: OE# Input and DDC_EN
Symbol
Parameter
Min Nom Max
Units
Comments
V
V
Input High Level
2.0
0
VDD
V
TMDS enable input changes state
on cable plug/unplug
IH
Input Low Level
0.8
10
V
IL
I
Input Leakage Current
μA
Measured with input at V
IH-EN
IN
max and V
min
IL-EN
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
V = 0.1V to 0.9V to isolated
DDC ports
I
DD
DD
|I
|
Input leakage current
0.1
2
ꢁA
lkg
C
Input/output capacitance
Switch resistance
V = 0V
7.5
25
pF
ohm
V
IO
I
R
ON
I = 3mA, V = 0.4V
O
50
O
(2)
(3)
V
Switch output voltage
V = 3.3V, I = 100ꢁA
I
1.5
2.0
2.5
PASS
I
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 10: Termination Resistors
Symbol
Parameter
Min Nom Max
Units
Comments
R
HPD_sink input pull- 80K 100k 120K
down resistor.
Ω
Guarantees HPD_sink is LOW when
no display is plugged in.
HPD
Packaging Mechanical: 48-Pin, TQFN (ZD)
DATE: 11/16/07
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD48)
REVISION: B
DOCUMENT CONTROL #: PD-2045
PS8906F
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Packaging Mechanical: 42-Pin, TQFN (ZH)
DATE: 03/03/08
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH (ZH42)
REVISION: B
DOCUMENT CONTROL #: PD-2035
08-0098
PS8906F
11/06/08
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PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Packaging Mechanical: 48-Pin, TQFN (ZB)
DATE: 08/13/08
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
ZB48
PACKAGE CODE:
REVISION: --
DOCUMENT CONTROL #: PD-2080
Ordering Information
Ordering Code
Package Code
Package Description
PI3VDP411LSTZDE
PI3VDP411LSTZHE
PI3VDP411LSTZBE
ZD
ZH
ZB
48-pin Pb-free & Green, TQFN
42-pin Pb-free & Green, TQFN
48-pin Pb-free & Green, TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8906F
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