PI3VDP411LSTZBE [PERICOM]
Consumer Circuit, 7 X 7 MM, GREEN, MO-220VKKD, TQFN-48;
| 型号： | PI3VDP411LSTZBE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Consumer Circuit, 7 X 7 MM, GREEN, MO-220VKKD, TQFN-48 商用集成电路 |
| 文件： | 总13页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP signals
w/ inverting buffer ꢀor HPD signal
Description
Features
Î Converts low-swing AC coupled differential input to HDMI
rev 1.3 compliant open-drain current steering Rx terminated
differential output
Pericom Semiconductor’s PI3VDP411LST provides the ability
to use a Dual-mode Display Port transmitter in HDMI mode.
is flexibility provides the user a choice oꢀ how to connect to
their ꢀavorite display. All signal paths accept AC coupled video
signals. e PI3VDP411LST converts this AC coupled signal into
an HDMI rev 1.3 compliant signal with proper signal swing.
is conversion is automatic and transparent to the user.
Î HDMI level shifing operation up to 2.5Gbps per lane
(250MHz pixel clock)
Î Integrated 50-ohm termination resistors ꢀor AC-coupled
differential inputs.
Î Enable/Disable ꢀeature to turn off TMDS outputs to enter low-
e PI3VDP411LST supports up to 2.5Gbps, which provides 12-
bits oꢀ color depth per channel, as indicated in HDMI rev 1.3.
power state.
Î Output slew rate control on TMDS outputs to minimize EMI.
Î Transparent operation: no re-timing or configuration
Block Diagram
required.
Î 3.3 Power supply required.
OE#
Î Integrated ESD protection up to 8kV contact on all high speed
I/O pins (IN_x and OUT_x) per IEC61000-4-2 specification,
level 4
OUT_D4+
Î DDC level shifers ꢀrom 5V down to 3.3V
Î Inverting level shifer ꢀor HPD signal ꢀrom HDMI/DVI
Î connector
OUT_D4-
0V
IN_D4+
IN_D4-
Rx
Î Integrated pull-down on HPD_sink input guarantees "input
low" when no display is plugged in
Î Packaging (Pb-Free & Green)
OUT_D3+
OUT_D3-
0V
à
à
48 TQFN, 7mm × 7mm (ZD)
48 TQFN, 7mm × 7mm (ZB)
IN_D3+
IN_D3-
Rx
Pin Configuration 48-Pin TQFN (ZD/ZB)
OUT_D2+
OUT_D2-
0V
IN_D2+
IN_D2-
Rx
25
24
36
35
33
29 28 27
26
34
32
31
30
GND
IN_D1-
IN_D1+
VDD
GND
37
23
22
38
39
OUT_D1-
OUT_D1+
VDD
OUT_D1+
OUT_D1-
0V
21
20
19
18
40
41
42
43
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
IN_D1+
IN_D1-
Rx
GND
GND
GND
HPD_SOURCE#
HPD_SINK
17
16
15
14
13
HPD
44
45
46
47
48
IN_D3-
IN_D3+
VDD
OUT_D3-
OUT_D3+
VDD
IN_D4-
IN_D4+
OUT_D4-
OUT_D4+
SCL_SOURCE
SCL_SINK
12
1
2
8
9
10
11
3
4
5
6
7
SDA_SOURCE
SDA_SINK
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Note: Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Ratings (Above which useful life may be im-
paired. For user guidelines, not tested.)
Storage Temperature .....................................–65°C to +150°C
Supply Voltage to Ground Potential .............–0.5V to +5V
DC Input Voltage ..........................................–0.5V to V
DC Output Current .......................................120mA
Power Dissipation .........................................1.0W
DD
Table 2: Signal Descriptions
Pin Name
Type
Description
Enable ꢀor level shifer path
OE#
IN_D Termination OUT_D Outputs
5.5V tolerant low-voltage single-
ended input
OE#
1
0
>100KΩ
50Ω
High-Z
Active
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D4+
makes a differential pair with IN_D4–.
IN_D4+
IN_D4–
IN_D3+
IN_D3–
IN_D2+
IN_D2–
IN_D1+
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D4–
makes a differential pair with IN_D4+.
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D3+
makes a differential pair with IN_D3–.
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D3–
makes a differential pair with IN_D3+.
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D2+
makes a differential pair with IN_D2–.
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D2–
makes a differential pair with IN_D2+.
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D1+
makes a differential pair with IN_D1–.
Differential input
Low-swing diff input ꢀrom GMCH PCIE outputs. IN_D1–
makes a differential pair with IN_D1+.
IN_D1–
Differential input
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a diꢀ-
ꢀerential output signal with OUT_D4–.
OUT_D4+
OUT_D4–
OUT_D3+
OUT_D3–
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D4– makes a diꢀ-
ꢀerential output signal with OUT_D4+.
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a diꢀ-
ꢀerential output signal with OUT_D3–.
HDMI 1.3 compliant TMDS output. OUT_D3– makes a diꢀ-
ꢀerential output signal with OUT_D3+.
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Pin Name
Type
Description
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differen-
tial output signal with OUT_D2–.
OUT_D2+
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D2– makes a differen-
tial output signal with OUT_D2+.
OUT_D2–
OUT_D1+
TMDS Differential output
TMDS Differential output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differen-
tial output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes a differen-
tial output signal with OUT_D1+.
OUT_D1–
TMDS Differential output
Low Frequency, 0V to 5V (nominal) input signal. is sig-
nal comes ꢀrom the HDMI connector. Voltage High indicates
"plugged" state; voltage low indicated
HPD_SINK
5V tolerance single-ended input
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm pull-down resistor.
Inverted buffer ꢀrom 0V to 5V input signal. Iꢀ input is LOGIC
HIGH, then output will be LOGIC LOW, with V max oꢀ 0.1V
OL
HPD_SOURCE#
1V buffer
max. Iꢀ input is LOGIC LOW, then output will be LOGIC HIGH,
with V oꢀ 0.8V min.
OH
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
Connected to SCL_SINK through voltage-limiting integrated
NMOS passgate.
Single-ended 3.3V open-drain DDC
I/O
SCL_SOURCE
SDA_SOURCE
SCL_SINK
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
Connected to SDA_SINK through voltage-limiting integrated
NMOS passgate.
Single-ended 3.3V open-drain DDC
I/O
5V DDC Clock I/O. Pulled up by external termination to 5V.
Connected to SCL_SOURCE through voltage-limiting integrated
NMOS passgate.
Single-ended 5V open-drain DDC
I/O
5V DDC Data I/O. Pulled up by external termination to 5V. Con-
nected to SDA_SOURCE through voltage-limiting integrated
NMOS passgate.
Single-ended 5V open-drain DDC
I/O
SDA_SINK
Enables bias voltage to the DDC passgate level shifer gates. (May
be implemented as a bias voltage connection to the DDC pass
gates themselves.)
DDC_EN
5.0V tolerant Single-ended input
DDC_EN
0V
Passgate
Disabled
Enabled
3.3V
V
3.3V DC Supply
3.3V 10%
DD
OC_2
(1)
Acceptable connections to OC_1 (REXT) pin are: Resistor to
GND; Resistor to 3.3V; NC. (Resistor should be 0-ohm).
3.3V single-ended control input
(REXT)
Note:
1) internal 100Kohm pull-up
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Pin Name
Type
Description
Analog connection to external compo- Acceptable connections to OC_3 pin are: short to 3.3V or to
OC_3
nent or supply
GND; NC.
OC_0
OC_1
EQ_0
EQ_1
Control pins are to enable Jitter elimination ꢀeatures.
Output and Input jitter elimination
control
For normal operation these pins are tied GND or to VDD. Please
see the truth tables ꢀor more inꢀormation.
Truth Table 1
(2)
(1)
(1)
(1)
OC_3
OC_2
OC_1
OC_0
Vswing (mV)
Pre/De-emphasis
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
500
600
750
0
0
0
1000
500
500
500
500
400
400
400
400
1000
1000
1000
1000
0
0
1.5dB
3.5dB
6dB
0
3.5dB
6dB
9dB
0
-3.5dB
-6dB
-9dB
Truth Table 2
(2)
(1)
EQ_1
EQ_0
Equalization @ 1.25GHz (dB)
0
0
1
0
1
3
0
6
1
9
1
12
Notes:
1. Internal 100Kohm pull-up
2. For 42-TQFN (ZHE) package, there is an internal connection to GND.
3. For 48-TQFN (ZDE) package, external connection is allowed and there is an internal 100KW pull-up.
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Electrical Characteristics
Table 3: Power Supplies and Temperature Range
Symbol
Parameter
Min
Nom
Max
Units
Comments
V
3.3V Power Supply
3.0
3.3
3.6
V
DD
Total current ꢀrom VDD
3.3V supply when de-
emphasis/pre-emphasis is
set to 0dB.
I
Max Current
100
mA
CC
Standby Current Consump-
tion
I
2
mA
OE# = HIGH
CCQ
Case temperature range ꢀor
operation with spec.
TCASE
-40
85
Celsius
Table 4: OE# Description
OE#
Device State
Comments
Differential input buffers and output buffers Normal ꢀunctioning state ꢀor IN_D to
Asserted (low voltage)
enabled. Input impedance = 50Ω
OUT_D level shifing ꢀunction.
Low-power state.
Intended ꢀor lowest power condition when:
•
•
No display is plugged in or
Differential input buffers and termination
are disabled. Differential inputs are in a
high-impedance state.
e level shiꢀed data path is disabled
Unasserted (high voltage)
HPD_SINK input and HPD_SOURCE# out-
put are not affected by OE# SCL_SOURCE,
SCL_SINK, SDA_SOURCE and SDA_SINK
signals and ꢀunctions are not affected by
OE#
OUT_D level-shifing outputs are disabled.
OUT_D level-shifing outputs are in high-
impedence state.
Internal bias currents are turned off.
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Table 5: Differential Input Characteristics for IN_D and RX_IN signals
Symbol
Parameter
Min
Nom Max Units Comments
Tbit is determined by the display mode. Nomi-
nal bit rate ranges ꢀrom 250Mbps to 2.5Gbps
per lane. Nominal Tbit at 2.5Gbps=400ps.
360ps=400ps-10%
Tbit
Unit Interval
360
ps
VRX-DIFFp-p=2'|VRX-D+ x VRX-D-|
Applies to IN_D and RX_IN signals
Differential Input Peak to
Peak Voltage
V
0.175
0.8
1.200
100
V
RX-DIFFp-p
Minimum Eye Width at
IN_D input pair
e level shifer may add a maximum oꢀ 0.02UI
jitter
T
Tbit
RX-EYE
VCM-AC-pp = |VRX-D+ + VRX-D-|/2 - VRX-
CM-DC.
AC Peak
VRX-CM-DC = DC(avg) oꢀ|VRX-D+ + VRX-
D-|/2
V
mV
CM-AC-pp
Common Mode Input
Voltage
VCM-AC-pp includes all ꢀrequencies above 30
kHz.
Required IN_D+ as well as IN_D- DC imped-
ance (50Ω ± 20% tolerance).
Z
40
0
50
60
Ω
RX-DC
Intended to limit power-up stress on chipset's
PCIE output buffers.
V
2.0
V
RX-Bias
Differential inputs must be in a high impedance
state when OE# is HIGH.
Z
100
kΩ
RX-HIGH-Z
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
TMDS Outputs
e level shifer's TMDS outputs are required to meet HDMI 1.3 specifications.
e HDMI 1.3 Specification is assumed to be the correct reꢀerence in instances where this document conflicts with the HDMI 1.3
specification.
Table 6: Differential Output Characteristics for TMDS_OUT signals
Symbol
Parameter
Min
Nom
Max
Units
Comments
AVDD is the DC ter-
mination voltage in the
HDMI or DVI Sink.
Single-ended
high level output AVDD-10mV
voltage
V
AVDD
AVDD+10mV
V
H
AVDD is nominally 3.3V
Single-ended
low level output
voltage
e open-drain output
pulls down ꢀrom AVDD.
V
V
AVDD-600mV AVDD-500mV AVDD-400mV
V
V
L
Swing down from
TMDS termination volt-
age (3.3V ± 10%)
Single-ended out-
put swing voltage
450mV
500mV
600mV
50
SWING
Measured with TMDS
outputs pulled up to
AVDD Max (3.6V)
through 50Ω resistors.
Single-ended
current in high-Z
state
I
µA
OFF
Max Rise/Fall time
@2.7Gbps = 148ps. 125ps
= 148-15%
T
T
Rise time
Fall time
125ps
125ps
0.4Tbit
0.4Tbit
ps
ps
R
F
Max Rise/Fall time
@2.7Gbps = 148ps. 125ps
= 148-15%
is differential skew
budget is in addition
to the skew presented
between D+ and D-
paired input pins. HDMI
revision 1.3 source allow-
able intra-pair skew is
0.15Tbit.
Intra-pair
T
30
ps
SKEW-INTRA
differential skew
is lane-to-lane skew
budget is in addition to
skew between differential
input pairs
Inter-pair lane-
to-lane output
skew
T
T
100
25
ps
ps
SKEW-INTER
Jitter budget ꢀor TMDS
signals as they pass
through the level shifer.
25ps = 0.056 Tbit at 2.25
Gb/s
Jitter added to
TMDS signals
JIT
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
TMDS output oscillation elimination
e inputs do not incorporate a squelch circuit. ereꢀore, we reccomend the input to be externally biased to prevent output oscilla-
tion. Pericom reccomends to add a 1.5Kohm pull-up to the CLK- input ꢀor each oiꢀ the video input ports.
VBIAS
3.3V
R
INT
R
INT
R
T
SS
DMDP
Receiver
TMDS
Driver
1.5Kohm
AV
DD
SS
R
T
TMDS Input Fail-Saꢀe Recommendation
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Table 8: HPD Characteristics
Symbol
Parameter
Min
Nom
Max
Units
Comments
Input High Level
Low-speed input changes state on cable plug/
unplug
V
V
2.0
5.0
5.3
V
IH-HPD
HPD_sink Input Low
Level
0
0.8
70
V
IL-HPD
IN-HPD
HPD_sink Input
Leakage Current
Measured with HPD_sink at V
max
IH-HPD
I
μA
and V
min
IL-HPD
HPD_Source# Output
V
High-Level, I
-200μA
=
0.8
0
1.1
0.1
V
V
V
= 3.3V 10%
DD
OH-HPDB
OH
HPD_Source# Output
V
Low-Level, I
=
OL
OL-HPDB
200μA
HPD_Source# to
HPD_source propaga-
tion delay
Time ꢀrom HPD_sink changing state to
HPD_source# changing state. Includes
HPD_source rise/ꢀall time
T
T
200
20
ns
ns
HPD
HPD_Source# rise/
ꢀall time
Time required to transition ꢀrom V
OH-HPD
to V
OL-HPD OH-HPD
1
RF-HPDB
to V
or ꢀrom V
OL-HPD
Table 9: OE# Input and DDC_EN
Symbol
Parameter
Min
Nom Max
Units
Comments
TMDS enable input changes state on
cable plug/unplug
V
V
Input High Level
Input Low Level
2.0
0
V
V
IH
IL
DD
0.8
10
V
Measured with input at V
max and
IH-EN
I
Input Leakage Current
μA
IN
V
min
IL-EN
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
V = 0.1V to 0.9V to isolated
I
DD
DD
|I
|
Input leakage current
0.1
2
µA
lkg
DDC ports
C
Input/output capacitance
Switch resistance
V = 0V
7.5
25
pF
IO
I
R
ON
I
O
= 3mA, V = 0.4V
50
ohm
V
O
(2)
(3)
V
Switch output voltage
V = 3.3V, I = 100µA
I
1.5
2.0
2.5
PASS
I
Table 10: Termination Resistors
Symbol
Parameter
Min
Nom
Max
Units
Comments
HPD_sink input pull-
down resistor.
Guarantees HPD_sink is LOW when no
display is plugged in.
R
80K
100k
120K
Ω
HPD
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Recommended Power Supply Decoupling Circuit
Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1µF decoupling capacitors on
each VDD pins oꢀ our part, there are ꢀour 0.1µF decoupling capacitors are put in Figure 1 with an assumption oꢀ only ꢀour VDD pins
on our part, iꢀ there is more or less VDD pins on our Pericom parts, the number oꢀ 0.1µF decoupling capacitors should be adjusted
according to the actual number oꢀ VDD pins. On top oꢀ 0.1µF decoupling capacitors on each VDD pins, it is recommended to put a
10µF decoupling capacitor near our part’s VDD, it is ꢀor stabilizing the power supply ꢀor our part. Ferrite bead is also recommended
ꢀor isolating the power supply ꢀor our part and other power supplies in other parts oꢀ the circuit. But, it is optional and depends on the
power supply conditions oꢀ other circuits.
10µF
Ferrite Bead
From main
power supply
0.1µF
V DD
0.1µF
V DD
P e ric om P a rt
0.1µF
V DD
V DD
0.1µF
Figure 1 Recommended Power Supply Decoupling Circuit Diagram
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
Requirements on the Decoupling Capacitors
ere is no special requirement on the material oꢀ the capacitors. Ceramic capacitors are generally being used with typically materi-
als oꢀ X5R or X7R.
Layout and Decoupling Capacitor Placement Consideration
i. Each 0.1µF decoupling capacitor should be placed as close as possible to each V pin.
DD
ii.
V
and GND planes should be used to provide a low impedance path for power and ground.
DD
iii. Via holes should be placed to connect to V and GND planes directly.
DD
iv. Trace should be as wide as possible
v. Trace should be as short as possible.
vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria.
vii. 10µF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1µF capacitors.
viii. Avoid the large current circuit placed close to our part; especially when it is shared the same V and GND planes. Since large
DD
current flowing on our V or GND planes will generate a potential variation on the V or GND of our part.
DD
DD
V DD P la ne
Bypass noise
Power Flow
0.1uF
G N D P la ne
P e ric om P a rt
Figure 2 Layout and Decoupling Capacitor Placement Diagram
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
DATE: 02/12/09
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Refer JEDEC MO-220/VKKD
3. Thermal Pad Soldering Area
4. Depending on the method of lead termination at the edge of the package,
pull back maybe present.
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD48)
5. Recommended Land Pattern is for reference only.
REVISION: D
DOCUMENT CONTROL #: PD-2045
09-0117
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PI3VDP411LST
Digital Video Level Shifer ꢀor dual mode DP
signals w/ inverting buffer ꢀor HPD signal
UNIT: mm
DATE: 02/11/09
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZB48
REVISION: A
DOCUMENT CONTROL #: PD-2080
09-0091
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
•
Ordering Information
Ordering Code
Package Code
Package Description
PI3VDP411LSTZDE
PI3VDP411LSTZBE
Notes:
ZD
ZB
48-pin Pb-ꢀree & Green, TQFN
48-pin Pb-ꢀree & Green, TQFN
• ermal characteristics can be ꢀound on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8906G
07/12/11
11-0083
13
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