CY62157DV30_10 [CYPRESS]
8-Mbit (512K x 16) MoBL Static RAM; 8兆位（ 512K ×16 ）的MoBL静态RAM
| 型号： | CY62157DV30_10 |
| 厂家： | 
CYPRESS |
| 描述： | 8-Mbit (512K x 16) MoBL Static RAM |
| 文件： | 总15页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157DV30 MoBL®
8-Mbit (512K x 16) MoBL Static RAM
This is ideal for providing More Battery Life (MoBL®) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
Features
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
■ Very high speed: 55 ns
■ Wide voltage range: 2.20 V–3.60 V
■ Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
■ Ultra-low active power
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
❐ Typical active current: 1.5 mA @ f = 1 MHz
❐ Typical active current: 12 mA @ f = fmax
■ Ultra-low standby power
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power-down when deselected
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table for a complete description
of read and write modes.
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Available in Pb-free and non Pb-free 48-ball fine ball grid
array (FBGA), and Pb-free 44-pin thin small outline package
(TSOPII) package
Functional Description
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA-IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
512K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
A2
A1
A0
COLUMN DECODER
BHE
WE
CE2
CE
1
OE
BLE
Power-down
Circuit
Cypress Semiconductor Corporation
Document #: 38-05392 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 25, 2010
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CY62157DV30 MoBL®
Contents
Product Portfolio ..............................................................3
Pin Configuration ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................5
Data Retention Waveform.................................................5
Switching Waveforms ......................................................7
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definition ...........................................11
Package Diagram ............................................................12
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
Document #: 38-05392 Rev. *J
Page 2 of 15
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CY62157DV30 MoBL®
Product Portfolio
Power Dissipation
VCC Range (V)
Operating ICC, (mA)
f = 1MHz f = fmax
Speed
(ns)
Standby ISB2,
Product
Range
(A)
Min
2.2
Typ[1]
Max
3.6
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
CY62157DV30LL Industrial
3.0
55, 70
1.5
3
12
15
2
8
Pin Configuration[2, 3, 4]
48-Ball FBGA Pinout
44-pin TSOP II Pinout
Top View
Top View
1
2
4
3
5
6
44
43
42
41
40
39
38
1
2
3
4
5
6
A
A
5
4
A
A
3
6
A
A
A
2
CE2
OE
BLE
0
1
A
B
C
A
A
7
OE
BHE
BLE
I/O
15
2
A
1
A
A
I/O BHE
8
CE1 I/O
0
A
3
4
0
CE
I/O
7
0
A
A
6
I/O I/O
I/O
I/O
2
5
9
10
1
37
36
35
34
33
I/O
8
I/O
I/O
1
2
14
13
12
I/O
9
Vcc
A
V
I/O
I/O
3
A17
D
E
F
SS
7
11
10
11
12
13
I/O
3
CC
V
SS
I/O
4
I/O
V
V
SS
Vss
I/O
DNU
A
V
V
I/O
I/O
CC
CC
16
12
4
32
31
30
29
28
27
I/O
I/O
11
10
I/O
14
15
16
5
A
A
15
I/O
I/O
I/O
14
13
5
14
6
I/O
I/O
6
9
8
I/O
I/O
7
A
8
WE 17
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
18
A
A
18
9
19
20
21
22
26
25
A
A
10
17
A
A
9
A
A
A18
NC
10
11
8
A
A
12
16
11
A
A
24
23
15
A
A
13
14
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating.
4. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *J
Page 3 of 15
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CY62157DV30 MoBL®
Output current into outputs (LOW) .............................. 20 mA
Maximum Ratings
Static discharge voltage........................................... >2001 V
(per MIL-STD-883, Method 3015)
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch-up current ......................................................>200 mA
Storage temperature ............................... –65 °C to + 150 °C
Operating Range
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Ambient
Temperature
(TA)
7]
[
Supply voltage to ground
potential.......................................... –0.3 V to VCC(max) + 0.3 V
Device
Range
VCC
CY62157DV30LL
Industrial
–40 °C to +85 °C 2.20 V to
3.60 V
DC voltage applied to outputs
in High-Z State[5, 6] ......................... –0.3 V to VCC(max) + 0.3 V
DC input voltage[5, 6]....................... –0.3 V to VCC(max) + 0.3 V
Electrical Characteristics Over the Operating Range
-55
Min Typ[8]
Parameter
Description
Test Conditions
Unit
Max
VOH
Output HIGH
voltage
IOH = –0.1 mA
OH = –1.0 mA
IOL = 0.1 mA
OL = 2.1 mA
VCC = 2.20 V
VCC = 2.70 V
VCC = 2.20 V
VCC = 2.70 V
2.0
2.4
–
–
–
–
–
–
–
–
–
–
–
–
V
V
I
VOL
VIH
VIL
Output LOW
voltage
0.4
V
I
–
0.4
V
Input HIGH
voltage
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.8
2.2
–0.3
–0.3
–1
VCC + 0.3
VCC + 0.3
0.6
V
V
Input LOW voltage VCC = 2.2 V to 2.7 V
CC = 2.7 V to 3.6 V
V
V
0.8
V
IIX
Input leakage
current
GND < VI < VCC
+1
A
Ind’l
Ind’l
IOZ
ICC
Output leakage
current
GND < VO < VCC, Output disabled
–1
–
+1
A
VCC Operating
supply current
f = fMAX = 1/tRC
f = 1 MHz
VCC = VCCmax LL
IOUT = 0 mA
CMOS levels
–
–
12
15
3
mA
mA
LL
1.5
ISB1
Automatic
LL
2
8
A
CE1 > VCC 0.2 V or CE2 < 0.2 V or
(BHE and BLE)
Ind’l
Power-down
current — CMOS
inputs
> VCC 0.2 V,
V
IN > VCC – 0.2 V, VIN < 0.2 V
f = fMAX (Address and Data Only),
f = 0 (OE, WE), VCC = 3.60V
ISB2
Automatic
Power-down
current -CMOS
inputs
LL
–
2
8
A
CE1 > VCC– 0.2 V or CE2 < 0.2 V,
Ind’l
> VCC 0.2 V,
(BHE and BLE)
V
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Capacitance
Parameter[9, 10]
Description
Input capacitance
Output capacitance
Test Conditions
Max
Unit
CIN
TA = 25 °C, f = 1 MHz,
CC = VCC(typ)
10
10
pF
pF
V
COUT
Notes
5.
6.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min.)
IH(max)
= V +0.75 V for pulse duration less than 20 ns.
CC
7. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
9. Tested initially and after any design or process changes that may affect these parameters.
10. The input capacitance on the CE pin of the FBGA package and on the BHE pin of the 44TSOPII package is 15 pF.
2
Document #: 38-05392 Rev. *J
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CY62157DV30 MoBL®
Thermal Resistance
Parameter[11]
Description
Test Conditions
FBGA
TSOP II
Unit
JA
Thermal resistance
(Junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
39.3
35.62
C / W
JC
Thermal resistance
(Junction to case)
9.69
9.13
C / W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
90%
10%
90%
10%
GND
Rise Time = 1 V/ns
R2
30 pF / 50 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50 V
16667
15385
8000
3.0 V
1103
1554
645
Unit
R1
R2
RTH
VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min Typ[12] Max
Unit
1.5
–
–
–
–
4
V
VCC= 1.5 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (
Ind’l
A
> VCC 0.2 V,
BHE and BLE)
IN > VCC – 0.2 V or VIN < 0.2 V
V
[11]
tCDR
Chip deselect to data
retention time
0
–
–
–
–
ns
ns
[13]
tR
Operation recovery time
55
Data Retention Waveform[14]
DATA RETENTION MODE
> 1.5 V
VCC, min.
tR
VCC, min.
tCDR
VDR
VCC
CE or
1
BHE.BLE
or
CE2
Notes
11. Tested initially and after any design or process changes that may affect these parameters
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
13. Full device operation requires linear V ramp from V to V
> 100 s or stable at V > 100 s.
CC(min.)
CC
DR
CC(min.)
14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05392 Rev. *J
Page 5 of 15
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CY62157DV30 MoBL®
Switching Characteristics Over the Operating Range
55 ns
Unit
Parameter[15]
Description
Min
Max
Read Cycle
tRC
Read cycle time
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
CE1 LOW and CE2 HIGH to data valid
OE LOW to data valid
OE LOW to LOW Z[16]
OE HIGH to High Z[16, 17]
CE1 LOW and CE2 HIGH to Low Z[16]
CE1 HIGH and CE2 LOW to High Z[16, 17]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH and CE2 LOW to Power-down
BLE/BHE LOW to data valid
10
–
55
25
–
–
5
–
20
–
10
–
20
–
0
tPD
–
55
55
–
tDBE
tLZBE
tHZBE
Write Cycle[18]
tWC
–
BLE/BHE LOW to Low Z[16]
BLE/BHE HIGH to HIGH Z[16, 17]
10
–
20
Write cycle time
55
40
40
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
–
tHA
–
tSA
0
–
tPWE
tBW
40
40
25
0
–
BLE/BHE LOW to write end
Data set-up to write end
Data hold from write end
WE LOW to High-Z[16, 17]
WE HIGH to Low-Z[16]
–
tSD
–
tHD
–
tHZWE
tLZWE
–
20
–
10
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels
CC(typ)
of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ.)
OL OH
16. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
device.
17. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
18. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a write
1
IL
IL
2
IH
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05392 Rev. *J
Page 6 of 15
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CY62157DV30 MoBL®
Switching Waveforms
Figure 1. Read Cycle 1 (Address Transition Controlled)[19, 20]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 2. Read Cycle 2 (OE Controlled)[20, 21]
ADDRESS
t
RC
CE
t
PD
t
HZCE
CE
t
ACE
BHE/BLE
t
DBE
t
HZBE
t
LZBE
OE
t
HZOE
t
DOE
LZOE
HIGH IMPEDANCE
t
HIGH
IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
ICC
ISB
t
PU
50%
50%
SUPPLY
CURRENT
Notes
19. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
1
IL
IL
2
IH
20. WE is HIGH for read cycle.
21. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05392 Rev. *J
Page 7 of 15
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CY62157DV30 MoBL®
Switching Waveforms (continued)
Figure 3. Write Cycle 1 (WE Controlled)[22, 23, 24]
t
WC
ADDRESS
CE1
t
SCE
CE2
t
t
HA
AW
t
t
PWE
SA
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID DATA
DATA I/O
See note 25
t
HZOE
Figure 4. Write Cycle 2 (CE1 or CE2 Controlled)[22, 23, 24]
t
WC
ADDRESS
t
SCE
CE
CE
1
2
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID DATA
DATA I/O
See note 25
t
HZOE
Notes
22. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE = VIH. All signals must be ACTIVE to initiate
1
2
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write
23. Data I/O is high-impedance if OE = V
.
IH
24. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high-impedance state.
1
2
IH
25. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05392 Rev. *J
Page 8 of 15
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CY62157DV30 MoBL®
Switching Waveforms (continued)
Figure 5. Write Cycle 3 (WE Controlled, OE LOW)[26]
t
WC
ADDRESS
CE1
t
SCE
CE2
t
BW
BHE/BLE
t
t
HA
AW
t
t
PWE
SA
WE
t
t
HD
SD
See note 27
DATA I/O
VALID DATA
t
LZWE
t
HZWE
Figure 6. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[26]
t
WC
ADDRESS
CE1
CE2
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
See note 27
DATA I/O
VALID DATA
Notes
26. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high-impedance state
1
2
IH
27. During this period, the I/Os are in output state and input signals should not be applied
Document #: 38-05392 Rev. *J
Page 9 of 15
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CY62157DV30 MoBL®
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power-down
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X
L
X
X
X
X
High Z
Deselect/Power-down
X
X
X
X
H
H
High Z
Deselect/Power-down
L
H
H
L
L
L
Data out (I/O0–I/O15
)
Read (upper byte and Lower byte)
Read (lower byte only)
Active (ICC
Active (ICC
)
)
L
H
H
L
H
L
Data out (I/O0–I/O7);
High Z (I/O8–I/O15
)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data out (I/O8–I/O15
Read (upper byte only)
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
Output disabled
Output disabled
L
Data in (I/O0–I/O15
Data in (I/O0–I/O7);
High Z (I/O8–I/O15
)
Write (upper byte and Lower byte)
Write (lower byte only)
L
H
)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data in (I/O8–I/O15
Write (upper byte only)
Active (ICC
)
)
Document #: 38-05392 Rev. *J
Page 10 of 15
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CY62157DV30 MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
55
CY62157DV30LL-55BVI
CY62157DV30LL-55BVXI
CY62157DV30LL-55ZSXI
51-85150 48-ball (6 x 8 x 1 mm) FBGA
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Industrial
Ordering Code Definition
LL
55 XXX X
CY
V30
621
5
7D
Temperature Grade
I = Industrial
Package Type :
ZSX : TSOP II (Pb-free)
BVX : VFBGA (Pb-free)
BV : VFBGA
Speed Grade
Low Power
Voltage = 3.0
Bus Width = X16
D = 130nm Technology
Density = 8Mbit
MoBL SRAM Family
Company ID: CY = Cypress
Document #: 38-05392 Rev. *J
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CY62157DV30 MoBL®
Package Diagram
Figure 7. 48-Pin VFBGA (51-85150)
51-85150 *F
Figure 8. 44-pin TSOP II (51-85087)
51-85087 *C
Document #: 38-05392 Rev. *J
Page 12 of 15
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CY62157DV30 MoBL®
Acronyms
Document Conventions
Units of Measure
Acronym
CMOS
I/O
Description
complementary metal oxide semiconductor
input/output
Symbol
°C
Unit of Measure
degrees Celsius
SRAM
static random access memory
very fine ball grid array
A
microamperes
milliampere
megahertz
nanoseconds
picofarads
volts
VFBGA
TSOP
mA
MHz
ns
thin small outline package
pF
V
ohms
W
watts
Document #: 38-05392 Rev. *J
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CY62157DV30 MoBL®
Document History Page
Document Title: CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL Static RAM
Document Number: 38-05392
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
126316
131013
133115
211601
05/22/03
11/19/03
01/24/04
See ECN
HRT
New Data Sheet
*A
*B
*C
CBD/LDZ Change from Advance to Preliminary
CBD
AJU
Minor Change: Change MPN and upload.
Change from Preliminary to Final
Changed Marketing part number from CY62157DV to CY62157DV30 in the title
and in the Ordering Information table
Added footnotes 4, 5 and 11
Modified footnote 8 to include ramp time and wait time
Removed MAX value for VDR on Data Retention Characteristics table
Changed ordering code for Pb-free parts
Modified voltage limits in Maximum Ratings section
*D
236628
See ECN
SYT/AJU Added 45-ns and 70-ns Speed Bins
Added Automotive product information
*E
*F
257349
372074
See ECN
See ECN
PCI
Added test condition for 45 ns part (footnote #13 on page 4)
SYT
Added Pb-Free Automotive Part in the Ordering Information
Removed ‘Preliminary’ tag from Automotive Information
*G
433838
See ECN
ZSD
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Updated the thermal resistance table
Updated the ordering information table and changed the package name column
to package diagram
*H
*I
488954
See ECN
VKN
VKN
Added Automotive-A product
Updated ordering Information table
2897932 03/23/2010
3068300 10/25/2010
Removed 45ns speed bin
Removed Auto-A/Auto-E information
Removed 48-Pin TSOP I information
Updated ordering Information table
Updated package diagrams.
*J
RAME
Removed CY62157DV30LL-70BVXI part related info
Updated ISB1/ISB2 CCDR test conditions to reflect byte power down feature
/I
Updated datasheet as per new template
Added Acronyms and Units of Measure table
Added Ordering Code Definition
Updated Package Diagram to 51-85150 *F
Converted all tablenotes into footnotes
Document #: 38-05392 Rev. *J
Page 14 of 15
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CY62157DV30 MoBL®
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© Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05392 Rev. *J
Revised October 25, 2010
Page 15 of 15
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their
respective holders.
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