CY62157E [CYPRESS]
8-Mbit (512K x 16) Static RAM; 8兆位（ 512K ×16 ）静态RAM
| 型号： | CY62157E |
| 厂家： | 
CYPRESS |
| 描述： | 8-Mbit (512K x 16) Static RAM |
| 文件： | 总12页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157E MoBL®
8-Mbit (512K x 16) Static RAM
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE1
HIGH or CE2 LOW or both BHE and BLE are HIGH). The input
or output pins (IO0 through IO15) are placed in a high
impedance state when:
Features
• Very high speed: 45 ns
— Industrial: –40°C to +85°C
— Automotive-E: –40°C to +125°C
• Wide voltage range: 4.5V–5.5V
• Ultra low standby power
• Deselected (CE1HIGH or CE2 LOW)
• Outputs are disabled (OE HIGH)
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA (Industrial)
• Ultra low active power
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE1 LOW, CE2 HIGH and WE
LOW)
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra low standby power
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7), is
written into the location specified on the address pins (A0
through A18). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO8 through IO15) is written into the location
specified on the address pins (A0 through A18).
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then
data from memory appears on IO8 to IO15. See the “Truth
Table” on page 9 for a complete description of read and write
modes.
Functional Description[1]
The CY62157E is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS
A
10
A
A
9
8
7
A
A
A
A
A
6
5
4
3
512K x 16
RAM Array
IO –IO
0
7
IO –IO
8
15
A
A
A
2
1
0
COLUMN DECODER
CE
CE
2
1
BHE
WE
PowerDown
Circuit
CE
CE
2
1
BHE
BLE
OE
BLE
Notes
1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05695 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 27, 2007
CY62157E MoBL®
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1 MHz f = fmax
Typ[2]
Max
Speed
(ns)
V
CC Range (V)
Standby, ISB2
Product
Range
(µA)
Min
4.5
4.5
Typ[2]
5.0
Max
5.5
Typ[2]
Max
25
Typ[2]
Max
8
CY62157ELL
CY62157ELL
Industrial
45
55
1.8
1.8
3
4
18
18
2
2
Automotive
5.0
5.5
35
30
Pin Configuration
The following pictures show the TSOP II and VFBGA pinouts.[3, 4]
TSOP II
VFBGA
Top View
Top View
1
4
3
2
5
6
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
A8
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
2
CE2
OE
BLE
0
1
A
A
A
IO
BHE
CE1 IO
B
C
4
3
0
2
8
CE
IO0
A
A
6
IO
IO
IO
IO
5
10
1
9
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
Vcc
A
V
IO
IO
3
A17
NC
D
E
F
SS
7
11
A
V
IO
Vss
IO
IO
IO
CC
16
12
4
5
A
A
15
IO
IO
14
13
14
6
A
A
WE
A18
A17
A16
A15
A14
G
H
IO
NC
WE
IO
13
12
15
7
A9
A10
A11
A12
A13
A
A
A
A
A18
NC
10
9
11
8
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
3. NC pins are not connected on the die.
4. The 44-pin TSOP II package has only one chip enable (CE) pin.
Document #: 38-05695 Rev. *E
Page 2 of 12
CY62157E MoBL®
DC Input Voltage[5, 6]........................................–0.5V to 6.0V
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Static Discharge Voltage ..........................................> 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch up Current ....................................................> 200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential .......................................................... –0.5V to 6.0V
Ambient
Temperature
[7]
Device
Range
VCC
DC Voltage Applied to Outputs
CY62157ELL Industrial
–40°C to +85°C 4.5V to 5.5V
in High-Z State[5, 6]........................................... –0.5V to 6.0V
Automotive –40°C to +125°C
Electrical Characteristics
Over the Operating Range
45 ns (Industrial)
55 ns (Automotive)
Unit
Parameter
Description
Test Conditions
IOH = –1 mA
Min Typ[2]
Max
Min Typ[2]
Max
VOH
Output HIGH
Voltage
2.4
2.4
V
V
VOL
VIH
VIL
IIX
Output LOW
Voltage
IOL = 2.1 mA
0.4
0.4
VCC + 0.5
0.8
Input HIGH
Voltage
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
GND < VI < VCC
2.2
–0.5
–1
VCC + 0.5 2.2
V
Input LOW
Voltage
0.8
+1
+1
–0.5
–4
V
Input Leakage
Current
+4
µA
µA
mA
IOZ
ICC
Output Leakage GND < VO < VCC, Output Disabled –1
Current
–4
+4
VCC Operating
Supply
Current
f = fmax = 1/tRC VCC = VCC(max)
18
25
3
18
35
4
IOUT = 0 mA
CMOS levels
f = 1 MHz
1.8
1.8
ISB1
Automatic CE
Power Down
Current —
2
8
2
30
µA
µA
CE1 > VCC − 0.2V or CE2 < 0.2V,
V
IN > VCC – 0.2V, VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
CMOS Inputs
V
CC = VCC(max)
CE1 > VCC – 0.2V or CE2 < 0.2V,
IN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
[8]
ISB2
Automatic CE
Power Down
Current —
2
8
2
30
V
CMOS Inputs
Capacitance[9]
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
10
10
pF
pF
COUT
Notes
5.
6.
V
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
V
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
8. Only chip enables (CE and CE ) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I / I spec. Other inputs can be left floating.
1
2
SB2 CCDR
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05695 Rev. *E
Page 3 of 12
CY62157E MoBL®
Thermal Resistance [9]
Parameter
Description
Test Conditions
TSOP II
VFBGA
Unit
ΘJA
Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,
(Junction to Ambient) two-layer printed circuit board
77
72
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
13
8.86
°C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
3V
90%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
Values
1800
990
Unit
Ω
R1
R2
Ω
RTH
VTH
639
Ω
1.77
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ [2] Max Unit
VDR
VCC for Data Retention
Data Retention Current
2
V
[8]
ICCDR
CE < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Industrial
8
µA
VCC=2V, CE1> VCC – 0.2V or
2
Automotive
30
[9]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[10]
tR
Operation Recovery Time
tRC
Data Retention Waveform[11]
Figure 2. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
tR
VCC(min)
tCDR
> 2V
VDR
VCC
CE1 or
BHE.BLE
or
CE2
Notes
10. Full device operation requires linear V ramp from V to V
11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
Document #: 38-05695 Rev. *E
Page 4 of 12
CY62157E MoBL®
Switching Characteristics
Over the Operating Range[12, 13]
45 ns (Industrial)
55 ns (Automotive)
Unit
Parameter
Description
Min
Max
Min
Max
Read Cycle
45
55
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
55
tAA
Address to Data Valid
10
10
tOHA
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW-Z[14]
OE HIGH to High-Z[14, 15]
CE1 LOW and CE2 HIGH to Low-Z[14]
CE1 HIGH and CE2 LOW to High-Z[14, 15]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH and CE2 LOW to Power Down
BLE/BHE LOW to Data Valid
tACE
45
22
55
25
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
18
18
20
20
tPD
45
45
55
55
tDBE
tLZBE
tHZBE
Write Cycle[16]
BLE/BHE LOW to Low-Z[14]
BLE/BHE HIGH to HIGH-Z[14, 15]
10
45
10
55
18
20
tWC
tSCE
tAW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
35
35
40
40
tHA
0
0
0
0
tSA
tPWE
tBW
35
35
25
0
40
40
25
0
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z[14, 15]
WE HIGH to Low-Z[14]
tSD
tHD
tHZWE
tLZWE
18
20
10
10
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.
CC(typ)
OL OH
13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
14. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
15. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
16. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V , and CE = V . All signals must be active to initiate a
1
IL
IL
2
IH
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
Document #: 38-05695 Rev. *E
Page 5 of 12
CY62157E MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[17, 18]
Figure 3. Read Cycle No. 1
t
RC
ADDRESS
DATA OUT
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[18, 19]
Figure 4. Read Cycle No. 2
ADDRESS
CE1
tRC
tPD
t
HZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
ICC
ISB
tPU
VCC
SUPPLY
CURRENT
50%
50%
Notes
17. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .
IH
1
IL
IL
2
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05695 Rev. *E
Page 6 of 12
CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[16, 20, 21]
Figure 5. Write Cycle No. 1
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
NOTE 22
VALID DATA
tHZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)[16, 20, 21]
Figure 6. Write Cycle No. 2
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
VALID DATA
DATA IO
NOTE 22
tHZOE
Notes
20. Data IO is high impedance if OE = V
.
IH
21. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
22. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05695 Rev. *E
Page 7 of 12
CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[21]
Figure 7. Write Cycle No. 3
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 22
DATA IO
VALID DATA
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[21]
Figure 8. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
NOTE 22
DATA IO
VALID DATA
Document #: 38-05695 Rev. *E
Page 8 of 12
CY62157E MoBL®
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
Mode
Power
Deselect/Power Down
Deselect/Power Down
Deselect/Power Down
Read
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X
L
X
X
X
X
High-Z
X
X
X
X
H
H
High-Z
L
H
H
L
L
L
Data Out (IO0–IO15
)
Active (ICC
)
)
L
H
H
L
H
L
Data Out (IO0–IO7);
High-Z (IO8–IO15
Read
Active (ICC
)
L
H
H
L
L
H
High-Z (IO0–IO7);
Data Out (IO8–IO15
Read
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High-Z
High-Z
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (IO0–IO15)
L
H
Data In (IO0–IO7);
High-Z (IO8–IO15)
Write
L
H
L
X
L
H
High-Z (IO0–IO7);
Data In (IO8–IO15)
Write
Active (ICC
)
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62157ELL-45ZSXI
CY62157ELL-55ZSXE
45
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Industrial
55
Automotive
CY62157ELL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Document #: 38-05695 Rev. *E
Page 9 of 12
CY62157E MoBL®
Package Diagrams
Figure 9. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85150-*D
Document #: 38-05695 Rev. *E
Page 10 of 12
CY62157E MoBL®
Package Diagrams (continued)
Figure 10. 44-Pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05695 Rev. *E
Page 11 of 12
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157E MoBL®
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05695
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
291273
457689
See ECN
See ECN
PCI
New data sheet
*A
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
*C
467033
See ECN
NXR
VKN
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz
Changed the ISB2(typ) value of Automotive from 5 µA to 1.8 µA
Modified footnote #4 to include current limit
Updated the Ordering Information table
569114
925501
See ECN
See ECN
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
*D
*E
VKN
VKN
Added footnote #9 related to ISB2 and ICCDR
Added footnote #14 related AC timing parameters
1045801 See ECN
Converted Automotive specs from preliminary to final
Document #: 38-05695 Rev. *E
Page 12 of 12
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