CY62157ELL-45ZSXIT [CYPRESS]
Standard SRAM, 512KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | CY62157ELL-45ZSXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总19页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157E MoBL®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512
K × 16) Static RAM
when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE
are HIGH). The input or output pins (I/O0 through I/O15) are
placed in a high impedance state when:
Features
■ Very high speed: 45 ns
❐ Industrial: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■ Deselected (CE1HIGH or CE2 LOW)
■ Outputs are disabled (OE HIGH)
■ Wide voltage range: 4.5 V–5.5 V
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A (Industrial)
■ Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
■ Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Ultra low standby power
A
18). If Byte High Enable (BHE) is LOW, then data from I/O pins
■ Easy memory expansion with CE1, CE2 and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of read and write modes.
■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Functional Description
The CY62157E is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
addresses are not toggling. Place the device into standby mode
The CY62157E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
A
9
8
7
A
A
A
A
A
6
5
4
3
512K x 16
RAM Array
I/O –I/O
0
7
I/O –I/O
8
15
A
A
A
2
1
0
COLUMN DECODER
CE
CE
2
1
BHE
WE
PowerDown
Circuit
CE
CE
2
BHE
BLE
1
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05695 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 9, 2017
CY62157E MoBL®
Contents
Product Portfolio ..............................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................12
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Package Diagrams ..........................................................14
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure .......................................................16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC® Solutions ......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 38-05695 Rev. *N
Page 2 of 19
CY62157E MoBL®
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1 MHz f = fmax
Speed
(ns)
VCC Range (V)
Product
Range
Standby, ISB2 (A)
Min
4.5
4.5
Typ[1]
5.0
Max
5.5
Typ[1]
Max
3
Typ[1]
Max
25
Typ[1]
Max
8
CY62157ELL
CY62157ELL
Industrial
45
55
1.8
1.8
18
18
2
2
Automotive
5.0
5.5
4
35
30
Pin Configurations
Figure 1. 44-pin TSOP II pinout [2, 3]
Figure 2. 48-ball VFBGA pinout [2]
Top View
Top View
1
2
4
3
5
6
A5
A6
A7
OE
BHE
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
2
A
CE2
OE
BLE
0
1
A
B
C
A
A
I/O BHE
CE1 I/O
4
3
0
8
CE
I/O0
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A
A
6
I/O I/O
I/O
I/O
2
5
9
10
1
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
9
Vcc
A
V
I/O
I/O
3
A17
NC
D
E
F
SS
7
10
11
12
13
14
15
16
17
18
19
20
21
22
11
A
V
I/O
Vss
I/O
I/O
CC
16
12
4
A
A
15
I/O
I/O
I/O
14
13
5
14
6
A
A
WE
A18
A17
A16
A15
A14
G
H
I/O
I/O
NC
WE
13
12
15
7
A9
A10
A11
A12
A13
A
A
A
A
A18
NC
10
9
11
8
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
2. NC pins are not connected on the die.
3. The 44-pin TSOP II package has only one chip enable (CE) pin.
Document Number: 38-05695 Rev. *N
Page 3 of 19
CY62157E MoBL®
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch up Current ....................................................> 200 mA
Storage Temperature .............................. –65 °C to + 150 °C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Operating Range
Ambient
Temperature
[6]
Supply Voltage to Ground
Potential .........................................................–0.5 V to 6.0 V
Device
Range
VCC
CY62157ELL
Industrial –40 °C to +85 °C 4.5 V to 5.5 V
Automotive –40 °C to +125 °C
DC Voltage Applied to Outputs
in High Z State [4, 5].........................................–0.5 V to 6.0 V
DC Input Voltage [4, 5] .....................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Test Conditions
Unit
Min Typ [7]
Max
Min Typ [7]
Max
VOH
Output HIGH
Voltage
VCC = 4.5 V
IOH = –1 mA
2.4
–
–
–
–
–
2.4
–
–
–
–
–
V
VCC = 5.5 V
IOL = 2.1 mA
IOH = –0.1 mA
3.4 [8]
0.4
3.4 [8]
0.4
VOL
VIH
VIL
IIX
Output LOW
Voltage
–
–
V
V
Input HIGH
Voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
GND < VI < VCC
2.2
–0.5
–1
–
–
–
–
VCC + 0.5
2.2
–0.5
–4
–
–
–
–
VCC + 0.5
Input LOW
Voltage
0.8
+1
+1
0.8
+4
+4
V
Input Leakage
Current
A
A
mA
IOZ
ICC
Output Leakage GND < VO < VCC, Output Disabled –1
Current
–4
VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCC(max)
OUT = 0 mA
CMOS levels
–
–
18
25
3
–
–
18
35
4
I
f = 1 MHz
1.8
1.8
[9]
ISB1
Automatic CE
Power Down
Current – CMOS
Inputs
–
–
2
8
–
2
30
A
A
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = VCC(max)
[9]
ISB2
Automatic CE
Power Down
Current – CMOS
Inputs
2
8
–
2
30
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
4.
5.
V
V
= –2.0 V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
8. Please note that the maximum V limit does not exceed minimum CMOS V of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
OH
IH
minimum V of 3.5V, please refer to Application Note AN6081 for technical details and options you may consider.
IH
9. Chip enables (CE and CE ) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I / I / I spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
Document Number: 38-05695 Rev. *N
Page 4 of 19
CY62157E MoBL®
Capacitance
Parameter [10]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [10]
Description
Test Conditions
44-pin TSOP II 48-ball VFBGA Unit
θJA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
55.84
48.34
°C/W
θJC
Thermal resistance
(junction to case)
15.79
8.78
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
OUTPUT
3 V
90%
90%
10%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
RTH
VTH
Parameters
Values
1800
990
Unit
R1
R2
RTH
VTH
639
1.77
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05695 Rev. *N
Page 5 of 19
CY62157E MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ [11] Max
Unit
V
VDR
VCC for Data Retention
Data Retention Current
2
–
–
–
–
–
–
8
[12]
ICCDR
Industrial
A
VCC = 2 V, CE1 > VCC – 0.2 V or
CE < 0.2 V
or
2
Automotive
30
,
(BHE and BLE) > VCC – 0.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V
[13]
tCDR
Chip Deselect to Data
Retention Time
0
–
–
ns
ns
[14]
tR
Operation Recovery Time
CY62157ELL-45
CY62157ELL-55
45
55
–
–
–
–
Data Retention Waveform
Figure 4. Data Retention Waveform [15]
DATA RETENTION MODE
VCC(min)
tR
VCC(min)
tCDR
> 2 V
VDR
VCC
CE1 or
BHE.BLE
or
CE2
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
12. Chip enables (CE and CE ) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear V ramp from V to V > 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05695 Rev. *N
Page 6 of 19
CY62157E MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Industrial)
55 ns (Automotive)
Unit
Parameter [16, 17]
Description
Min
Max
Min
Max
Read Cycle
45
–
–
45
–
55
–
–
55
–
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
10
–
10
–
tOHA
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[18]
OE HIGH to High Z[18, 19]
CE1 LOW and CE2 HIGH to Low Z[18]
CE1 HIGH and CE2 LOW to High Z[18, 19]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH and CE2 LOW to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[18]
tACE
45
22
–
55
25
–
–
–
tDOE
tLZOE
5
–
5
–
tHZOE
18
–
20
–
tLZCE
10
–
10
–
tHZCE
18
–
20
–
tPU
0
–
–
0
–
–
tPD
45
45
–
55
55
–
tDBE
tLZBE
10
–
10
–
tHZBE
BLE/BHE HIGH to High Z[18, 19]
18
20
Write Cycle [20, 21]
45
–
–
–
–
–
–
–
–
–
55
–
–
–
–
–
–
–
–
–
tWC
tSCE
tAW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
35
35
40
40
tHA
0
0
0
0
tSA
tPWE
tBW
35
35
25
0
40
40
25
0
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[18, 19]
WE HIGH to Low Z[18]
tSD
tHD
–
–
tHZWE
tLZWE
18
–
20
–
10
10
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels
CC(typ)
of 0 to V
, and output loading of the specified I /I as shown in the Figure 3 on page 5.
CC(typ)
OL OH
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
18. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
19. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
20. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V , and CE = V . All signals must be active to initiate a write
1
IL
IL
2
IH
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
21. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of t and t
SD
.
HZWE
Document Number: 38-05695 Rev. *N
Page 7 of 19
CY62157E MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [22, 23]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [23, 24]
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
22. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .
IH
1
IL
IL
2
23. WE is HIGH for read cycle.
24. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document Number: 38-05695 Rev. *N
Page 8 of 19
CY62157E MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [25, 26, 27]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
tHD
OE
tSD
DATA I/O
NOTE 28
VALID DATA
tHZOE
Notes
25. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V , and CE = V . All signals must be active to initiate
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
26. Data I/O is high impedance if OE = V
.
IH
27. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *N
Page 9 of 19
CY62157E MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled) [29, 30, 31]
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
VALID DATA
DATA I/O
NOTE 32
tHZOE
Notes
29. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V , and CE = V . All signals must be active to initiate
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
30. Data I/O is high impedance if OE = V
.
IH
31. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
32. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *N
Page 10 of 19
CY62157E MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [33, 34]
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 35
DATA I/O
VALID DATA
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [33]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
NOTE 35
DATA I/O
VALID DATA
Notes
33. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
34. The minimum write cycle pulse width should be equal to sum of t and t
.
SD
HZWE
35. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05695 Rev. *N
Page 11 of 19
CY62157E MoBL®
Truth Table
CE1
CE2
X[36]
L
WE
X
OE
X
BHE BLE
Inputs/Outputs
High Z
Mode
Deselect/Power Down
Deselect/Power Down
Deselect/Power Down
Read
Power
H
X
X
H
L
X
X
H
L
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X[36]
X
X
High Z
X[36] X[36]
X
X
High Z
L
L
H
H
H
L
Data Out (I/O0–I/O15
)
Active (ICC
Active (ICC
)
)
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15
Read
)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15
Read
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (I/O0–I/O15)
L
H
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC
)
Note
36. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05695 Rev. *N
Page 12 of 19
CY62157E MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62157ELL-45ZSXI
CY62157ELL-55ZSXE
CY62157ELL-55BVXE
45
51-85087 44-pin TSOP Type II (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85150 48-ball VFBGA (Pb-free)
Industrial
55
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
E
XX XX
5
LL
-
X
X
621
CY
7
Temperature Range: X = I or E
I = Industrial; E = Automotive-E
Pb-free
Package Type: XX = ZS or BV
ZS = 44-pin TSOP II
BV = 48-ball VFBGA
Speed Grade: XX = 45 ns or 55 ns
Low Power
Process Technology: E = 90 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: 621= MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05695 Rev. *N
Page 13 of 19
CY62157E MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 38-05695 Rev. *N
Page 14 of 19
CY62157E MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05695 Rev. *N
Page 15 of 19
CY62157E MoBL®
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
MHz
µA
µs
OE
Output Enable
RAM
SRAM
TTL
Random Access Memory
Static Random Access Memory
Transistor-Transistor Logic
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
Write Enable
mA
mm
ns
TSOP
VFBGA
WE
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05695 Rev. *N
Page 16 of 19
CY62157E MoBL®
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512 K × 16) Static RAM
Document Number: 38-05695
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
291273
457689
See ECN
See ECN
PCI
New data sheet.
*A
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
467033
See ECN
NXR
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz
Changed the ISB2(typ) value of Automotive from 5 A to 1.8 A
Modified footnote #4 to include current limit
Updated the Ordering Information table
*C
*D
569114
925501
See ECN
See ECN
VKN
VKN
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
Added footnote #9 related to ISB2 and ICCDR
Added footnote #14 related AC timing parameters
*E
*F
1045801
2934396
See ECN
06/03/10
VKN
VKN
Converted Automotive specs from preliminary to final
Added footnote #23 related to chip enable
Updated Package Diagrams.
Updated to new template.
*G
*H
3110053
3269641
12/14/2010
05/30/2011
PRAS
RAME
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
Removed the note “For best practice recommendations, please refer to the
Cypress application note AN1064, SRAM System Guidelines.” and its
reference in Functional Description.
Updated Electrical Characteristics.
Updated Data Retention Characteristics.
Added Acronyms and Units of Measure.
Updated to new template.
*I
4013958
06/05/2013
MEMJ
Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH parameter
and added maximum value corresponding to that Test Condition.
Added Note 8 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “VCC = 5.5 V, IOH = –0.1 mA”.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
*J
4102449
08/22/2013
VINI
Updated Switching Characteristics:
Updated Note 17.
Updated to new template.
Document Number: 38-05695 Rev. *N
Page 17 of 19
CY62157E MoBL®
Document History Page (continued)
Document Title: CY62157E MoBL®, 8-Mbit (512 K × 16) Static RAM
Document Number: 38-05695
Orig. of
Rev.
ECN No.
Issue Date
Description of Change
Updated Switching Characteristics:
Change
*K
4410589
06/17/2014
VINI
Added Note 21 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 34 and referred the same note in Figure 9.
Completing Sunset Review.
*L
4576475
4795615
11/21/2014
06/12/2015
VINI
VINI
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*M
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of θJA corresponding to 44-pin TSOP II package from 77 °C/W
to 55.84 °C/W.
Changed value of θJA corresponding to 48-ball VFBGA package from 72 °C/W
to 48.34 °C/W.
Changed value of θJC corresponding to 44-pin TSOP II package from 13 °C/W
to 15.79 °C/W.
Changed value of θJC corresponding to 48-ball VFBGA package from
8.86 °C/W to 8.78 °C/W.
Updated AC Test Loads and Waveforms:
Updated Figure 3:
Replaced “V” with “VTH” in bottom part.
Updated to new template.
Completing Sunset Review.
*N
5962457
11/09/2017 AESATMP8 Updated logo and Copyright.
Document Number: 38-05695 Rev. *N
Page 18 of 19
CY62157E MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05695 Rev. *N
Revised November 9, 2017
Page 19 of 19
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