CY62157ESL-45ZSXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62157ESL-45ZSXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157ESL MoBL®
8-Mbit (512K × 16) Static RAM
8-Mbit (512K
× 16) Static RAM
addresses are not toggling. Place the device into standby mode
when deselected (CE HIGH or both BHE and BLE are HIGH).
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), both the Byte High Enable and
the Byte Low Enable are disabled (BHE, BLE HIGH), or during
an active write operation (CE LOW and WE LOW).
Features
■ Very high speed: 45 ns
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical Standby current: 2 A
❐ Maximum Standby current: 8 A
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18).
■ Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 44-pin thin small outline package (TSOP) II
package
Functional Description
The CY62157ESL device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
10
9
8
7
A
A
A
A
6
5
4
3
512K × 16
RAM Array
I/O –I/O
0
7
I/O –I/O
8
15
A
A
A
2
1
0
COLUMN DECODER
CE
BHE
WE
CE
PowerDown
Circuit
BHE
BLE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-43141 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 10, 2016
CY62157ESL MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagram ............................................................13
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC® Solutions ......................................................17
Cypress Developer Community .................................17
Technical Support .....................................................17
Document Number: 001-43141 Rev. *H
Page 2 of 17
CY62157ESL MoBL®
Pin Configurations
Figure 1. 44-pin TSOP II pinout (Top View)
A5
A6
A7
OE
BHE
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
A9
A10
A11
A12
A13
Product Portfolio
Power Dissipation
Operating ICC, (mA)
Speed
(ns)
Product
Range
VCC Range (V) [1]
Standby, ISB2 (A)
f = 1MHz
f = fmax
Typ[2]
Max
Typ [2]
Max
Typ [2]
Max
CY62157ESL Industrial 2.2 V–3.6 V and 4.5 V–5.5 V
45
1.8
3
18
25
2
8
Notes
1. Datasheet specifications are not guaranteed for V in the range of 3.6 V to 4.5 V.
CC
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V, and V = 5 V, T = 25 °C.
CC
CC
A
Document Number: 001-43141 Rev. *H
Page 3 of 17
CY62157ESL MoBL®
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..................................>2001 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch up Current .....................................................>200mA
Storage Temperature ............................... –65 °C to +150 °C
Operating Range
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Ambient
Temperature
[5]
Device
Range
VCC
Supply Voltage to Ground Potential ...............–0.5 V to 6.0 V
CY62157ESL
Industrial –40 °C to +85 °C 2.2 V–3.6 V,
DC Voltage Applied to Outputs
in High Z State [3, 4] ........................................–0.5 V to 6.0 V
and
4.5 V–5.5 V
DC Input Voltage [3, 4] ....................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
45 ns
Unit
Parameter
VOH
Description
Output high voltage
Test Conditions
Min
2.0
2.4
2.4
–
Typ [6]
Max
2.2 < VCC < 2.7 IOH = –0.1 mA
2.7 < VCC < 3.6 IOH = –1.0 mA
4.5 < VCC < 5.5 IOH = –1.0 mA
4.5 < VCC < 5.5 IOH = –0.1 mA
2.2 < VCC < 2.7 IOL = 0.1 mA
2.7 < VCC < 3.6 IOL = 2.1 mA
4.5 < VCC < 5.5 IOL = 2.1 mA
2.2 < VCC < 2.7
–
–
–
–
V
–
–
–
3.4 [7]
VOL
VIH
VIL
Output low voltage
Input high voltage
Input low voltage
–
–
0.4
V
V
V
–
–
0.4
–
–
0.4
1.8
2.2
2.2
–0.3
–0.3
–0.5
–1
–1
–
–
VCC + 0.3
VCC + 0.3
VCC + 0.5
0.6
2.7 < VCC < 3.6
–
4.5 < VCC < 5.5
–
2.2 < VCC < 2.7
–
2.7 < VCC < 3.6
–
0.8
4.5 < VCC < 5.5
–
0.8
IIX
Input leakage current
GND < VI < VCC
–
+1
A
A
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VO < VCC, Output Disabled
–
+1
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
OUT = 0 mA,
CMOS levels
18
1.8
25
mA
I
–
3
[8]
[8]
ISB1
Automatic CE power down
current – CMOS inputs
–
2
2
8
8
A
A
CE > VCC 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
ISB2
Automatic CE power down
current – CMOS inputs
–
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
V
=
f = 0, VCC
CC(max)
Notes
3.
4.
V
V
(min) = –2.0 V for pulse durations less than 20 ns.
IL
(max) = V + 0.75 V for pulse durations less than 20 ns.
IH
CC
5. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V, and V = 5 V, T = 25 °C.
CC
CC
A
7. Please note that the maximum V limit does not exceed minimum CMOS V of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
OH
IH
minimum V of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
IH
8. Chip enable (CE) needs to be tied to CMOS levels to meet the I
/I
/ I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
Document Number: 001-43141 Rev. *H
Page 4 of 17
CY62157ESL MoBL®
Capacitance
Parameter [9]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [9]
Description
Test Conditions
TSOP II
Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
57.92
C/W
JC
Thermal resistance
(junction to case)
17.44
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
90%
90%
VCC
OUTPUT
10%
10%
Fall Time = 1 V/ns
GND
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V
16667
15385
8000
3.0 V
1103
1554
645
5.0 V
Unit
R1
R2
1800
990
RTH
VTH
639
1.20
1.75
1.77
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-43141 Rev. *H
Page 5 of 17
CY62157ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.5
–
Typ [10]
Max
Unit
V
–
2
2
–
5
8
[10]
CE > VCC – 0.2 V,
IN > VCC – 0.2 V or
VCC = 1.5 V
VCC = 2.0 V
A
ICCDR
V
–
VIN < 0.2 V
[12]
tCDR
Chip deselect to data retention
time
0
–
–
–
–
ns
ns
[13]
tR
Operation recovery time
45
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5 V
VCC
t
t
R
CDR
CE or
BHE.BLE[14]
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V, and V = 5 V, T = 25 °C.
CC
CC
A
11. Chip enable (CE) needs to be tied to CMOS levels to meet the I /I
/ I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear V ramp from V to V > 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-43141 Rev. *H
Page 6 of 17
CY62157ESL MoBL®
Switching Characteristics
Over the Operating Range
45 ns
Unit
Parameter [15, 16]
Description
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
10
–
tACE
45
22
–
–
tDOE
OE LOW to data valid
OE LOW to Low Z [17]
OE HIGH to High Z [17, 18]
CE LOW to Low Z [17]
CE HIGH to High Z [17, 18]
tLZOE
5
–
tHZOE
18
–
tLZCE
10
–
tHZCE
18
–
tPU
CE LOW to power up
0
–
–
tPD
CE HIGH to power down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z [17, 19]
BLE/BHE HIGH to High Z [17, 18]
45
45
–
tDBE
tLZBE
5
–
tHZBE
18
Write Cycle [20, 21]
tWC
Write cycle time
45
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
tSA
CE LOW to write end
35
35
ns
ns
Address setup to write end
Address hold from write end
Address setup to write start
0
0
ns
ns
tPWE
tBW
tSD
WE pulse width
35
35
25
0
ns
ns
ns
ns
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
tHD
WE LOW to High Z [17, 18]
WE HIGH to Low Z [17]
18
–
ns
ns
–
tHZWE
tLZWE
10
Notes
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
17. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
18. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
19. If both byte enables are toggled together, this value is 10 ns.
20. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
21. The minimum write cycle pulse width for Write Cycle No. 4 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 001-43141 Rev. *H
Page 7 of 17
CY62157ESL MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [22, 23]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [23, 24]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
22. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V
.
IL
IL
23. WE is HIGH for read cycle.
24. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-43141 Rev. *H
Page 8 of 17
CY62157ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [25, 26]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
DATA I/O
t
HD
t
SD
NOTE 27
DATAIN
Figure 7. Write Cycle No. 2 (CE Controlled) [25, 26]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 27
Notes
25. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
26. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-43141 Rev. *H
Page 9 of 17
CY62157ESL MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (BHE/BLE Controlled) [28, 29]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 30
DATAIN
DATA I/O
tLZWE
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW) [28, 29, 31]
t
WC
Address
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
Data In Valid
Data I/O
t
LZWE
Notes
28. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
29. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
30. During this period, the I/Os are in output state. Do not apply input signals.
31. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 001-43141 Rev. *H
Page 10 of 17
CY62157ESL MoBL®
Truth Table
CE
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Deselect/power down
Deselect/power down
Read
Power
H
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
X[32]
L
X
X
H
H
High Z
)
H
L
L
L
Data Out (I/O0–I/O15
)
)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
High-Z
High-Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (I/O0–I/O15
)
)
L
H
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
32. The ‘X’ (Don’t care) state for the Chip enable in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-43141 Rev. *H
Page 11 of 17
CY62157ESL MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
45
CY62157ESL-45ZSXI
51-85087 44-pin TSOP Type II (Pb-free)
Industrial
Ordering Code Definitions
E
45 ZS
X
I
SL -
5
CY 621
7
Temperature Range: I = Industrial
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: SL = 3 V typical; 5 V typical
Process Technology: E = 90 nm
Bus width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-43141 Rev. *H
Page 12 of 17
CY62157ESL MoBL®
Package Diagram
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-43141 Rev. *H
Page 13 of 17
CY62157ESL MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
CE
Byte High Enable
Unit of Measure
Byte Low Enable
Chip Enable
°C
MHz
A
mA
ns
degrees Celsius
megahertz
microampere
milliampere
nanosecond
ohm
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
OE
Output Enable
SRAM
TSOP
WE
Static Random Access Memory
Thin Small Outline Package
Write Enable
pF
V
picofarad
volt
W
watt
Document Number: 001-43141 Rev. *H
Page 14 of 17
CY62157ESL MoBL®
Document History Page
Document Title: CY62157ESL MoBL®, 8-Mbit (512K × 16) Static RAM
Document Number: 001-43141
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
1875228
See ECN
VKN /
AESA
New data sheet.
Added Contents.
*A
2943752
06/03/2010
VKN
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Truth Table:
Added Note 32 and referred the same note in CE column.
Updated Package Diagram.
Added Sales, Solutions, and Legal Information.
*B
*C
3109266
3295175
12/13/2010
06/29/2011
PRAS
RAME
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
Updated Functional Description:
Remove reference to AN1064 SRAM system guidelines.
Updated Electrical Characteristics:
Updated Note 8 (Added ISB1) and referred the same note in ISB1 parameter.
Updated Capacitance:
Added Note 9 and referred the same note in parameter column.
Updated Thermal Resistance:
Added Note 9 and referred the same note in parameter column.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Updated Ordering Code Definitions.
Added Units of Measure.
*D
3904207
02/14/2013
MEMJ
Updated Switching Waveforms:
Updated Figure 6 (Removed OE signal).
Updated Figure 7 (Removed OE signal).
Removed the Note “Data I/O is high impedance if OE = VIH.” and its reference
in Figure 6, Figure 7.
Removed the figure “Write Cycle 3: WE controlled, OE LOW”.
Updated Figure 8 (Removed “OE LOW” in caption only).
Removed the Note “Data I/O is high impedance if OE = VIH.” and its reference
in Figure 8.
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *E.
*E
4019657
06/04/2013
MEMJ
Updated Functional Description:
Updated description.
Updated Electrical Characteristics:
Added one more Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA” for VOH
parameter and added maximum value corresponding to that Test Condition.
Added Note 7 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA”.
*F
4100920
4576406
08/21/2013
01/16/2015
VINI
VINI
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
Updated to new template.
*G
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 21 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Figure 9.
Added Note 31 and referred the same note in Figure 9.
Document Number: 001-43141 Rev. *H
Page 15 of 17
CY62157ESL MoBL®
Document History Page (continued)
Document Title: CY62157ESL MoBL®, 8-Mbit (512K × 16) Static RAM
Document Number: 001-43141
Orig. of
Rev.
ECN No.
Issue Date
Description of Change
Updated Thermal Resistance:
Change
*H
5169392
03/10/2016
VINI
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter from 77 °C/W to 57.92 °C/W.
Changed value of JC parameter from 13 C/W to 17.44 C/W.
Updated to new template.
Completing Sunset Review.
Document Number: 001-43141 Rev. *H
Page 16 of 17
CY62157ESL MoBL®
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© Cypress Semiconductor Corporation 2008–2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
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is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
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and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43141 Rev. *H
Revised March 10, 2016
Page 17 of 17
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. Corporation.
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